ixp425_if_npe.c revision 1.7
1 /* $NetBSD: ixp425_if_npe.c,v 1.7 2008/01/19 22:10:14 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.7 2008/01/19 22:10:14 dyoung Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include "bpfilter.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/device.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/socket.h> 60 #include <sys/endian.h> 61 #include <sys/ioctl.h> 62 63 #include <machine/bus.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <arm/xscale/ixp425reg.h> 75 #include <arm/xscale/ixp425var.h> 76 #include <arm/xscale/ixp425_qmgr.h> 77 #include <arm/xscale/ixp425_npevar.h> 78 #include <arm/xscale/ixp425_if_npereg.h> 79 80 #include <dev/mii/miivar.h> 81 82 #include "locators.h" 83 84 struct npebuf { 85 struct npebuf *ix_next; /* chain to next buffer */ 86 void *ix_m; /* backpointer to mbuf */ 87 bus_dmamap_t ix_map; /* bus dma map for associated data */ 88 struct npehwbuf *ix_hw; /* associated h/w block */ 89 uint32_t ix_neaddr; /* phys address of ix_hw */ 90 }; 91 92 struct npedma { 93 const char* name; 94 int nbuf; /* # npebuf's allocated */ 95 bus_dmamap_t m_map; 96 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 97 bus_dmamap_t buf_map; 98 bus_addr_t buf_phys; /* phys addr of buffers */ 99 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 100 }; 101 102 struct npe_softc { 103 struct device sc_dev; 104 struct ethercom sc_ethercom; 105 struct mii_data sc_mii; 106 bus_space_tag_t sc_iot; 107 bus_dma_tag_t sc_dt; 108 bus_space_handle_t sc_ioh; /* MAC register window */ 109 bus_space_handle_t sc_miih; /* MII register window */ 110 struct ixpnpe_softc *sc_npe; /* NPE support */ 111 int sc_unit; 112 int sc_phy; 113 struct callout sc_tick_ch; /* Tick callout */ 114 struct npedma txdma; 115 struct npebuf *tx_free; /* list of free tx buffers */ 116 struct npedma rxdma; 117 int rx_qid; /* rx qid */ 118 int rx_freeqid; /* rx free buffers qid */ 119 int tx_qid; /* tx qid */ 120 int tx_doneqid; /* tx completed qid */ 121 struct npestats *sc_stats; 122 bus_dmamap_t sc_stats_map; 123 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 124 }; 125 126 /* 127 * Per-unit static configuration for IXP425. The tx and 128 * rx free Q id's are fixed by the NPE microcode. The 129 * rx Q id's are programmed to be separate to simplify 130 * multi-port processing. It may be better to handle 131 * all traffic through one Q (as done by the Intel drivers). 132 * 133 * Note that the PHY's are accessible only from MAC A 134 * on the IXP425. This and other platform-specific 135 * assumptions probably need to be handled through hints. 136 */ 137 static const struct { 138 const char *desc; /* device description */ 139 int npeid; /* NPE assignment */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .imageid = IXP425_NPE_B_IMAGEID, 153 .regbase = IXP425_MAC_A_HWBASE, 154 .regsize = IXP425_MAC_A_SIZE, 155 .miibase = IXP425_MAC_A_HWBASE, 156 .miisize = IXP425_MAC_A_SIZE, 157 .rx_qid = 4, 158 .rx_freeqid = 27, 159 .tx_qid = 24, 160 .tx_doneqid = 31 161 }, 162 { .desc = "IXP NPE-C", 163 .npeid = NPE_C, 164 .imageid = IXP425_NPE_C_IMAGEID, 165 .regbase = IXP425_MAC_B_HWBASE, 166 .regsize = IXP425_MAC_B_SIZE, 167 .miibase = IXP425_MAC_A_HWBASE, 168 .miisize = IXP425_MAC_A_SIZE, 169 .rx_qid = 12, 170 .rx_freeqid = 28, 171 .tx_qid = 25, 172 .tx_doneqid = 31 173 }, 174 }; 175 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 176 177 static __inline uint32_t 178 RD4(struct npe_softc *sc, bus_size_t off) 179 { 180 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 181 } 182 183 static __inline void 184 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 185 { 186 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 187 } 188 189 static int npe_activate(struct npe_softc *); 190 #if 0 191 static void npe_deactivate(struct npe_softc *); 192 #endif 193 static int npe_ifmedia_change(struct ifnet *ifp); 194 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 195 static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 196 static void npe_getmac(struct npe_softc *sc, u_char *eaddr); 197 static void npe_txdone(int qid, void *arg); 198 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 199 struct mbuf *); 200 static void npe_rxdone(int qid, void *arg); 201 static int npeinit(struct ifnet *); 202 static void npestart(struct ifnet *); 203 static void npestop(struct ifnet *, int); 204 static void npewatchdog(struct ifnet *); 205 static int npeioctl(struct ifnet * ifp, u_long, void *); 206 207 static int npe_setrxqosentry(struct npe_softc *, int classix, 208 int trafclass, int qid); 209 static int npe_updatestats(struct npe_softc *); 210 #if 0 211 static int npe_getstats(struct npe_softc *); 212 static uint32_t npe_getimageid(struct npe_softc *); 213 static int npe_setloopback(struct npe_softc *, int ena); 214 #endif 215 216 static int npe_miibus_readreg(struct device *, int, int); 217 static void npe_miibus_writereg(struct device *, int, int, int); 218 static void npe_miibus_statchg(struct device *); 219 220 static int npe_debug; 221 #define DPRINTF(sc, fmt, ...) do { \ 222 if (npe_debug) printf(fmt, __VA_ARGS__); \ 223 } while (0) 224 #define DPRINTFn(n, sc, fmt, ...) do { \ 225 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 228 #define NPE_TXBUF 128 229 #define NPE_RXBUF 64 230 231 #ifndef ETHER_ALIGN 232 #define ETHER_ALIGN 2 /* XXX: Ditch this */ 233 #endif 234 235 /* NB: all tx done processing goes through one queue */ 236 static int tx_doneqid = -1; 237 238 static int npe_match(struct device *, struct cfdata *, void *); 239 static void npe_attach(struct device *, struct device *, void *); 240 241 CFATTACH_DECL(npe, sizeof(struct npe_softc), 242 npe_match, npe_attach, NULL, NULL); 243 244 static int 245 npe_match(struct device *parent, struct cfdata *cf, void *arg) 246 { 247 struct ixpnpe_attach_args *na = arg; 248 249 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 250 } 251 252 static void 253 npe_attach(struct device *parent, struct device *self, void *arg) 254 { 255 struct npe_softc *sc = (void *)self; 256 struct ixpnpe_attach_args *na = arg; 257 struct ifnet *ifp; 258 u_char eaddr[6]; 259 260 aprint_naive("\n"); 261 aprint_normal(": Ethernet co-processor\n"); 262 263 sc->sc_iot = na->na_iot; 264 sc->sc_dt = na->na_dt; 265 sc->sc_npe = na->na_npe; 266 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 267 sc->sc_phy = na->na_phy; 268 269 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 270 memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 271 272 callout_init(&sc->sc_tick_ch, 0); 273 274 if (npe_activate(sc)) { 275 aprint_error("%s: Failed to activate NPE (missing " 276 "microcode?)\n", sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* 281 * XXXSCW: This is bogus - the NPE may not have been configured for 282 * XXXSCW: Ethernet yet. We must check for a property set by 283 * XXXSCW: board-specific code. 284 */ 285 npe_getmac(sc, eaddr); 286 287 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 288 ether_sprintf(eaddr)); 289 290 ifp = &sc->sc_ethercom.ec_if; 291 ifmedia_init(&sc->sc_mii.mii_media, 0, npe_ifmedia_change, 292 npe_ifmedia_status); 293 294 if (sc->sc_phy != IXPNPECF_PHY_DEFAULT) { 295 sc->sc_mii.mii_ifp = ifp; 296 sc->sc_mii.mii_readreg = npe_miibus_readreg; 297 sc->sc_mii.mii_writereg = npe_miibus_writereg; 298 sc->sc_mii.mii_statchg = npe_miibus_statchg; 299 sc->sc_ethercom.ec_mii = &sc->sc_mii; 300 301 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 302 (sc->sc_phy > IXPNPECF_PHY_DEFAULT) ? 303 sc->sc_phy : MII_PHY_ANY, 304 MII_OFFSET_ANY, MIIF_NOISOLATE); 305 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 306 } else { 307 /* Assume direct connection to a 100mbit switch */ 308 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX, 0,0); 309 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX); 310 } 311 312 ifp->if_softc = sc; 313 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 314 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 315 ifp->if_start = npestart; 316 ifp->if_ioctl = npeioctl; 317 ifp->if_watchdog = npewatchdog; 318 ifp->if_init = npeinit; 319 ifp->if_stop = npestop; 320 IFQ_SET_READY(&ifp->if_snd); 321 322 if_attach(ifp); 323 ether_ifattach(ifp, eaddr); 324 } 325 326 /* 327 * Compute and install the multicast filter. 328 */ 329 static void 330 npe_setmcast(struct npe_softc *sc) 331 { 332 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 333 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 334 int i; 335 336 if (ifp->if_flags & IFF_PROMISC) { 337 memset(mask, 0, ETHER_ADDR_LEN); 338 memset(addr, 0, ETHER_ADDR_LEN); 339 } else if (ifp->if_flags & IFF_ALLMULTI) { 340 static const uint8_t allmulti[ETHER_ADDR_LEN] = 341 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 342 all_multi: 343 memcpy(mask, allmulti, ETHER_ADDR_LEN); 344 memcpy(addr, allmulti, ETHER_ADDR_LEN); 345 } else { 346 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 347 struct ether_multistep step; 348 struct ether_multi *enm; 349 350 memset(clr, 0, ETHER_ADDR_LEN); 351 memset(set, 0xff, ETHER_ADDR_LEN); 352 353 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 354 while (enm != NULL) { 355 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 356 ifp->if_flags |= IFF_ALLMULTI; 357 goto all_multi; 358 } 359 360 for (i = 0; i < ETHER_ADDR_LEN; i++) { 361 clr[i] |= enm->enm_addrlo[i]; 362 set[i] &= enm->enm_addrlo[i]; 363 } 364 365 ETHER_NEXT_MULTI(step, enm); 366 } 367 368 for (i = 0; i < ETHER_ADDR_LEN; i++) { 369 mask[i] = set[i] | ~clr[i]; 370 addr[i] = set[i]; 371 } 372 } 373 374 /* 375 * Write the mask and address registers. 376 */ 377 for (i = 0; i < ETHER_ADDR_LEN; i++) { 378 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 379 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 380 } 381 } 382 383 static int 384 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 385 const char *name, int nbuf, int maxseg) 386 { 387 bus_dma_segment_t seg; 388 int rseg, error, i; 389 void *hwbuf; 390 size_t size; 391 392 memset(dma, 0, sizeof(dma)); 393 394 dma->name = name; 395 dma->nbuf = nbuf; 396 397 size = nbuf * sizeof(struct npehwbuf); 398 399 /* XXX COHERENT for now */ 400 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 401 1, &rseg, BUS_DMA_NOWAIT); 402 if (error) { 403 printf("%s: unable to allocate memory for %s h/w buffers, " 404 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 405 } 406 407 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 408 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 409 if (error) { 410 printf("%s: unable to map memory for %s h/w buffers, " 411 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 412 free_dmamem: 413 bus_dmamem_free(sc->sc_dt, &seg, rseg); 414 return error; 415 } 416 dma->hwbuf = (void *)hwbuf; 417 418 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 419 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 420 if (error) { 421 printf("%s: unable to create map for %s h/w buffers, " 422 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 423 unmap_dmamem: 424 dma->hwbuf = NULL; 425 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 426 goto free_dmamem; 427 } 428 429 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 430 BUS_DMA_NOWAIT); 431 if (error) { 432 printf("%s: unable to load map for %s h/w buffers, " 433 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 434 destroy_dmamap: 435 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 436 goto unmap_dmamem; 437 } 438 439 /* XXX M_TEMP */ 440 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 441 if (dma->buf == NULL) { 442 printf("%s: unable to allocate memory for %s s/w buffers\n", 443 sc->sc_dev.dv_xname, dma->name); 444 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 445 error = ENOMEM; 446 goto destroy_dmamap; 447 } 448 449 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 450 for (i = 0; i < dma->nbuf; i++) { 451 struct npebuf *npe = &dma->buf[i]; 452 struct npehwbuf *hw = &dma->hwbuf[i]; 453 454 /* calculate offset to shared area */ 455 npe->ix_neaddr = dma->buf_phys + 456 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 457 KASSERT((npe->ix_neaddr & 0x1f) == 0); 458 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, 1, 459 MCLBYTES, 0, 0, &npe->ix_map); 460 if (error != 0) { 461 printf("%s: unable to create dmamap for %s buffer %u, " 462 "error %u\n", sc->sc_dev.dv_xname, dma->name, i, 463 error); 464 /* XXXSCW: Free up maps... */ 465 return error; 466 } 467 npe->ix_hw = hw; 468 } 469 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 470 BUS_DMASYNC_PREWRITE); 471 return 0; 472 } 473 474 #if 0 475 static void 476 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 477 { 478 int i; 479 480 /* XXXSCW: Clean this up */ 481 482 if (dma->hwbuf != NULL) { 483 for (i = 0; i < dma->nbuf; i++) { 484 struct npebuf *npe = &dma->buf[i]; 485 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 486 } 487 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 488 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 489 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 490 } 491 if (dma->buf != NULL) 492 free(dma->buf, M_TEMP); 493 memset(dma, 0, sizeof(*dma)); 494 } 495 #endif 496 497 static int 498 npe_activate(struct npe_softc *sc) 499 { 500 bus_dma_segment_t seg; 501 int unit = sc->sc_unit; 502 int error, i, rseg; 503 void *statbuf; 504 505 /* load NPE firmware and start it running */ 506 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 507 if (error != 0) 508 return error; 509 510 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 511 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 512 printf("%s: Cannot map registers 0x%x:0x%x\n", 513 sc->sc_dev.dv_xname, npeconfig[unit].regbase, 514 npeconfig[unit].regsize); 515 return ENOMEM; 516 } 517 518 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 519 /* 520 * The PHY's are only accessible from one MAC (it appears) 521 * so for other MAC's setup an additional mapping for 522 * frobbing the PHY registers. 523 */ 524 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 525 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 526 printf("%s: Cannot map MII registers 0x%x:0x%x\n", 527 sc->sc_dev.dv_xname, npeconfig[unit].miibase, 528 npeconfig[unit].miisize); 529 return ENOMEM; 530 } 531 } else 532 sc->sc_miih = sc->sc_ioh; 533 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 534 if (error != 0) 535 return error; 536 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 537 if (error != 0) 538 return error; 539 540 /* setup statistics block */ 541 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 542 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 543 if (error) { 544 printf("%s: unable to allocate memory for stats block, " 545 "error %u\n", sc->sc_dev.dv_xname, error); 546 return error; 547 } 548 549 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 550 &statbuf, BUS_DMA_NOWAIT); 551 if (error) { 552 printf("%s: unable to map memory for stats block, " 553 "error %u\n", sc->sc_dev.dv_xname, error); 554 return error; 555 } 556 sc->sc_stats = (void *)statbuf; 557 558 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 559 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 560 &sc->sc_stats_map); 561 if (error) { 562 printf("%s: unable to create map for stats block, " 563 "error %u\n", sc->sc_dev.dv_xname, error); 564 return error; 565 } 566 567 if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 568 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) { 569 printf("%s: unable to load memory for stats block, error %u\n", 570 sc->sc_dev.dv_xname, error); 571 return error; 572 } 573 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 574 575 /* XXX disable half-bridge LEARNING+FILTERING feature */ 576 577 /* 578 * Setup h/w rx/tx queues. There are four q's: 579 * rx inbound q of rx'd frames 580 * rx_free pool of ixpbuf's for receiving frames 581 * tx outbound q of frames to send 582 * tx_done q of tx frames that have been processed 583 * 584 * The NPE handles the actual tx/rx process and the q manager 585 * handles the queues. The driver just writes entries to the 586 * q manager mailbox's and gets callbacks when there are rx'd 587 * frames to process or tx'd frames to reap. These callbacks 588 * are controlled by the q configurations; e.g. we get a 589 * callback when tx_done has 2 or more frames to process and 590 * when the rx q has at least one frame. These setings can 591 * changed at the time the q is configured. 592 */ 593 sc->rx_qid = npeconfig[unit].rx_qid; 594 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 595 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 596 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 597 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 598 /* tell the NPE to direct all traffic to rx_qid */ 599 #if 0 600 for (i = 0; i < 8; i++) 601 #else 602 printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname); 603 for (i = 0; i < 4; i++) 604 #endif 605 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 606 607 sc->tx_qid = npeconfig[unit].tx_qid; 608 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 609 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 610 if (tx_doneqid == -1) { 611 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 612 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 613 tx_doneqid = sc->tx_doneqid; 614 } 615 616 KASSERT(npes[npeconfig[unit].npeid] == NULL); 617 npes[npeconfig[unit].npeid] = sc; 618 619 return 0; 620 } 621 622 #if 0 623 static void 624 npe_deactivate(struct npe_softc *sc); 625 { 626 int unit = sc->sc_unit; 627 628 npes[npeconfig[unit].npeid] = NULL; 629 630 /* XXX disable q's */ 631 if (sc->sc_npe != NULL) 632 ixpnpe_stop(sc->sc_npe); 633 if (sc->sc_stats != NULL) { 634 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 635 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 636 sc->sc_stats_map); 637 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 638 } 639 if (sc->sc_stats_tag != NULL) 640 bus_dma_tag_destroy(sc->sc_stats_tag); 641 npe_dma_destroy(sc, &sc->txdma); 642 npe_dma_destroy(sc, &sc->rxdma); 643 bus_generic_detach(sc->sc_dev); 644 if (sc->sc_mii) 645 device_delete_child(sc->sc_dev, sc->sc_mii); 646 #if 0 647 /* XXX sc_ioh and sc_miih */ 648 if (sc->mem_res) 649 bus_release_resource(dev, SYS_RES_IOPORT, 650 rman_get_rid(sc->mem_res), sc->mem_res); 651 sc->mem_res = 0; 652 #endif 653 } 654 #endif 655 656 /* 657 * Change media according to request. 658 */ 659 static int 660 npe_ifmedia_change(struct ifnet *ifp) 661 { 662 struct npe_softc *sc = ifp->if_softc; 663 664 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 665 return ether_mediachange(ifp); 666 return 0; 667 } 668 669 /* 670 * Notify the world which media we're using. 671 */ 672 static void 673 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 674 { 675 struct npe_softc *sc = ifp->if_softc; 676 677 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 678 mii_pollstat(&sc->sc_mii); 679 680 ifmr->ifm_active = sc->sc_mii.mii_media_active; 681 ifmr->ifm_status = sc->sc_mii.mii_media_status; 682 } 683 684 static void 685 npe_addstats(struct npe_softc *sc) 686 { 687 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 688 struct npestats *ns = sc->sc_stats; 689 690 ifp->if_oerrors += 691 be32toh(ns->dot3StatsInternalMacTransmitErrors) 692 + be32toh(ns->dot3StatsCarrierSenseErrors) 693 + be32toh(ns->TxVLANIdFilterDiscards) 694 ; 695 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 696 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 697 + be32toh(ns->RxOverrunDiscards) 698 + be32toh(ns->RxUnderflowEntryDiscards) 699 ; 700 ifp->if_collisions += 701 be32toh(ns->dot3StatsSingleCollisionFrames) 702 + be32toh(ns->dot3StatsMultipleCollisionFrames) 703 ; 704 } 705 706 static void 707 npe_tick(void *xsc) 708 { 709 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 710 struct npe_softc *sc = xsc; 711 uint32_t msg[2]; 712 713 /* 714 * NB: to avoid sleeping with the softc lock held we 715 * split the NPE msg processing into two parts. The 716 * request for statistics is sent w/o waiting for a 717 * reply and then on the next tick we retrieve the 718 * results. This works because npe_tick is the only 719 * code that talks via the mailbox's (except at setup). 720 * This likely can be handled better. 721 */ 722 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 723 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 724 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 725 npe_addstats(sc); 726 } 727 npe_updatestats(sc); 728 mii_tick(&sc->sc_mii); 729 730 /* schedule next poll */ 731 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 732 #undef ACK 733 } 734 735 static void 736 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 737 { 738 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 739 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 740 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 741 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 742 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 743 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 744 745 } 746 747 static void 748 npe_getmac(struct npe_softc *sc, u_char *eaddr) 749 { 750 /* NB: the unicast address appears to be loaded from EEPROM on reset */ 751 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 752 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 753 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 754 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 755 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 756 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 757 } 758 759 struct txdone { 760 struct npebuf *head; 761 struct npebuf **tail; 762 int count; 763 }; 764 765 static __inline void 766 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 767 { 768 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 769 770 *td->tail = sc->tx_free; 771 sc->tx_free = td->head; 772 /* 773 * We're no longer busy, so clear the busy flag and call the 774 * start routine to xmit more packets. 775 */ 776 ifp->if_opackets += td->count; 777 ifp->if_flags &= ~IFF_OACTIVE; 778 ifp->if_timer = 0; 779 npestart(ifp); 780 } 781 782 /* 783 * Q manager callback on tx done queue. Reap mbufs 784 * and return tx buffers to the free list. Finally 785 * restart output. Note the microcode has only one 786 * txdone q wired into it so we must use the NPE ID 787 * returned with each npehwbuf to decide where to 788 * send buffers. 789 */ 790 static void 791 npe_txdone(int qid, void *arg) 792 { 793 #define P2V(a, dma) \ 794 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 795 struct npe_softc *sc; 796 struct npebuf *npe; 797 struct txdone *td, q[NPE_MAX]; 798 uint32_t entry; 799 800 /* XXX no NPE-A support */ 801 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 802 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 803 /* XXX max # at a time? */ 804 while (ixpqmgr_qread(qid, &entry) == 0) { 805 sc = npes[NPE_QM_Q_NPE(entry)]; 806 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 807 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 808 809 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 810 m_freem(npe->ix_m); 811 npe->ix_m = NULL; 812 813 td = &q[NPE_QM_Q_NPE(entry)]; 814 *td->tail = npe; 815 td->tail = &npe->ix_next; 816 td->count++; 817 } 818 819 if (q[NPE_B].count) 820 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 821 if (q[NPE_C].count) 822 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 823 #undef P2V 824 } 825 826 static __inline struct mbuf * 827 npe_getcl(void) 828 { 829 struct mbuf *m; 830 831 MGETHDR(m, M_DONTWAIT, MT_DATA); 832 if (m != NULL) { 833 MCLGET(m, M_DONTWAIT); 834 if ((m->m_flags & M_EXT) == 0) { 835 m_freem(m); 836 m = NULL; 837 } 838 } 839 return (m); 840 } 841 842 static int 843 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 844 { 845 struct npehwbuf *hw; 846 int error; 847 848 if (m == NULL) { 849 m = npe_getcl(); 850 if (m == NULL) 851 return ENOBUFS; 852 } 853 KASSERT(m->m_ext.ext_size >= (1536 + ETHER_ALIGN)); 854 m->m_pkthdr.len = m->m_len = 1536; 855 /* backload payload and align ip hdr */ 856 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 857 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 858 BUS_DMA_READ|BUS_DMA_NOWAIT); 859 if (error != 0) { 860 m_freem(m); 861 return error; 862 } 863 hw = npe->ix_hw; 864 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 865 /* NB: NPE requires length be a multiple of 64 */ 866 /* NB: buffer length is shifted in word */ 867 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 868 hw->ix_ne[0].next = 0; 869 npe->ix_m = m; 870 /* Flush the memory in the mbuf */ 871 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 872 BUS_DMASYNC_PREREAD); 873 return 0; 874 } 875 876 /* 877 * RX q processing for a specific NPE. Claim entries 878 * from the hardware queue and pass the frames up the 879 * stack. Pass the rx buffers to the free list. 880 */ 881 static void 882 npe_rxdone(int qid, void *arg) 883 { 884 #define P2V(a, dma) \ 885 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 886 struct npe_softc *sc = arg; 887 struct npedma *dma = &sc->rxdma; 888 uint32_t entry; 889 890 while (ixpqmgr_qread(qid, &entry) == 0) { 891 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 892 struct mbuf *m; 893 894 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 895 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 896 /* 897 * Allocate a new mbuf to replenish the rx buffer. 898 * If doing so fails we drop the rx'd frame so we 899 * can reuse the previous mbuf. When we're able to 900 * allocate a new mbuf dispatch the mbuf w/ rx'd 901 * data up the stack and replace it with the newly 902 * allocated one. 903 */ 904 m = npe_getcl(); 905 if (m != NULL) { 906 struct mbuf *mrx = npe->ix_m; 907 struct npehwbuf *hw = npe->ix_hw; 908 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 909 910 /* Flush mbuf memory for rx'd data */ 911 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 912 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 913 914 /* XXX flush hw buffer; works now 'cuz coherent */ 915 /* set m_len etc. per rx frame size */ 916 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 917 mrx->m_pkthdr.len = mrx->m_len; 918 mrx->m_pkthdr.rcvif = ifp; 919 mrx->m_flags |= M_HASFCS; 920 921 ifp->if_ipackets++; 922 ifp->if_input(ifp, mrx); 923 } else { 924 /* discard frame and re-use mbuf */ 925 m = npe->ix_m; 926 } 927 if (npe_rxbuf_init(sc, npe, m) == 0) { 928 /* return npe buf to rx free list */ 929 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 930 } else { 931 /* XXX should not happen */ 932 } 933 } 934 #undef P2V 935 } 936 937 static void 938 npe_startxmit(struct npe_softc *sc) 939 { 940 struct npedma *dma = &sc->txdma; 941 int i; 942 943 sc->tx_free = NULL; 944 for (i = 0; i < dma->nbuf; i++) { 945 struct npebuf *npe = &dma->buf[i]; 946 if (npe->ix_m != NULL) { 947 /* NB: should not happen */ 948 printf("%s: %s: free mbuf at entry %u\n", 949 sc->sc_dev.dv_xname, __func__, i); 950 m_freem(npe->ix_m); 951 } 952 npe->ix_m = NULL; 953 npe->ix_next = sc->tx_free; 954 sc->tx_free = npe; 955 } 956 } 957 958 static void 959 npe_startrecv(struct npe_softc *sc) 960 { 961 struct npedma *dma = &sc->rxdma; 962 struct npebuf *npe; 963 int i; 964 965 for (i = 0; i < dma->nbuf; i++) { 966 npe = &dma->buf[i]; 967 npe_rxbuf_init(sc, npe, npe->ix_m); 968 /* set npe buf on rx free list */ 969 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 970 } 971 } 972 973 /* 974 * Reset and initialize the chip 975 */ 976 static void 977 npeinit_locked(void *xsc) 978 { 979 struct npe_softc *sc = xsc; 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 982 if (ifp->if_flags & IFF_RUNNING) return;/*XXX*/ 983 984 /* 985 * Reset MAC core. 986 */ 987 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 988 DELAY(NPE_MAC_RESET_DELAY); 989 /* configure MAC to generate MDC clock */ 990 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 991 992 /* disable transmitter and reciver in the MAC */ 993 WR4(sc, NPE_MAC_RX_CNTRL1, 994 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 995 WR4(sc, NPE_MAC_TX_CNTRL1, 996 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 997 998 /* 999 * Set the MAC core registers. 1000 */ 1001 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1002 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1003 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1004 /* thresholds determined by NPE firmware FS */ 1005 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1006 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1007 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1008 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1009 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1010 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1011 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1012 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1013 1014 WR4(sc, NPE_MAC_TX_CNTRL1, 1015 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1016 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1017 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1018 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1019 /* XXX pad strip? */ 1020 WR4(sc, NPE_MAC_RX_CNTRL1, 1021 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1022 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1023 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1024 1025 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1026 npe_setmcast(sc); 1027 1028 npe_startxmit(sc); 1029 npe_startrecv(sc); 1030 1031 ifp->if_flags |= IFF_RUNNING; 1032 ifp->if_flags &= ~IFF_OACTIVE; 1033 ifp->if_timer = 0; /* just in case */ 1034 1035 /* enable transmitter and reciver in the MAC */ 1036 WR4(sc, NPE_MAC_RX_CNTRL1, 1037 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1038 WR4(sc, NPE_MAC_TX_CNTRL1, 1039 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1040 1041 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1042 } 1043 1044 static int 1045 npeinit(struct ifnet *ifp) 1046 { 1047 struct npe_softc *sc = ifp->if_softc; 1048 int s; 1049 1050 s = splnet(); 1051 npeinit_locked(sc); 1052 splx(s); 1053 1054 return (0); 1055 } 1056 1057 /* 1058 * Defragment an mbuf chain, returning at most maxfrags separate 1059 * mbufs+clusters. If this is not possible NULL is returned and 1060 * the original mbuf chain is left in it's present (potentially 1061 * modified) state. We use two techniques: collapsing consecutive 1062 * mbufs and replacing consecutive mbufs by a cluster. 1063 */ 1064 static __inline struct mbuf * 1065 npe_defrag(struct mbuf *m0) 1066 { 1067 struct mbuf *m; 1068 1069 MGETHDR(m, M_DONTWAIT, MT_DATA); 1070 if (m == NULL) 1071 return (NULL); 1072 M_COPY_PKTHDR(m, m0); 1073 1074 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1075 MCLGET(m, M_DONTWAIT); 1076 if ((m->m_flags & M_EXT) == 0) { 1077 m_freem(m); 1078 return (NULL); 1079 } 1080 } 1081 1082 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1083 m_freem(m0); 1084 1085 return (m); 1086 } 1087 1088 /* 1089 * Dequeue packets and place on the h/w transmit queue. 1090 */ 1091 static void 1092 npestart(struct ifnet *ifp) 1093 { 1094 struct npe_softc *sc = ifp->if_softc; 1095 struct npebuf *npe; 1096 struct npehwbuf *hw; 1097 struct mbuf *m, *n; 1098 bus_dma_segment_t *segs; 1099 int nseg, len, error, i; 1100 uint32_t next; 1101 1102 /* XXX can this happen? */ 1103 if (ifp->if_flags & IFF_OACTIVE) 1104 return; 1105 1106 while (sc->tx_free != NULL) { 1107 IFQ_DEQUEUE(&ifp->if_snd, m); 1108 if (m == NULL) { 1109 /* XXX? */ 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 return; 1112 } 1113 npe = sc->tx_free; 1114 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1115 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1116 if (error == EFBIG) { 1117 n = npe_defrag(m); 1118 if (n == NULL) { 1119 printf("%s: %s: too many fragments\n", 1120 sc->sc_dev.dv_xname, __func__); 1121 m_freem(m); 1122 return; /* XXX? */ 1123 } 1124 m = n; 1125 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1126 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1127 } 1128 if (error != 0) { 1129 printf("%s: %s: error %u\n", 1130 sc->sc_dev.dv_xname, __func__, error); 1131 m_freem(m); 1132 return; /* XXX? */ 1133 } 1134 sc->tx_free = npe->ix_next; 1135 1136 #if NBPFILTER > 0 1137 /* 1138 * Tap off here if there is a bpf listener. 1139 */ 1140 if (__predict_false(ifp->if_bpf)) 1141 bpf_mtap(ifp->if_bpf, m); 1142 #endif 1143 1144 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1145 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1146 1147 npe->ix_m = m; 1148 hw = npe->ix_hw; 1149 len = m->m_pkthdr.len; 1150 nseg = npe->ix_map->dm_nsegs; 1151 segs = npe->ix_map->dm_segs; 1152 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1153 for (i = 0; i < nseg; i++) { 1154 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1155 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1156 hw->ix_ne[i].next = htobe32(next); 1157 1158 len = 0; /* zero for segments > 1 */ 1159 next += sizeof(hw->ix_ne[0]); 1160 } 1161 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1162 /* XXX flush descriptor instead of using uncached memory */ 1163 1164 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1165 __func__, sc->tx_qid, npe->ix_neaddr, 1166 hw->ix_ne[0].data, hw->ix_ne[0].len); 1167 /* stick it on the tx q */ 1168 /* XXX add vlan priority */ 1169 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1170 1171 ifp->if_timer = 5; 1172 } 1173 if (sc->tx_free == NULL) 1174 ifp->if_flags |= IFF_OACTIVE; 1175 } 1176 1177 static void 1178 npe_stopxmit(struct npe_softc *sc) 1179 { 1180 struct npedma *dma = &sc->txdma; 1181 int i; 1182 1183 /* XXX qmgr */ 1184 for (i = 0; i < dma->nbuf; i++) { 1185 struct npebuf *npe = &dma->buf[i]; 1186 1187 if (npe->ix_m != NULL) { 1188 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1189 m_freem(npe->ix_m); 1190 npe->ix_m = NULL; 1191 } 1192 } 1193 } 1194 1195 static void 1196 npe_stoprecv(struct npe_softc *sc) 1197 { 1198 struct npedma *dma = &sc->rxdma; 1199 int i; 1200 1201 /* XXX qmgr */ 1202 for (i = 0; i < dma->nbuf; i++) { 1203 struct npebuf *npe = &dma->buf[i]; 1204 1205 if (npe->ix_m != NULL) { 1206 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1207 m_freem(npe->ix_m); 1208 npe->ix_m = NULL; 1209 } 1210 } 1211 } 1212 1213 /* 1214 * Turn off interrupts, and stop the nic. 1215 */ 1216 void 1217 npestop(struct ifnet *ifp, int disable) 1218 { 1219 struct npe_softc *sc = ifp->if_softc; 1220 1221 /* disable transmitter and reciver in the MAC */ 1222 WR4(sc, NPE_MAC_RX_CNTRL1, 1223 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1224 WR4(sc, NPE_MAC_TX_CNTRL1, 1225 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1226 1227 ifp->if_timer = 0; 1228 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1229 1230 callout_stop(&sc->sc_tick_ch); 1231 1232 npe_stopxmit(sc); 1233 npe_stoprecv(sc); 1234 /* XXX go into loopback & drain q's? */ 1235 /* XXX but beware of disabling tx above */ 1236 1237 /* 1238 * The MAC core rx/tx disable may leave the MAC hardware in an 1239 * unpredictable state. A hw reset is executed before resetting 1240 * all the MAC parameters to a known value. 1241 */ 1242 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1243 DELAY(NPE_MAC_RESET_DELAY); 1244 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1245 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1246 } 1247 1248 void 1249 npewatchdog(struct ifnet *ifp) 1250 { 1251 struct npe_softc *sc = ifp->if_softc; 1252 int s; 1253 1254 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1255 s = splnet(); 1256 ifp->if_oerrors++; 1257 npeinit_locked(sc); 1258 splx(s); 1259 } 1260 1261 static int 1262 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1263 { 1264 struct npe_softc *sc = ifp->if_softc; 1265 struct ifreq *ifr = (struct ifreq *)data; 1266 int s, error = 0; 1267 1268 s = splnet(); 1269 1270 error = ether_ioctl(ifp, cmd, data); 1271 if (error == ENETRESET) { 1272 if ((ifp->if_flags & IFF_UP) == 0 && 1273 ifp->if_flags & IFF_RUNNING) { 1274 ifp->if_flags &= ~IFF_RUNNING; 1275 npestop(&sc->sc_ethercom.ec_if, 0); 1276 } else { 1277 /* reinitialize card on any parameter change */ 1278 npeinit_locked(sc); 1279 } 1280 error = 0; 1281 } 1282 1283 npestart(ifp); 1284 1285 splx(s); 1286 return error; 1287 } 1288 1289 /* 1290 * Setup a traffic class -> rx queue mapping. 1291 */ 1292 static int 1293 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1294 { 1295 int npeid = npeconfig[sc->sc_unit].npeid; 1296 uint32_t msg[2]; 1297 1298 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix; 1299 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1300 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1301 } 1302 1303 /* 1304 * Update and reset the statistics in the NPE. 1305 */ 1306 static int 1307 npe_updatestats(struct npe_softc *sc) 1308 { 1309 uint32_t msg[2]; 1310 1311 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1312 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1313 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1314 } 1315 1316 #if 0 1317 /* 1318 * Get the current statistics block. 1319 */ 1320 static int 1321 npe_getstats(struct npe_softc *sc) 1322 { 1323 uint32_t msg[2]; 1324 1325 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1326 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1327 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1328 } 1329 1330 /* 1331 * Query the image id of the loaded firmware. 1332 */ 1333 static uint32_t 1334 npe_getimageid(struct npe_softc *sc) 1335 { 1336 uint32_t msg[2]; 1337 1338 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1339 msg[1] = 0; 1340 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1341 } 1342 1343 /* 1344 * Enable/disable loopback. 1345 */ 1346 static int 1347 npe_setloopback(struct npe_softc *sc, int ena) 1348 { 1349 uint32_t msg[2]; 1350 1351 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1352 msg[1] = 0; 1353 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1354 } 1355 #endif 1356 1357 /* 1358 * MII bus support routines. 1359 * 1360 * NB: ixp425 has one PHY per NPE 1361 */ 1362 static uint32_t 1363 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1364 { 1365 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1366 uint32_t v; 1367 1368 /* NB: registers are known to be sequential */ 1369 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1370 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1371 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1372 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1373 return v; 1374 #undef MII_RD4 1375 } 1376 1377 static void 1378 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1379 { 1380 #define MII_WR4(sc, reg, v) \ 1381 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1382 1383 /* NB: registers are known to be sequential */ 1384 MII_WR4(sc, reg+0, cmd & 0xff); 1385 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1386 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1387 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1388 #undef MII_WR4 1389 } 1390 1391 static int 1392 npe_mii_mdio_wait(struct npe_softc *sc) 1393 { 1394 #define MAXTRIES 100 /* XXX */ 1395 uint32_t v; 1396 int i; 1397 1398 for (i = 0; i < MAXTRIES; i++) { 1399 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1400 if ((v & NPE_MII_GO) == 0) 1401 return 1; 1402 } 1403 return 0; /* NB: timeout */ 1404 #undef MAXTRIES 1405 } 1406 1407 static int 1408 npe_miibus_readreg(struct device *self, int phy, int reg) 1409 { 1410 struct npe_softc *sc = (void *)self; 1411 uint32_t v; 1412 1413 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1414 return 0xffff; 1415 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1416 | NPE_MII_GO; 1417 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1418 if (npe_mii_mdio_wait(sc)) 1419 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1420 else 1421 v = 0xffff | NPE_MII_READ_FAIL; 1422 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1423 #undef MAXTRIES 1424 } 1425 1426 static void 1427 npe_miibus_writereg(struct device *self, int phy, int reg, int data) 1428 { 1429 struct npe_softc *sc = (void *)self; 1430 uint32_t v; 1431 1432 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1433 return; 1434 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1435 | data | NPE_MII_WRITE 1436 | NPE_MII_GO; 1437 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1438 /* XXX complain about timeout */ 1439 (void) npe_mii_mdio_wait(sc); 1440 } 1441 1442 static void 1443 npe_miibus_statchg(struct device *self) 1444 { 1445 struct npe_softc *sc = (void *)self; 1446 uint32_t tx1, rx1; 1447 1448 /* sync MAC duplex state */ 1449 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1450 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1451 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1452 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1453 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1454 } else { 1455 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1456 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1457 } 1458 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1459 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1460 } 1461
Indexes created Thu Oct 02 10:09:58 GMT 2025