ixp425_intr.c revision 1.1
1 /* $NetBSD: ixp425_intr.c,v 1.1 2003/05/23 00:57:25 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.1 2003/05/23 00:57:25 ichiro Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Current interrupt priority level. */ 102 __volatile int current_spl_level; 103 104 /* Interrupts pending. */ 105 __volatile int ixp425_ipending; 106 107 /* Software copy of the IRQs we have enabled. */ 108 __volatile uint32_t intr_enabled; 109 110 /* Mask if interrupts steered to FIQs. */ 111 uint32_t intr_steer; 112 113 /* 114 * Map a software interrupt queue index 115 */ 116 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 117 IXP425_INT_bit31, /* SI_SOFT */ 118 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 119 IXP425_INT_bit29, /* SI_SOFTNET */ 120 IXP425_INT_bit22, /* SI_SOFTSERIAL */ 121 }; 122 123 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 124 125 /* 126 * Map a software interrupt queue to an interrupt priority level. 127 */ 128 static const int si_to_ipl[SI_NQUEUES] = { 129 IPL_SOFT, /* SI_SOFT */ 130 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 131 IPL_SOFTNET, /* SI_SOFTNET */ 132 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 133 }; 134 135 void ixp425_intr_dispatch(struct clockframe *frame); 136 137 static __inline uint32_t 138 ixp425_irq_read(void) 139 { 140 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 141 } 142 143 static __inline void 144 ixp425_set_intrsteer(void) 145 { 146 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 147 } 148 149 static __inline void 150 ixp425_enable_irq(int irq) 151 { 152 153 intr_enabled |= (1U << irq); 154 ixp425_set_intrmask(); 155 } 156 157 static __inline void 158 ixp425_disable_irq(int irq) 159 { 160 161 intr_enabled &= ~(1U << irq); 162 ixp425_set_intrmask(); 163 } 164 165 /* 166 * NOTE: This routine must be called with interrupts disabled in the CPSR. 167 */ 168 static void 169 ixp425_intr_calculate_masks(void) 170 { 171 struct intrq *iq; 172 struct intrhand *ih; 173 int irq, ipl; 174 175 /* First, figure out which IPLs each IRQ has. */ 176 for (irq = 0; irq < NIRQ; irq++) { 177 int levels = 0; 178 iq = &intrq[irq]; 179 ixp425_disable_irq(irq); 180 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 181 ih = TAILQ_NEXT(ih, ih_list)) 182 levels |= (1U << ih->ih_ipl); 183 iq->iq_levels = levels; 184 } 185 186 /* Next, figure out which IRQs are used by each IPL. */ 187 for (ipl = 0; ipl < NIPL; ipl++) { 188 int irqs = 0; 189 for (irq = 0; irq < NIRQ; irq++) { 190 if (intrq[irq].iq_levels & (1U << ipl)) 191 irqs |= (1U << irq); 192 } 193 ixp425_imask[ipl] = irqs; 194 } 195 196 ixp425_imask[IPL_NONE] = 0; 197 198 /* 199 * Initialize the soft interrupt masks to block themselves. 200 */ 201 ixp425_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 202 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 203 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 204 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 205 206 /* 207 * splsoftclock() is the only interface that users of the 208 * generic software interrupt facility have to block their 209 * soft intrs, so splsoftclock() must also block IPL_SOFT. 210 */ 211 ixp425_imask[IPL_SOFTCLOCK] |= ixp425_imask[IPL_SOFT]; 212 213 /* 214 * splsoftnet() must also block splsoftclock(), since we don't 215 * want timer-driven network events to occur while we're 216 * processing incoming packets. 217 */ 218 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTCLOCK]; 219 220 /* 221 * Enforce a heirarchy that gives "slow" device (or devices with 222 * limited input buffer space/"real-time" requirements) a better 223 * chance at not dropping data. 224 */ 225 ixp425_imask[IPL_BIO] |= ixp425_imask[IPL_SOFTNET]; 226 ixp425_imask[IPL_NET] |= ixp425_imask[IPL_BIO]; 227 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_NET]; 228 ixp425_imask[IPL_TTY] |= ixp425_imask[IPL_SOFTSERIAL]; 229 230 /* 231 * splvm() blocks all interrupts that use the kernel memory 232 * allocation facilities. 233 */ 234 ixp425_imask[IPL_IMP] |= ixp425_imask[IPL_TTY]; 235 236 /* 237 * Audio devices are not allowed to perform memory allocation 238 * in their interrupt routines, and they have fairly "real-time" 239 * requirements, so give them a high interrupt priority. 240 */ 241 ixp425_imask[IPL_AUDIO] |= ixp425_imask[IPL_IMP]; 242 243 /* 244 * splclock() must block anything that uses the scheduler. 245 */ 246 ixp425_imask[IPL_CLOCK] |= ixp425_imask[IPL_AUDIO]; 247 248 /* 249 * No separate statclock on the IQ80310. 250 */ 251 ixp425_imask[IPL_STATCLOCK] |= ixp425_imask[IPL_CLOCK]; 252 253 /* 254 * splhigh() must block "everything". 255 */ 256 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_STATCLOCK]; 257 258 /* 259 * XXX We need serial drivers to run at the absolute highest priority 260 * in order to avoid overruns, so serial > high. 261 */ 262 ixp425_imask[IPL_SERIAL] |= ixp425_imask[IPL_HIGH]; 263 264 /* 265 * Now compute which IRQs must be blocked when servicing any 266 * given IRQ. 267 */ 268 for (irq = 0; irq < NIRQ; irq++) { 269 int irqs = (1U << irq); 270 iq = &intrq[irq]; 271 if (TAILQ_FIRST(&iq->iq_list) != NULL) 272 ixp425_enable_irq(irq); 273 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 274 ih = TAILQ_NEXT(ih, ih_list)) 275 irqs |= ixp425_imask[ih->ih_ipl]; 276 iq->iq_mask = irqs; 277 } 278 } 279 280 __inline void 281 ixp425_do_pending(void) 282 { 283 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 284 int new, oldirqstate; 285 286 if (__cpu_simple_lock_try(&processing) == 0) 287 return; 288 289 new = current_spl_level; 290 291 oldirqstate = disable_interrupts(I32_bit); 292 293 #define DO_SOFTINT(si) \ 294 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 295 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 296 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 297 restore_interrupts(oldirqstate); \ 298 softintr_dispatch(si); \ 299 oldirqstate = disable_interrupts(I32_bit); \ 300 current_spl_level = new; \ 301 } 302 303 DO_SOFTINT(SI_SOFTSERIAL); 304 DO_SOFTINT(SI_SOFTNET); 305 DO_SOFTINT(SI_SOFTCLOCK); 306 DO_SOFTINT(SI_SOFT); 307 308 __cpu_simple_unlock(&processing); 309 310 restore_interrupts(oldirqstate); 311 } 312 313 void 314 splx(int new) 315 { 316 317 ixp425_splx(new); 318 } 319 320 int 321 _spllower(int ipl) 322 { 323 324 return (ixp425_spllower(ipl)); 325 } 326 327 int 328 _splraise(int ipl) 329 { 330 331 return (ixp425_splraise(ipl)); 332 } 333 334 void 335 _setsoftintr(int si) 336 { 337 int oldirqstate; 338 339 oldirqstate = disable_interrupts(I32_bit); 340 ixp425_ipending |= SI_TO_IRQBIT(si); 341 restore_interrupts(oldirqstate); 342 343 /* Process unmasked pending soft interrupts. */ 344 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 345 ixp425_do_pending(); 346 } 347 348 /* 349 * ixp425_icu_init: 350 * 351 * Called early in bootstrap to make clear interrupt register 352 */ 353 void 354 ixp425_icu_init(void) 355 { 356 357 intr_enabled = 0; /* All interrupts disabled */ 358 ixp425_set_intrmask(); 359 360 intr_steer = 0; /* All interrupts steered to IRQ */ 361 ixp425_set_intrsteer(); 362 } 363 364 /* 365 * ixp425_intr_init: 366 * 367 * Initialize the rest of the interrupt subsystem, making it 368 * ready to handle interrupts from devices. 369 */ 370 void 371 ixp425_intr_init(void) 372 { 373 struct intrq *iq; 374 int i; 375 376 intr_enabled = 0; 377 378 for (i = 0; i < NIRQ; i++) { 379 iq = &intrq[i]; 380 TAILQ_INIT(&iq->iq_list); 381 382 sprintf(iq->iq_name, "irq %d", i); 383 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 384 NULL, "ixp425", iq->iq_name); 385 } 386 387 ixp425_intr_calculate_masks(); 388 389 /* Enable IRQs (don't yet use FIQs). */ 390 enable_interrupts(I32_bit); 391 } 392 393 void * 394 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 395 { 396 struct intrq *iq; 397 struct intrhand *ih; 398 u_int oldirqstate; 399 400 if (irq < 0 || irq > NIRQ) 401 panic("ixp425_intr_establish: IRQ %d out of range", irq); 402 #ifdef DEBUG 403 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 404 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 405 #endif 406 407 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 408 if (ih == NULL) 409 return (NULL); 410 411 ih->ih_func = func; 412 ih->ih_arg = arg; 413 ih->ih_ipl = ipl; 414 ih->ih_irq = irq; 415 416 iq = &intrq[irq]; 417 418 /* All IXP425 interrupts are level-triggered. */ 419 iq->iq_ist = IST_LEVEL; /* XXX */ 420 421 oldirqstate = disable_interrupts(I32_bit); 422 423 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 424 425 ixp425_intr_calculate_masks(); 426 427 restore_interrupts(oldirqstate); 428 429 return (ih); 430 } 431 432 void 433 ixp425_intr_disestablish(void *cookie) 434 { 435 struct intrhand *ih = cookie; 436 struct intrq *iq = &intrq[ih->ih_irq]; 437 int oldirqstate; 438 439 oldirqstate = disable_interrupts(I32_bit); 440 441 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 442 443 ixp425_intr_calculate_masks(); 444 445 restore_interrupts(oldirqstate); 446 } 447 448 void 449 ixp425_intr_dispatch(struct clockframe *frame) 450 { 451 struct intrq *iq; 452 struct intrhand *ih; 453 int oldirqstate, pcpl, irq, ibit, hwpend; 454 455 pcpl = current_spl_level; 456 457 hwpend = ixp425_irq_read(); 458 459 /* 460 * Disable all the interrupts that are pending. We will 461 * reenable them once they are processed and not masked. 462 */ 463 intr_enabled &= ~hwpend; 464 ixp425_set_intrmask(); 465 466 while (hwpend != 0) { 467 irq = ffs(hwpend) - 1; 468 ibit = (1U << irq); 469 470 hwpend &= ~ibit; 471 472 if (pcpl & ibit) { 473 /* 474 * IRQ is masked; mark it as pending and check 475 * the next one. Note: the IRQ is already disabled. 476 */ 477 ixp425_ipending |= ibit; 478 continue; 479 } 480 481 ixp425_ipending &= ~ibit; 482 483 iq = &intrq[irq]; 484 iq->iq_ev.ev_count++; 485 uvmexp.intrs++; 486 current_spl_level |= iq->iq_mask; 487 oldirqstate = enable_interrupts(I32_bit); 488 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 489 ih = TAILQ_NEXT(ih, ih_list)) { 490 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 491 } 492 restore_interrupts(oldirqstate); 493 494 current_spl_level = pcpl; 495 496 /* Re-enable this interrupt now that's it's cleared. */ 497 intr_enabled |= ibit; 498 ixp425_set_intrmask(); 499 } 500 501 /* Check for pendings soft intrs. */ 502 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 503 oldirqstate = enable_interrupts(I32_bit); 504 ixp425_do_pending(); 505 restore_interrupts(oldirqstate); 506 } 507 } 508
Indexes created Wed Oct 22 13:09:56 GMT 2025