ixp425_intr.c revision 1.10
1 /* $NetBSD: ixp425_intr.c,v 1.10 2004/02/27 18:55:19 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.10 2004/02/27 18:55:19 scw Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Current interrupt priority level. */ 102 __volatile int current_spl_level; 103 104 /* Interrupts pending. */ 105 __volatile int ixp425_ipending; 106 107 /* Software copy of the IRQs we have enabled. */ 108 __volatile uint32_t intr_enabled; 109 110 /* Mask if interrupts steered to FIQs. */ 111 uint32_t intr_steer; 112 113 /* 114 * Map a software interrupt queue index 115 * 116 * XXX: !NOTE! :XXX 117 * We 'borrow' bits from the interrupt status register for interrupt sources 118 * which are not used by the current IXP425 port. Should any of the following 119 * interrupt sources be used at some future time, this must be revisited. 120 * 121 * Bit#31: SW Interrupt 1 122 * Bit#30: SW Interrupt 0 123 * Bit#14: Timestamp Timer 124 * Bit#11: General-purpose Timer 1 125 */ 126 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 127 IXP425_INT_bit31, /* SI_SOFT */ 128 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 129 IXP425_INT_bit14, /* SI_SOFTNET */ 130 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 131 }; 132 133 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 134 135 /* 136 * Map a software interrupt queue to an interrupt priority level. 137 */ 138 static const int si_to_ipl[SI_NQUEUES] = { 139 IPL_SOFT, /* SI_SOFT */ 140 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 141 IPL_SOFTNET, /* SI_SOFTNET */ 142 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 143 }; 144 145 void ixp425_intr_dispatch(struct clockframe *frame); 146 147 static __inline uint32_t 148 ixp425_irq_read(void) 149 { 150 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 151 } 152 153 static __inline void 154 ixp425_set_intrsteer(void) 155 { 156 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 157 } 158 159 static __inline void 160 ixp425_enable_irq(int irq) 161 { 162 163 intr_enabled |= (1U << irq); 164 ixp425_set_intrmask(); 165 } 166 167 static __inline void 168 ixp425_disable_irq(int irq) 169 { 170 171 intr_enabled &= ~(1U << irq); 172 ixp425_set_intrmask(); 173 } 174 175 static __inline u_int32_t 176 ixp425_irq2gpio_bit(int irq) 177 { 178 179 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 180 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 181 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 182 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 183 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 184 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 185 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 186 0xff, 0xff /* INT#30 -> INT#31 */ 187 }; 188 189 #ifdef DEBUG 190 if (int2gpio[irq] == 0xff) 191 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 192 #endif 193 return (1U << int2gpio[irq]); 194 } 195 196 /* 197 * NOTE: This routine must be called with interrupts disabled in the CPSR. 198 */ 199 static void 200 ixp425_intr_calculate_masks(void) 201 { 202 struct intrq *iq; 203 struct intrhand *ih; 204 int irq, ipl; 205 206 /* First, figure out which IPLs each IRQ has. */ 207 for (irq = 0; irq < NIRQ; irq++) { 208 int levels = 0; 209 iq = &intrq[irq]; 210 ixp425_disable_irq(irq); 211 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 212 ih = TAILQ_NEXT(ih, ih_list)) 213 levels |= (1U << ih->ih_ipl); 214 iq->iq_levels = levels; 215 } 216 217 /* Next, figure out which IRQs are used by each IPL. */ 218 for (ipl = 0; ipl < NIPL; ipl++) { 219 int irqs = 0; 220 for (irq = 0; irq < NIRQ; irq++) { 221 if (intrq[irq].iq_levels & (1U << ipl)) 222 irqs |= (1U << irq); 223 } 224 ixp425_imask[ipl] = irqs; 225 } 226 227 ixp425_imask[IPL_NONE] = 0; 228 229 /* 230 * Initialize the soft interrupt masks to block themselves. 231 */ 232 ixp425_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 233 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 234 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 235 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 236 237 /* 238 * splsoftclock() is the only interface that users of the 239 * generic software interrupt facility have to block their 240 * soft intrs, so splsoftclock() must also block IPL_SOFT. 241 */ 242 ixp425_imask[IPL_SOFTCLOCK] |= ixp425_imask[IPL_SOFT]; 243 244 /* 245 * splsoftnet() must also block splsoftclock(), since we don't 246 * want timer-driven network events to occur while we're 247 * processing incoming packets. 248 */ 249 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTCLOCK]; 250 251 /* 252 * Enforce a heirarchy that gives "slow" device (or devices with 253 * limited input buffer space/"real-time" requirements) a better 254 * chance at not dropping data. 255 */ 256 ixp425_imask[IPL_BIO] |= ixp425_imask[IPL_SOFTNET]; 257 ixp425_imask[IPL_NET] |= ixp425_imask[IPL_BIO]; 258 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_NET]; 259 ixp425_imask[IPL_TTY] |= ixp425_imask[IPL_SOFTSERIAL]; 260 261 /* 262 * splvm() blocks all interrupts that use the kernel memory 263 * allocation facilities. 264 */ 265 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_TTY]; 266 267 /* 268 * Audio devices are not allowed to perform memory allocation 269 * in their interrupt routines, and they have fairly "real-time" 270 * requirements, so give them a high interrupt priority. 271 */ 272 ixp425_imask[IPL_AUDIO] |= ixp425_imask[IPL_VM]; 273 274 /* 275 * splclock() must block anything that uses the scheduler. 276 */ 277 ixp425_imask[IPL_CLOCK] |= ixp425_imask[IPL_AUDIO]; 278 279 /* 280 * No separate statclock on the IQ80310. 281 */ 282 ixp425_imask[IPL_STATCLOCK] |= ixp425_imask[IPL_CLOCK]; 283 284 /* 285 * splhigh() must block "everything". 286 */ 287 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_STATCLOCK]; 288 289 /* 290 * XXX We need serial drivers to run at the absolute highest priority 291 * in order to avoid overruns, so serial > high. 292 */ 293 ixp425_imask[IPL_SERIAL] |= ixp425_imask[IPL_HIGH]; 294 295 /* 296 * Now compute which IRQs must be blocked when servicing any 297 * given IRQ. 298 */ 299 for (irq = 0; irq < NIRQ; irq++) { 300 int irqs = (1U << irq); 301 iq = &intrq[irq]; 302 if (TAILQ_FIRST(&iq->iq_list) != NULL) 303 ixp425_enable_irq(irq); 304 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 305 ih = TAILQ_NEXT(ih, ih_list)) 306 irqs |= ixp425_imask[ih->ih_ipl]; 307 iq->iq_mask = irqs; 308 } 309 } 310 311 __inline void 312 ixp425_do_pending(void) 313 { 314 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 315 int new, oldirqstate; 316 317 if (__cpu_simple_lock_try(&processing) == 0) 318 return; 319 320 new = current_spl_level; 321 322 oldirqstate = disable_interrupts(I32_bit); 323 324 #define DO_SOFTINT(si) \ 325 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 326 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 327 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 328 restore_interrupts(oldirqstate); \ 329 softintr_dispatch(si); \ 330 oldirqstate = disable_interrupts(I32_bit); \ 331 current_spl_level = new; \ 332 } 333 334 DO_SOFTINT(SI_SOFTSERIAL); 335 DO_SOFTINT(SI_SOFTNET); 336 DO_SOFTINT(SI_SOFTCLOCK); 337 DO_SOFTINT(SI_SOFT); 338 339 __cpu_simple_unlock(&processing); 340 341 restore_interrupts(oldirqstate); 342 } 343 344 void 345 splx(int new) 346 { 347 348 ixp425_splx(new); 349 } 350 351 int 352 _spllower(int ipl) 353 { 354 355 return (ixp425_spllower(ipl)); 356 } 357 358 int 359 _splraise(int ipl) 360 { 361 362 return (ixp425_splraise(ipl)); 363 } 364 365 void 366 _setsoftintr(int si) 367 { 368 int oldirqstate; 369 370 oldirqstate = disable_interrupts(I32_bit); 371 ixp425_ipending |= SI_TO_IRQBIT(si); 372 restore_interrupts(oldirqstate); 373 374 /* Process unmasked pending soft interrupts. */ 375 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 376 ixp425_do_pending(); 377 } 378 379 /* 380 * ixp425_icu_init: 381 * 382 * Called early in bootstrap to make clear interrupt register 383 */ 384 void 385 ixp425_icu_init(void) 386 { 387 388 intr_enabled = 0; /* All interrupts disabled */ 389 ixp425_set_intrmask(); 390 391 intr_steer = 0; /* All interrupts steered to IRQ */ 392 ixp425_set_intrsteer(); 393 } 394 395 /* 396 * ixp425_intr_init: 397 * 398 * Initialize the rest of the interrupt subsystem, making it 399 * ready to handle interrupts from devices. 400 */ 401 void 402 ixp425_intr_init(void) 403 { 404 struct intrq *iq; 405 int i; 406 407 intr_enabled = 0; 408 409 for (i = 0; i < NIRQ; i++) { 410 iq = &intrq[i]; 411 TAILQ_INIT(&iq->iq_list); 412 413 sprintf(iq->iq_name, "irq %d", i); 414 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 415 NULL, "ixp425", iq->iq_name); 416 } 417 418 ixp425_intr_calculate_masks(); 419 420 /* Enable IRQs (don't yet use FIQs). */ 421 enable_interrupts(I32_bit); 422 } 423 424 void * 425 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 426 { 427 struct intrq *iq; 428 struct intrhand *ih; 429 u_int oldirqstate; 430 431 if (irq < 0 || irq > NIRQ) 432 panic("ixp425_intr_establish: IRQ %d out of range", irq); 433 #ifdef DEBUG 434 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 435 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 436 #endif 437 438 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 439 if (ih == NULL) 440 return (NULL); 441 442 ih->ih_func = func; 443 ih->ih_arg = arg; 444 ih->ih_ipl = ipl; 445 ih->ih_irq = irq; 446 447 iq = &intrq[irq]; 448 449 /* All IXP425 interrupts are level-triggered. */ 450 iq->iq_ist = IST_LEVEL; /* XXX */ 451 452 oldirqstate = disable_interrupts(I32_bit); 453 454 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 455 456 ixp425_intr_calculate_masks(); 457 458 restore_interrupts(oldirqstate); 459 460 return (ih); 461 } 462 463 void 464 ixp425_intr_disestablish(void *cookie) 465 { 466 struct intrhand *ih = cookie; 467 struct intrq *iq = &intrq[ih->ih_irq]; 468 int oldirqstate; 469 470 oldirqstate = disable_interrupts(I32_bit); 471 472 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 473 474 ixp425_intr_calculate_masks(); 475 476 restore_interrupts(oldirqstate); 477 } 478 479 void 480 ixp425_intr_dispatch(struct clockframe *frame) 481 { 482 struct intrq *iq; 483 struct intrhand *ih; 484 int oldirqstate, pcpl, irq, ibit, hwpend; 485 486 pcpl = current_spl_level; 487 488 hwpend = ixp425_irq_read(); 489 490 /* 491 * Disable all the interrupts that are pending. We will 492 * reenable them once they are processed and not masked. 493 */ 494 intr_enabled &= ~hwpend; 495 ixp425_set_intrmask(); 496 497 while (hwpend != 0) { 498 irq = ffs(hwpend) - 1; 499 ibit = (1U << irq); 500 501 hwpend &= ~ibit; 502 503 if (pcpl & ibit) { 504 /* 505 * IRQ is masked; mark it as pending and check 506 * the next one. Note: the IRQ is already disabled. 507 */ 508 ixp425_ipending |= ibit; 509 continue; 510 } 511 512 ixp425_ipending &= ~ibit; 513 514 iq = &intrq[irq]; 515 iq->iq_ev.ev_count++; 516 uvmexp.intrs++; 517 current_spl_level |= iq->iq_mask; 518 519 /* Clear down non-level triggered GPIO interrupts now */ 520 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 521 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 522 ixp425_irq2gpio_bit(irq); 523 } 524 525 oldirqstate = enable_interrupts(I32_bit); 526 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 527 ih = TAILQ_NEXT(ih, ih_list)) { 528 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 529 } 530 restore_interrupts(oldirqstate); 531 532 /* Clear down level triggered GPIO interrupts now */ 533 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 534 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 535 ixp425_irq2gpio_bit(irq); 536 } 537 538 current_spl_level = pcpl; 539 540 /* Re-enable this interrupt now that's it's cleared. */ 541 intr_enabled |= ibit; 542 ixp425_set_intrmask(); 543 544 /* 545 * Don't forget to include interrupts which may have 546 * arrived in the meantime. 547 */ 548 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~pcpl); 549 } 550 551 /* Check for pendings soft intrs. */ 552 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 553 oldirqstate = enable_interrupts(I32_bit); 554 ixp425_do_pending(); 555 restore_interrupts(oldirqstate); 556 } 557 } 558
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