ixp425_intr.c revision 1.15.30.1
1 /* $NetBSD: ixp425_intr.c,v 1.15.30.1 2007/11/09 05:37:46 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.15.30.1 2007/11/09 05:37:46 matt Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Interrupts pending. */ 102 volatile int ixp425_ipending; 103 104 /* Software copy of the IRQs we have enabled. */ 105 volatile uint32_t intr_enabled; 106 107 /* Mask if interrupts steered to FIQs. */ 108 uint32_t intr_steer; 109 110 /* 111 * Map a software interrupt queue index 112 * 113 * XXX: !NOTE! :XXX 114 * We 'borrow' bits from the interrupt status register for interrupt sources 115 * which are not used by the current IXP425 port. Should any of the following 116 * interrupt sources be used at some future time, this must be revisited. 117 * 118 * Bit#31: SW Interrupt 1 119 * Bit#30: SW Interrupt 0 120 * Bit#14: Timestamp Timer 121 * Bit#11: General-purpose Timer 1 122 */ 123 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 124 IXP425_INT_bit31, /* SI_SOFT */ 125 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 126 IXP425_INT_bit14, /* SI_SOFTNET */ 127 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 128 }; 129 130 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 131 132 /* 133 * Map a software interrupt queue to an interrupt priority level. 134 */ 135 static const int si_to_ipl[SI_NQUEUES] = { 136 IPL_SOFT, /* SI_SOFT */ 137 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 138 IPL_SOFTNET, /* SI_SOFTNET */ 139 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 140 }; 141 142 void ixp425_intr_dispatch(struct clockframe *frame); 143 144 static inline uint32_t 145 ixp425_irq_read(void) 146 { 147 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 148 } 149 150 static inline void 151 ixp425_set_intrsteer(void) 152 { 153 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 154 } 155 156 static inline void 157 ixp425_enable_irq(int irq) 158 { 159 160 intr_enabled |= (1U << irq); 161 ixp425_set_intrmask(); 162 } 163 164 static inline void 165 ixp425_disable_irq(int irq) 166 { 167 168 intr_enabled &= ~(1U << irq); 169 ixp425_set_intrmask(); 170 } 171 172 static inline u_int32_t 173 ixp425_irq2gpio_bit(int irq) 174 { 175 176 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 177 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 178 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 179 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 180 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 181 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 182 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 183 0xff, 0xff /* INT#30 -> INT#31 */ 184 }; 185 186 #ifdef DEBUG 187 if (int2gpio[irq] == 0xff) 188 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 189 #endif 190 return (1U << int2gpio[irq]); 191 } 192 193 /* 194 * NOTE: This routine must be called with interrupts disabled in the CPSR. 195 */ 196 static void 197 ixp425_intr_calculate_masks(void) 198 { 199 struct intrq *iq; 200 struct intrhand *ih; 201 int irq, ipl; 202 203 /* First, figure out which IPLs each IRQ has. */ 204 for (irq = 0; irq < NIRQ; irq++) { 205 int levels = 0; 206 iq = &intrq[irq]; 207 ixp425_disable_irq(irq); 208 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 209 ih = TAILQ_NEXT(ih, ih_list)) 210 levels |= (1U << ih->ih_ipl); 211 iq->iq_levels = levels; 212 } 213 214 /* Next, figure out which IRQs are used by each IPL. */ 215 for (ipl = 0; ipl < NIPL; ipl++) { 216 int irqs = 0; 217 for (irq = 0; irq < NIRQ; irq++) { 218 if (intrq[irq].iq_levels & (1U << ipl)) 219 irqs |= (1U << irq); 220 } 221 ixp425_imask[ipl] = irqs; 222 } 223 224 ixp425_imask[IPL_NONE] = 0; 225 226 /* 227 * Initialize the soft interrupt masks to block themselves. 228 */ 229 ixp425_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 230 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 231 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 232 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 233 234 /* 235 * splsoftclock() is the only interface that users of the 236 * generic software interrupt facility have to block their 237 * soft intrs, so splsoftclock() must also block IPL_SOFT. 238 */ 239 ixp425_imask[IPL_SOFTCLOCK] |= ixp425_imask[IPL_SOFT]; 240 241 /* 242 * splsoftnet() must also block splsoftclock(), since we don't 243 * want timer-driven network events to occur while we're 244 * processing incoming packets. 245 */ 246 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTCLOCK]; 247 248 /* 249 * Enforce a hierarchy that gives "slow" device (or devices with 250 * limited input buffer space/"real-time" requirements) a better 251 * chance at not dropping data. 252 */ 253 ixp425_imask[IPL_BIO] |= ixp425_imask[IPL_SOFTNET]; 254 ixp425_imask[IPL_NET] |= ixp425_imask[IPL_BIO]; 255 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_NET]; 256 ixp425_imask[IPL_TTY] |= ixp425_imask[IPL_SOFTSERIAL]; 257 258 /* 259 * splvm() blocks all interrupts that use the kernel memory 260 * allocation facilities. 261 */ 262 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_TTY]; 263 264 /* 265 * Audio devices are not allowed to perform memory allocation 266 * in their interrupt routines, and they have fairly "real-time" 267 * requirements, so give them a high interrupt priority. 268 */ 269 ixp425_imask[IPL_AUDIO] |= ixp425_imask[IPL_VM]; 270 271 /* 272 * splclock() must block anything that uses the scheduler. 273 */ 274 ixp425_imask[IPL_CLOCK] |= ixp425_imask[IPL_AUDIO]; 275 276 /* 277 * No separate statclock on the IQ80310. 278 */ 279 ixp425_imask[IPL_STATCLOCK] |= ixp425_imask[IPL_CLOCK]; 280 281 /* 282 * splhigh() must block "everything". 283 */ 284 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_STATCLOCK]; 285 286 /* 287 * XXX We need serial drivers to run at the absolute highest priority 288 * in order to avoid overruns, so serial > high. 289 */ 290 ixp425_imask[IPL_SERIAL] |= ixp425_imask[IPL_HIGH]; 291 292 /* 293 * Now compute which IRQs must be blocked when servicing any 294 * given IRQ. 295 */ 296 for (irq = 0; irq < NIRQ; irq++) { 297 int irqs = (1U << irq); 298 iq = &intrq[irq]; 299 if (TAILQ_FIRST(&iq->iq_list) != NULL) 300 ixp425_enable_irq(irq); 301 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 302 ih = TAILQ_NEXT(ih, ih_list)) 303 irqs |= ixp425_imask[ih->ih_ipl]; 304 iq->iq_mask = irqs; 305 } 306 } 307 308 void 309 ixp425_do_pending(void) 310 { 311 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 312 int new, oldirqstate; 313 314 if (__cpu_simple_lock_try(&processing) == 0) 315 return; 316 317 new = curcpl(); 318 319 oldirqstate = disable_interrupts(I32_bit); 320 321 #define DO_SOFTINT(si) \ 322 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 323 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 324 set_curcpl(new | ixp425_imask[si_to_ipl[(si)]]); \ 325 restore_interrupts(oldirqstate); \ 326 softintr_dispatch(si); \ 327 oldirqstate = disable_interrupts(I32_bit); \ 328 set_curcpl(new); \ 329 } 330 331 DO_SOFTINT(SI_SOFTSERIAL); 332 DO_SOFTINT(SI_SOFTNET); 333 DO_SOFTINT(SI_SOFTCLOCK); 334 DO_SOFTINT(SI_SOFT); 335 336 __cpu_simple_unlock(&processing); 337 338 restore_interrupts(oldirqstate); 339 } 340 341 void 342 splx(int new) 343 { 344 345 ixp425_splx(new); 346 } 347 348 int 349 _spllower(int ipl) 350 { 351 352 return (ixp425_spllower(ipl)); 353 } 354 355 int 356 _splraise(int ipl) 357 { 358 359 return (ixp425_splraise(ipl)); 360 } 361 362 void 363 _setsoftintr(int si) 364 { 365 int oldirqstate; 366 367 oldirqstate = disable_interrupts(I32_bit); 368 ixp425_ipending |= SI_TO_IRQBIT(si); 369 restore_interrupts(oldirqstate); 370 371 /* Process unmasked pending soft interrupts. */ 372 if ((ixp425_ipending & INT_SWMASK) & ~curcpl()) 373 ixp425_do_pending(); 374 } 375 376 /* 377 * ixp425_icu_init: 378 * 379 * Called early in bootstrap to make clear interrupt register 380 */ 381 void 382 ixp425_icu_init(void) 383 { 384 385 intr_enabled = 0; /* All interrupts disabled */ 386 ixp425_set_intrmask(); 387 388 intr_steer = 0; /* All interrupts steered to IRQ */ 389 ixp425_set_intrsteer(); 390 } 391 392 /* 393 * ixp425_intr_init: 394 * 395 * Initialize the rest of the interrupt subsystem, making it 396 * ready to handle interrupts from devices. 397 */ 398 void 399 ixp425_intr_init(void) 400 { 401 struct intrq *iq; 402 int i; 403 404 intr_enabled = 0; 405 406 for (i = 0; i < NIRQ; i++) { 407 iq = &intrq[i]; 408 TAILQ_INIT(&iq->iq_list); 409 410 sprintf(iq->iq_name, "irq %d", i); 411 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 412 NULL, "ixp425", iq->iq_name); 413 } 414 415 ixp425_intr_calculate_masks(); 416 417 /* Enable IRQs (don't yet use FIQs). */ 418 enable_interrupts(I32_bit); 419 } 420 421 void * 422 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 423 { 424 struct intrq *iq; 425 struct intrhand *ih; 426 u_int oldirqstate; 427 428 if (irq < 0 || irq > NIRQ) 429 panic("ixp425_intr_establish: IRQ %d out of range", irq); 430 #ifdef DEBUG 431 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 432 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 433 #endif 434 435 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 436 if (ih == NULL) 437 return (NULL); 438 439 ih->ih_func = func; 440 ih->ih_arg = arg; 441 ih->ih_ipl = ipl; 442 ih->ih_irq = irq; 443 444 iq = &intrq[irq]; 445 446 /* All IXP425 interrupts are level-triggered. */ 447 iq->iq_ist = IST_LEVEL; /* XXX */ 448 449 oldirqstate = disable_interrupts(I32_bit); 450 451 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 452 453 ixp425_intr_calculate_masks(); 454 455 restore_interrupts(oldirqstate); 456 457 return (ih); 458 } 459 460 void 461 ixp425_intr_disestablish(void *cookie) 462 { 463 struct intrhand *ih = cookie; 464 struct intrq *iq = &intrq[ih->ih_irq]; 465 int oldirqstate; 466 467 oldirqstate = disable_interrupts(I32_bit); 468 469 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 470 471 ixp425_intr_calculate_masks(); 472 473 restore_interrupts(oldirqstate); 474 } 475 476 void 477 ixp425_intr_dispatch(struct clockframe *frame) 478 { 479 struct intrq *iq; 480 struct intrhand *ih; 481 int oldirqstate, pcpl, irq, ibit, hwpend; 482 483 pcpl = curcpl(); 484 485 hwpend = ixp425_irq_read(); 486 487 /* 488 * Disable all the interrupts that are pending. We will 489 * reenable them once they are processed and not masked. 490 */ 491 intr_enabled &= ~hwpend; 492 ixp425_set_intrmask(); 493 494 while (hwpend != 0) { 495 irq = ffs(hwpend) - 1; 496 ibit = (1U << irq); 497 498 hwpend &= ~ibit; 499 500 if (pcpl & ibit) { 501 /* 502 * IRQ is masked; mark it as pending and check 503 * the next one. Note: the IRQ is already disabled. 504 */ 505 ixp425_ipending |= ibit; 506 continue; 507 } 508 509 ixp425_ipending &= ~ibit; 510 511 iq = &intrq[irq]; 512 iq->iq_ev.ev_count++; 513 uvmexp.intrs++; 514 set_curcpl(pcpl | iq->iq_mask); 515 516 /* Clear down non-level triggered GPIO interrupts now */ 517 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 518 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 519 ixp425_irq2gpio_bit(irq); 520 } 521 522 oldirqstate = enable_interrupts(I32_bit); 523 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 524 ih = TAILQ_NEXT(ih, ih_list)) { 525 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 526 } 527 restore_interrupts(oldirqstate); 528 529 /* Clear down level triggered GPIO interrupts now */ 530 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 531 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 532 ixp425_irq2gpio_bit(irq); 533 } 534 535 set_curcpl(pcpl); 536 537 /* Re-enable this interrupt now that's it's cleared. */ 538 intr_enabled |= ibit; 539 ixp425_set_intrmask(); 540 541 /* 542 * Don't forget to include interrupts which may have 543 * arrived in the meantime. 544 */ 545 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~pcpl); 546 } 547 548 /* Check for pendings soft intrs. */ 549 if ((ixp425_ipending & INT_SWMASK) & ~curcpl()) { 550 oldirqstate = enable_interrupts(I32_bit); 551 ixp425_do_pending(); 552 restore_interrupts(oldirqstate); 553 } 554 } 555
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