ixp425_intr.c revision 1.15.36.3
1 /* $NetBSD: ixp425_intr.c,v 1.15.36.3 2008/02/18 21:04:24 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.15.36.3 2008/02/18 21:04:24 mjf Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Current interrupt priority level. */ 102 volatile int current_spl_level; 103 104 /* Interrupts pending. */ 105 volatile int ixp425_ipending; 106 107 /* Software copy of the IRQs we have enabled. */ 108 volatile uint32_t intr_enabled; 109 110 /* Mask if interrupts steered to FIQs. */ 111 uint32_t intr_steer; 112 113 #ifdef __HAVE_FAST_SOFTINTS 114 /* 115 * Map a software interrupt queue index 116 * 117 * XXX: !NOTE! :XXX 118 * We 'borrow' bits from the interrupt status register for interrupt sources 119 * which are not used by the current IXP425 port. Should any of the following 120 * interrupt sources be used at some future time, this must be revisited. 121 * 122 * Bit#31: SW Interrupt 1 123 * Bit#30: SW Interrupt 0 124 * Bit#14: Timestamp Timer 125 * Bit#11: General-purpose Timer 1 126 */ 127 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 128 IXP425_INT_bit31, /* SI_SOFT */ 129 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 130 IXP425_INT_bit14, /* SI_SOFTNET */ 131 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 132 }; 133 134 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 135 136 /* 137 * Map a software interrupt queue to an interrupt priority level. 138 */ 139 static const int si_to_ipl[] = { 140 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 141 [SI_SOFTBIO] = IPL_SOFTBIO, 142 [SI_SOFTNET] = IPL_SOFTNET, 143 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 144 }; 145 #endif /* __HAVE_FAST_SOFTINTS */ 146 void ixp425_intr_dispatch(struct clockframe *frame); 147 148 static inline uint32_t 149 ixp425_irq_read(void) 150 { 151 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 152 } 153 154 static inline void 155 ixp425_set_intrsteer(void) 156 { 157 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 158 } 159 160 static inline void 161 ixp425_enable_irq(int irq) 162 { 163 164 intr_enabled |= (1U << irq); 165 ixp425_set_intrmask(); 166 } 167 168 static inline void 169 ixp425_disable_irq(int irq) 170 { 171 172 intr_enabled &= ~(1U << irq); 173 ixp425_set_intrmask(); 174 } 175 176 static inline u_int32_t 177 ixp425_irq2gpio_bit(int irq) 178 { 179 180 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 181 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 182 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 183 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 184 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 185 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 186 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 187 0xff, 0xff /* INT#30 -> INT#31 */ 188 }; 189 190 #ifdef DEBUG 191 if (int2gpio[irq] == 0xff) 192 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 193 #endif 194 return (1U << int2gpio[irq]); 195 } 196 197 /* 198 * NOTE: This routine must be called with interrupts disabled in the CPSR. 199 */ 200 static void 201 ixp425_intr_calculate_masks(void) 202 { 203 struct intrq *iq; 204 struct intrhand *ih; 205 int irq, ipl; 206 207 /* First, figure out which IPLs each IRQ has. */ 208 for (irq = 0; irq < NIRQ; irq++) { 209 int levels = 0; 210 iq = &intrq[irq]; 211 ixp425_disable_irq(irq); 212 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 213 ih = TAILQ_NEXT(ih, ih_list)) 214 levels |= (1U << ih->ih_ipl); 215 iq->iq_levels = levels; 216 } 217 218 /* Next, figure out which IRQs are used by each IPL. */ 219 for (ipl = 0; ipl < NIPL; ipl++) { 220 int irqs = 0; 221 for (irq = 0; irq < NIRQ; irq++) { 222 if (intrq[irq].iq_levels & (1U << ipl)) 223 irqs |= (1U << irq); 224 } 225 ixp425_imask[ipl] = irqs; 226 } 227 228 KASSERT(ixp425_imask[IPL_NONE] == 0); 229 230 #ifdef __HAVE_FAST_SOFTINTS 231 /* 232 * Initialize the soft interrupt masks to block themselves. 233 */ 234 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 235 ixp425_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO); 236 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 237 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 238 #endif 239 240 /* 241 * Enforce a hierarchy that gives "slow" device (or devices with 242 * limited input buffer space/"real-time" requirements) a better 243 * chance at not dropping data. 244 */ 245 ixp425_imask[IPL_SOFTBIO] |= ixp425_imask[IPL_SOFTCLOCK]; 246 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTBIO]; 247 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_SOFTNET]; 248 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_SOFTSERIAL]; 249 ixp425_imask[IPL_SCHED] |= ixp425_imask[IPL_VM]; 250 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED]; 251 252 /* 253 * Now compute which IRQs must be blocked when servicing any 254 * given IRQ. 255 */ 256 for (irq = 0; irq < NIRQ; irq++) { 257 int irqs = (1U << irq); 258 iq = &intrq[irq]; 259 if (TAILQ_FIRST(&iq->iq_list) != NULL) 260 ixp425_enable_irq(irq); 261 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 262 ih = TAILQ_NEXT(ih, ih_list)) 263 irqs |= ixp425_imask[ih->ih_ipl]; 264 iq->iq_mask = irqs; 265 } 266 } 267 268 #ifdef __HAVE_FAST_SOFTINTS 269 void 270 ixp425_do_pending(void) 271 { 272 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 273 int new, oldirqstate; 274 275 if (__cpu_simple_lock_try(&processing) == 0) 276 return; 277 278 new = current_spl_level; 279 280 oldirqstate = disable_interrupts(I32_bit); 281 282 #define DO_SOFTINT(si) \ 283 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 284 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 285 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 286 restore_interrupts(oldirqstate); \ 287 softintr_dispatch(si); \ 288 oldirqstate = disable_interrupts(I32_bit); \ 289 current_spl_level = new; \ 290 } 291 292 DO_SOFTINT(SI_SOFTSERIAL); 293 DO_SOFTINT(SI_SOFTNET); 294 DO_SOFTINT(SI_SOFTCLOCK); 295 DO_SOFTINT(SI_SOFT); 296 297 __cpu_simple_unlock(&processing); 298 299 restore_interrupts(oldirqstate); 300 } 301 #endif 302 303 void 304 splx(int new) 305 { 306 307 ixp425_splx(new); 308 } 309 310 int 311 _spllower(int ipl) 312 { 313 314 return (ixp425_spllower(ipl)); 315 } 316 317 int 318 _splraise(int ipl) 319 { 320 321 return (ixp425_splraise(ipl)); 322 } 323 324 #ifdef __HAVE_FAST_SOFTINTS 325 void 326 _setsoftintr(int si) 327 { 328 int oldirqstate; 329 330 oldirqstate = disable_interrupts(I32_bit); 331 ixp425_ipending |= SI_TO_IRQBIT(si); 332 restore_interrupts(oldirqstate); 333 334 /* Process unmasked pending soft interrupts. */ 335 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 336 ixp425_do_pending(); 337 } 338 #endif /* __HAVE_FAST_SOFTINTS */ 339 340 /* 341 * ixp425_icu_init: 342 * 343 * Called early in bootstrap to make clear interrupt register 344 */ 345 void 346 ixp425_icu_init(void) 347 { 348 349 intr_enabled = 0; /* All interrupts disabled */ 350 ixp425_set_intrmask(); 351 352 intr_steer = 0; /* All interrupts steered to IRQ */ 353 ixp425_set_intrsteer(); 354 } 355 356 /* 357 * ixp425_intr_init: 358 * 359 * Initialize the rest of the interrupt subsystem, making it 360 * ready to handle interrupts from devices. 361 */ 362 void 363 ixp425_intr_init(void) 364 { 365 struct intrq *iq; 366 int i; 367 368 intr_enabled = 0; 369 370 for (i = 0; i < NIRQ; i++) { 371 iq = &intrq[i]; 372 TAILQ_INIT(&iq->iq_list); 373 374 sprintf(iq->iq_name, "irq %d", i); 375 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 376 NULL, "ixp425", iq->iq_name); 377 } 378 379 ixp425_intr_calculate_masks(); 380 381 /* Enable IRQs (don't yet use FIQs). */ 382 enable_interrupts(I32_bit); 383 } 384 385 void * 386 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 387 { 388 struct intrq *iq; 389 struct intrhand *ih; 390 u_int oldirqstate; 391 392 if (irq < 0 || irq > NIRQ) 393 panic("ixp425_intr_establish: IRQ %d out of range", irq); 394 #ifdef DEBUG 395 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 396 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 397 #endif 398 399 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 400 if (ih == NULL) 401 return (NULL); 402 403 ih->ih_func = func; 404 ih->ih_arg = arg; 405 ih->ih_ipl = ipl; 406 ih->ih_irq = irq; 407 408 iq = &intrq[irq]; 409 410 /* All IXP425 interrupts are level-triggered. */ 411 iq->iq_ist = IST_LEVEL; /* XXX */ 412 413 oldirqstate = disable_interrupts(I32_bit); 414 415 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 416 417 ixp425_intr_calculate_masks(); 418 419 restore_interrupts(oldirqstate); 420 421 return (ih); 422 } 423 424 void 425 ixp425_intr_disestablish(void *cookie) 426 { 427 struct intrhand *ih = cookie; 428 struct intrq *iq = &intrq[ih->ih_irq]; 429 int oldirqstate; 430 431 oldirqstate = disable_interrupts(I32_bit); 432 433 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 434 435 ixp425_intr_calculate_masks(); 436 437 restore_interrupts(oldirqstate); 438 } 439 440 void 441 ixp425_intr_dispatch(struct clockframe *frame) 442 { 443 struct intrq *iq; 444 struct intrhand *ih; 445 int oldirqstate, pcpl, irq, ibit, hwpend; 446 struct cpu_info *ci; 447 448 ci = curcpu(); 449 ci->ci_idepth++; 450 pcpl = current_spl_level; 451 hwpend = ixp425_irq_read(); 452 453 /* 454 * Disable all the interrupts that are pending. We will 455 * reenable them once they are processed and not masked. 456 */ 457 intr_enabled &= ~hwpend; 458 ixp425_set_intrmask(); 459 460 while (hwpend != 0) { 461 irq = ffs(hwpend) - 1; 462 ibit = (1U << irq); 463 464 hwpend &= ~ibit; 465 466 if (pcpl & ibit) { 467 /* 468 * IRQ is masked; mark it as pending and check 469 * the next one. Note: the IRQ is already disabled. 470 */ 471 ixp425_ipending |= ibit; 472 continue; 473 } 474 475 ixp425_ipending &= ~ibit; 476 477 iq = &intrq[irq]; 478 iq->iq_ev.ev_count++; 479 uvmexp.intrs++; 480 current_spl_level |= iq->iq_mask; 481 482 /* Clear down non-level triggered GPIO interrupts now */ 483 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 484 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 485 ixp425_irq2gpio_bit(irq); 486 } 487 488 oldirqstate = enable_interrupts(I32_bit); 489 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 490 ih = TAILQ_NEXT(ih, ih_list)) { 491 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 492 } 493 restore_interrupts(oldirqstate); 494 495 /* Clear down level triggered GPIO interrupts now */ 496 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 497 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 498 ixp425_irq2gpio_bit(irq); 499 } 500 501 current_spl_level = pcpl; 502 503 /* Re-enable this interrupt now that's it's cleared. */ 504 intr_enabled |= ibit; 505 ixp425_set_intrmask(); 506 507 /* 508 * Don't forget to include interrupts which may have 509 * arrived in the meantime. 510 */ 511 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~pcpl); 512 } 513 ci->ci_idepth--; 514 515 #ifdef __HAVE_FAST_SOFTINTS 516 /* Check for pendings soft intrs. */ 517 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 518 oldirqstate = enable_interrupts(I32_bit); 519 ixp425_do_pending(); 520 restore_interrupts(oldirqstate); 521 } 522 #endif 523 } 524
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