ixp425_intr.c revision 1.17
1 /* $NetBSD: ixp425_intr.c,v 1.17 2007/12/11 17:12:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.17 2007/12/11 17:12:27 ad Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Current interrupt priority level. */ 102 volatile int current_spl_level; 103 104 /* Interrupts pending. */ 105 volatile int ixp425_ipending; 106 107 /* Software copy of the IRQs we have enabled. */ 108 volatile uint32_t intr_enabled; 109 110 /* Mask if interrupts steered to FIQs. */ 111 uint32_t intr_steer; 112 113 /* 114 * Map a software interrupt queue index 115 * 116 * XXX: !NOTE! :XXX 117 * We 'borrow' bits from the interrupt status register for interrupt sources 118 * which are not used by the current IXP425 port. Should any of the following 119 * interrupt sources be used at some future time, this must be revisited. 120 * 121 * Bit#31: SW Interrupt 1 122 * Bit#30: SW Interrupt 0 123 * Bit#14: Timestamp Timer 124 * Bit#11: General-purpose Timer 1 125 */ 126 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 127 IXP425_INT_bit31, /* SI_SOFT */ 128 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 129 IXP425_INT_bit14, /* SI_SOFTNET */ 130 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 131 }; 132 133 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 134 135 /* 136 * Map a software interrupt queue to an interrupt priority level. 137 */ 138 static const int si_to_ipl[SI_NQUEUES] = { 139 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 140 IPL_SOFTBIO, /* SI_SOFTBIO */ 141 IPL_SOFTNET, /* SI_SOFTNET */ 142 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 143 }; 144 145 void ixp425_intr_dispatch(struct clockframe *frame); 146 147 static inline uint32_t 148 ixp425_irq_read(void) 149 { 150 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 151 } 152 153 static inline void 154 ixp425_set_intrsteer(void) 155 { 156 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 157 } 158 159 static inline void 160 ixp425_enable_irq(int irq) 161 { 162 163 intr_enabled |= (1U << irq); 164 ixp425_set_intrmask(); 165 } 166 167 static inline void 168 ixp425_disable_irq(int irq) 169 { 170 171 intr_enabled &= ~(1U << irq); 172 ixp425_set_intrmask(); 173 } 174 175 static inline u_int32_t 176 ixp425_irq2gpio_bit(int irq) 177 { 178 179 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 180 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 181 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 182 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 183 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 184 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 185 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 186 0xff, 0xff /* INT#30 -> INT#31 */ 187 }; 188 189 #ifdef DEBUG 190 if (int2gpio[irq] == 0xff) 191 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 192 #endif 193 return (1U << int2gpio[irq]); 194 } 195 196 /* 197 * NOTE: This routine must be called with interrupts disabled in the CPSR. 198 */ 199 static void 200 ixp425_intr_calculate_masks(void) 201 { 202 struct intrq *iq; 203 struct intrhand *ih; 204 int irq, ipl; 205 206 /* First, figure out which IPLs each IRQ has. */ 207 for (irq = 0; irq < NIRQ; irq++) { 208 int levels = 0; 209 iq = &intrq[irq]; 210 ixp425_disable_irq(irq); 211 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 212 ih = TAILQ_NEXT(ih, ih_list)) 213 levels |= (1U << ih->ih_ipl); 214 iq->iq_levels = levels; 215 } 216 217 /* Next, figure out which IRQs are used by each IPL. */ 218 for (ipl = 0; ipl < NIPL; ipl++) { 219 int irqs = 0; 220 for (irq = 0; irq < NIRQ; irq++) { 221 if (intrq[irq].iq_levels & (1U << ipl)) 222 irqs |= (1U << irq); 223 } 224 ixp425_imask[ipl] = irqs; 225 } 226 227 ixp425_imask[IPL_NONE] = 0; 228 229 /* 230 * Initialize the soft interrupt masks to block themselves. 231 */ 232 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 233 ixp425_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO); 234 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 235 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 236 237 /* 238 * Enforce a hierarchy that gives "slow" device (or devices with 239 * limited input buffer space/"real-time" requirements) a better 240 * chance at not dropping data. 241 */ 242 ixp425_imask[IPL_SOFTBIO] |= ixp425_imask[IPL_SOFTCLOCK]; 243 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTBIO]; 244 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_SOFTNET]; 245 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_SOFTSERIAL]; 246 ixp425_imask[IPL_SCHED] |= ixp425_imask[IPL_VM]; 247 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED]; 248 249 /* 250 * Now compute which IRQs must be blocked when servicing any 251 * given IRQ. 252 */ 253 for (irq = 0; irq < NIRQ; irq++) { 254 int irqs = (1U << irq); 255 iq = &intrq[irq]; 256 if (TAILQ_FIRST(&iq->iq_list) != NULL) 257 ixp425_enable_irq(irq); 258 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 259 ih = TAILQ_NEXT(ih, ih_list)) 260 irqs |= ixp425_imask[ih->ih_ipl]; 261 iq->iq_mask = irqs; 262 } 263 } 264 265 void 266 ixp425_do_pending(void) 267 { 268 #ifdef __HAVE_FAST_SOFTINTS 269 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 270 int new, oldirqstate; 271 272 if (__cpu_simple_lock_try(&processing) == 0) 273 return; 274 275 new = current_spl_level; 276 277 oldirqstate = disable_interrupts(I32_bit); 278 279 #define DO_SOFTINT(si) \ 280 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 281 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 282 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 283 restore_interrupts(oldirqstate); \ 284 softintr_dispatch(si); \ 285 oldirqstate = disable_interrupts(I32_bit); \ 286 current_spl_level = new; \ 287 } 288 289 DO_SOFTINT(SI_SOFTSERIAL); 290 DO_SOFTINT(SI_SOFTNET); 291 DO_SOFTINT(SI_SOFTCLOCK); 292 DO_SOFTINT(SI_SOFT); 293 294 __cpu_simple_unlock(&processing); 295 296 restore_interrupts(oldirqstate); 297 #endif 298 } 299 300 void 301 splx(int new) 302 { 303 304 ixp425_splx(new); 305 } 306 307 int 308 _spllower(int ipl) 309 { 310 311 return (ixp425_spllower(ipl)); 312 } 313 314 int 315 _splraise(int ipl) 316 { 317 318 return (ixp425_splraise(ipl)); 319 } 320 321 void 322 _setsoftintr(int si) 323 { 324 int oldirqstate; 325 326 oldirqstate = disable_interrupts(I32_bit); 327 ixp425_ipending |= SI_TO_IRQBIT(si); 328 restore_interrupts(oldirqstate); 329 330 /* Process unmasked pending soft interrupts. */ 331 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 332 ixp425_do_pending(); 333 } 334 335 /* 336 * ixp425_icu_init: 337 * 338 * Called early in bootstrap to make clear interrupt register 339 */ 340 void 341 ixp425_icu_init(void) 342 { 343 344 intr_enabled = 0; /* All interrupts disabled */ 345 ixp425_set_intrmask(); 346 347 intr_steer = 0; /* All interrupts steered to IRQ */ 348 ixp425_set_intrsteer(); 349 } 350 351 /* 352 * ixp425_intr_init: 353 * 354 * Initialize the rest of the interrupt subsystem, making it 355 * ready to handle interrupts from devices. 356 */ 357 void 358 ixp425_intr_init(void) 359 { 360 struct intrq *iq; 361 int i; 362 363 intr_enabled = 0; 364 365 for (i = 0; i < NIRQ; i++) { 366 iq = &intrq[i]; 367 TAILQ_INIT(&iq->iq_list); 368 369 sprintf(iq->iq_name, "irq %d", i); 370 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 371 NULL, "ixp425", iq->iq_name); 372 } 373 374 ixp425_intr_calculate_masks(); 375 376 /* Enable IRQs (don't yet use FIQs). */ 377 enable_interrupts(I32_bit); 378 } 379 380 void * 381 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 382 { 383 struct intrq *iq; 384 struct intrhand *ih; 385 u_int oldirqstate; 386 387 if (irq < 0 || irq > NIRQ) 388 panic("ixp425_intr_establish: IRQ %d out of range", irq); 389 #ifdef DEBUG 390 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 391 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 392 #endif 393 394 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 395 if (ih == NULL) 396 return (NULL); 397 398 ih->ih_func = func; 399 ih->ih_arg = arg; 400 ih->ih_ipl = ipl; 401 ih->ih_irq = irq; 402 403 iq = &intrq[irq]; 404 405 /* All IXP425 interrupts are level-triggered. */ 406 iq->iq_ist = IST_LEVEL; /* XXX */ 407 408 oldirqstate = disable_interrupts(I32_bit); 409 410 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 411 412 ixp425_intr_calculate_masks(); 413 414 restore_interrupts(oldirqstate); 415 416 return (ih); 417 } 418 419 void 420 ixp425_intr_disestablish(void *cookie) 421 { 422 struct intrhand *ih = cookie; 423 struct intrq *iq = &intrq[ih->ih_irq]; 424 int oldirqstate; 425 426 oldirqstate = disable_interrupts(I32_bit); 427 428 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 429 430 ixp425_intr_calculate_masks(); 431 432 restore_interrupts(oldirqstate); 433 } 434 435 void 436 ixp425_intr_dispatch(struct clockframe *frame) 437 { 438 struct intrq *iq; 439 struct intrhand *ih; 440 int oldirqstate, pcpl, irq, ibit, hwpend; 441 struct cpu_info *ci; 442 443 ci = curcpu(); 444 ci->ci_idepth++; 445 pcpl = current_spl_level; 446 hwpend = ixp425_irq_read(); 447 448 /* 449 * Disable all the interrupts that are pending. We will 450 * reenable them once they are processed and not masked. 451 */ 452 intr_enabled &= ~hwpend; 453 ixp425_set_intrmask(); 454 455 while (hwpend != 0) { 456 irq = ffs(hwpend) - 1; 457 ibit = (1U << irq); 458 459 hwpend &= ~ibit; 460 461 if (pcpl & ibit) { 462 /* 463 * IRQ is masked; mark it as pending and check 464 * the next one. Note: the IRQ is already disabled. 465 */ 466 ixp425_ipending |= ibit; 467 continue; 468 } 469 470 ixp425_ipending &= ~ibit; 471 472 iq = &intrq[irq]; 473 iq->iq_ev.ev_count++; 474 uvmexp.intrs++; 475 current_spl_level |= iq->iq_mask; 476 477 /* Clear down non-level triggered GPIO interrupts now */ 478 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 479 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 480 ixp425_irq2gpio_bit(irq); 481 } 482 483 oldirqstate = enable_interrupts(I32_bit); 484 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 485 ih = TAILQ_NEXT(ih, ih_list)) { 486 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 487 } 488 restore_interrupts(oldirqstate); 489 490 /* Clear down level triggered GPIO interrupts now */ 491 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 492 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 493 ixp425_irq2gpio_bit(irq); 494 } 495 496 current_spl_level = pcpl; 497 498 /* Re-enable this interrupt now that's it's cleared. */ 499 intr_enabled |= ibit; 500 ixp425_set_intrmask(); 501 502 /* 503 * Don't forget to include interrupts which may have 504 * arrived in the meantime. 505 */ 506 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~pcpl); 507 } 508 ci->ci_idepth--; 509 510 /* Check for pendings soft intrs. */ 511 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 512 oldirqstate = enable_interrupts(I32_bit); 513 ixp425_do_pending(); 514 restore_interrupts(oldirqstate); 515 } 516 } 517
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