ixp425_intr.c revision 1.18.10.1
1 /* $NetBSD: ixp425_intr.c,v 1.18.10.1 2008/05/16 02:22:04 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.18.10.1 2008/05/16 02:22:04 yamt Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Interrupts pending. */ 102 volatile int ixp425_ipending; 103 104 /* Software copy of the IRQs we have enabled. */ 105 volatile uint32_t intr_enabled; 106 107 /* Mask if interrupts steered to FIQs. */ 108 uint32_t intr_steer; 109 110 #ifdef __HAVE_FAST_SOFTINTS 111 /* 112 * Map a software interrupt queue index 113 * 114 * XXX: !NOTE! :XXX 115 * We 'borrow' bits from the interrupt status register for interrupt sources 116 * which are not used by the current IXP425 port. Should any of the following 117 * interrupt sources be used at some future time, this must be revisited. 118 * 119 * Bit#31: SW Interrupt 1 120 * Bit#30: SW Interrupt 0 121 * Bit#14: Timestamp Timer 122 * Bit#11: General-purpose Timer 1 123 */ 124 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 125 IXP425_INT_bit31, /* SI_SOFT */ 126 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 127 IXP425_INT_bit14, /* SI_SOFTNET */ 128 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 129 }; 130 131 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 132 133 /* 134 * Map a software interrupt queue to an interrupt priority level. 135 */ 136 static const int si_to_ipl[] = { 137 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 138 [SI_SOFTBIO] = IPL_SOFTBIO, 139 [SI_SOFTNET] = IPL_SOFTNET, 140 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 141 }; 142 #endif /* __HAVE_FAST_SOFTINTS */ 143 void ixp425_intr_dispatch(struct clockframe *frame); 144 145 static inline uint32_t 146 ixp425_irq_read(void) 147 { 148 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 149 } 150 151 static inline void 152 ixp425_set_intrsteer(void) 153 { 154 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 155 } 156 157 static inline void 158 ixp425_enable_irq(int irq) 159 { 160 161 intr_enabled |= (1U << irq); 162 ixp425_set_intrmask(); 163 } 164 165 static inline void 166 ixp425_disable_irq(int irq) 167 { 168 169 intr_enabled &= ~(1U << irq); 170 ixp425_set_intrmask(); 171 } 172 173 static inline u_int32_t 174 ixp425_irq2gpio_bit(int irq) 175 { 176 177 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 178 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 179 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 180 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 181 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 182 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 183 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 184 0xff, 0xff /* INT#30 -> INT#31 */ 185 }; 186 187 #ifdef DEBUG 188 if (int2gpio[irq] == 0xff) 189 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 190 #endif 191 return (1U << int2gpio[irq]); 192 } 193 194 /* 195 * NOTE: This routine must be called with interrupts disabled in the CPSR. 196 */ 197 static void 198 ixp425_intr_calculate_masks(void) 199 { 200 struct intrq *iq; 201 struct intrhand *ih; 202 int irq, ipl; 203 204 /* First, figure out which IPLs each IRQ has. */ 205 for (irq = 0; irq < NIRQ; irq++) { 206 int levels = 0; 207 iq = &intrq[irq]; 208 ixp425_disable_irq(irq); 209 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 210 ih = TAILQ_NEXT(ih, ih_list)) 211 levels |= (1U << ih->ih_ipl); 212 iq->iq_levels = levels; 213 } 214 215 /* Next, figure out which IRQs are used by each IPL. */ 216 for (ipl = 0; ipl < NIPL; ipl++) { 217 int irqs = 0; 218 for (irq = 0; irq < NIRQ; irq++) { 219 if (intrq[irq].iq_levels & (1U << ipl)) 220 irqs |= (1U << irq); 221 } 222 ixp425_imask[ipl] = irqs; 223 } 224 225 KASSERT(ixp425_imask[IPL_NONE] == 0); 226 227 #ifdef __HAVE_FAST_SOFTINTS 228 /* 229 * Initialize the soft interrupt masks to block themselves. 230 */ 231 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 232 ixp425_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO); 233 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 234 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 235 #endif 236 237 /* 238 * Enforce a hierarchy that gives "slow" device (or devices with 239 * limited input buffer space/"real-time" requirements) a better 240 * chance at not dropping data. 241 */ 242 ixp425_imask[IPL_SOFTBIO] |= ixp425_imask[IPL_SOFTCLOCK]; 243 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTBIO]; 244 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_SOFTNET]; 245 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_SOFTSERIAL]; 246 ixp425_imask[IPL_SCHED] |= ixp425_imask[IPL_VM]; 247 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED]; 248 249 /* 250 * Now compute which IRQs must be blocked when servicing any 251 * given IRQ. 252 */ 253 for (irq = 0; irq < NIRQ; irq++) { 254 int irqs = (1U << irq); 255 iq = &intrq[irq]; 256 if (TAILQ_FIRST(&iq->iq_list) != NULL) 257 ixp425_enable_irq(irq); 258 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 259 ih = TAILQ_NEXT(ih, ih_list)) 260 irqs |= ixp425_imask[ih->ih_ipl]; 261 iq->iq_mask = irqs; 262 } 263 } 264 265 void 266 splx(int new) 267 { 268 ixp425_splx(new); 269 } 270 271 int 272 _spllower(int ipl) 273 { 274 return (ixp425_spllower(ipl)); 275 } 276 277 int 278 _splraise(int ipl) 279 { 280 return (ixp425_splraise(ipl)); 281 } 282 283 /* 284 * ixp425_icu_init: 285 * 286 * Called early in bootstrap to make clear interrupt register 287 */ 288 void 289 ixp425_icu_init(void) 290 { 291 292 intr_enabled = 0; /* All interrupts disabled */ 293 ixp425_set_intrmask(); 294 295 intr_steer = 0; /* All interrupts steered to IRQ */ 296 ixp425_set_intrsteer(); 297 } 298 299 /* 300 * ixp425_intr_init: 301 * 302 * Initialize the rest of the interrupt subsystem, making it 303 * ready to handle interrupts from devices. 304 */ 305 void 306 ixp425_intr_init(void) 307 { 308 struct intrq *iq; 309 int i; 310 311 intr_enabled = 0; 312 313 for (i = 0; i < NIRQ; i++) { 314 iq = &intrq[i]; 315 TAILQ_INIT(&iq->iq_list); 316 317 sprintf(iq->iq_name, "irq %d", i); 318 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 319 NULL, "ixp425", iq->iq_name); 320 } 321 322 ixp425_intr_calculate_masks(); 323 324 /* Enable IRQs (don't yet use FIQs). */ 325 enable_interrupts(I32_bit); 326 } 327 328 void * 329 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 330 { 331 struct intrq *iq; 332 struct intrhand *ih; 333 u_int oldirqstate; 334 335 if (irq < 0 || irq > NIRQ) 336 panic("ixp425_intr_establish: IRQ %d out of range", irq); 337 #ifdef DEBUG 338 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 339 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 340 #endif 341 342 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 343 if (ih == NULL) 344 return (NULL); 345 346 ih->ih_func = func; 347 ih->ih_arg = arg; 348 ih->ih_ipl = ipl; 349 ih->ih_irq = irq; 350 351 iq = &intrq[irq]; 352 353 /* All IXP425 interrupts are level-triggered. */ 354 iq->iq_ist = IST_LEVEL; /* XXX */ 355 356 oldirqstate = disable_interrupts(I32_bit); 357 358 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 359 360 ixp425_intr_calculate_masks(); 361 362 restore_interrupts(oldirqstate); 363 364 return (ih); 365 } 366 367 void 368 ixp425_intr_disestablish(void *cookie) 369 { 370 struct intrhand *ih = cookie; 371 struct intrq *iq = &intrq[ih->ih_irq]; 372 int oldirqstate; 373 374 oldirqstate = disable_interrupts(I32_bit); 375 376 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 377 378 ixp425_intr_calculate_masks(); 379 380 restore_interrupts(oldirqstate); 381 } 382 383 void 384 ixp425_intr_dispatch(struct clockframe *frame) 385 { 386 struct intrq *iq; 387 struct intrhand *ih; 388 int oldirqstate, irq, ibit, hwpend; 389 struct cpu_info * const ci = curcpu(); 390 const int ppl = ci->ci_cpl; 391 const uint32_t imask = ixp425_imask[ppl]; 392 393 hwpend = ixp425_irq_read(); 394 395 /* 396 * Disable all the interrupts that are pending. We will 397 * reenable them once they are processed and not masked. 398 */ 399 intr_enabled &= ~hwpend; 400 ixp425_set_intrmask(); 401 402 while (hwpend != 0) { 403 irq = ffs(hwpend) - 1; 404 ibit = (1U << irq); 405 406 hwpend &= ~ibit; 407 408 if (imask & ibit) { 409 /* 410 * IRQ is masked; mark it as pending and check 411 * the next one. Note: the IRQ is already disabled. 412 */ 413 ixp425_ipending |= ibit; 414 continue; 415 } 416 417 ixp425_ipending &= ~ibit; 418 419 iq = &intrq[irq]; 420 iq->iq_ev.ev_count++; 421 uvmexp.intrs++; 422 423 /* Clear down non-level triggered GPIO interrupts now */ 424 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 425 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 426 ixp425_irq2gpio_bit(irq); 427 } 428 429 TAILQ_FOREACH(ih, &iq->iq_list, ih_list) { 430 ci->ci_cpl = ih->ih_ipl; 431 oldirqstate = enable_interrupts(I32_bit); 432 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 433 restore_interrupts(oldirqstate); 434 } 435 436 /* Clear down level triggered GPIO interrupts now */ 437 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 438 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 439 ixp425_irq2gpio_bit(irq); 440 } 441 442 ci->ci_cpl = ppl; 443 444 /* Re-enable this interrupt now that's it's cleared. */ 445 intr_enabled |= ibit; 446 ixp425_set_intrmask(); 447 448 /* 449 * Don't forget to include interrupts which may have 450 * arrived in the meantime. 451 */ 452 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~imask); 453 } 454 455 #ifdef __HAVE_FAST_SOFTINTS 456 cpu_dosoftints(); 457 #endif 458 } 459
Indexes created Tue Oct 21 12:09:54 GMT 2025