ixp425_intr.c revision 1.18.10.2
1 /* $NetBSD: ixp425_intr.c,v 1.18.10.2 2010/03/11 15:02:07 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 /* 30 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 31 * All rights reserved. 32 * 33 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed for the NetBSD Project by 46 * Wasabi Systems, Inc. 47 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 48 * or promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.18.10.2 2010/03/11 15:02:07 yamt Exp $"); 66 67 #ifndef EVBARM_SPL_NOINLINE 68 #define EVBARM_SPL_NOINLINE 69 #endif 70 71 /* 72 * Interrupt support for the Intel IXP425 NetworkProcessor. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/malloc.h> 78 79 #include <uvm/uvm_extern.h> 80 81 #include <machine/bus.h> 82 #include <machine/intr.h> 83 84 #include <arm/cpufunc.h> 85 86 #include <arm/xscale/ixp425reg.h> 87 #include <arm/xscale/ixp425var.h> 88 89 /* Interrupt handler queues. */ 90 struct intrq intrq[NIRQ]; 91 92 /* Interrupts to mask at each level. */ 93 int ixp425_imask[NIPL]; 94 95 /* Interrupts pending. */ 96 volatile int ixp425_ipending; 97 98 /* Software copy of the IRQs we have enabled. */ 99 volatile uint32_t intr_enabled; 100 101 /* Mask if interrupts steered to FIQs. */ 102 uint32_t intr_steer; 103 104 #ifdef __HAVE_FAST_SOFTINTS 105 /* 106 * Map a software interrupt queue index 107 * 108 * XXX: !NOTE! :XXX 109 * We 'borrow' bits from the interrupt status register for interrupt sources 110 * which are not used by the current IXP425 port. Should any of the following 111 * interrupt sources be used at some future time, this must be revisited. 112 * 113 * Bit#31: SW Interrupt 1 114 * Bit#30: SW Interrupt 0 115 * Bit#14: Timestamp Timer 116 * Bit#11: General-purpose Timer 1 117 */ 118 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 119 IXP425_INT_bit31, /* SI_SOFT */ 120 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 121 IXP425_INT_bit14, /* SI_SOFTNET */ 122 IXP425_INT_bit11, /* SI_SOFTSERIAL */ 123 }; 124 125 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 126 127 /* 128 * Map a software interrupt queue to an interrupt priority level. 129 */ 130 static const int si_to_ipl[] = { 131 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 132 [SI_SOFTBIO] = IPL_SOFTBIO, 133 [SI_SOFTNET] = IPL_SOFTNET, 134 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 135 }; 136 #endif /* __HAVE_FAST_SOFTINTS */ 137 void ixp425_intr_dispatch(struct clockframe *frame); 138 139 static inline uint32_t 140 ixp425_irq_read(void) 141 { 142 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 143 } 144 145 static inline void 146 ixp425_set_intrsteer(void) 147 { 148 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 149 } 150 151 static inline void 152 ixp425_enable_irq(int irq) 153 { 154 155 intr_enabled |= (1U << irq); 156 ixp425_set_intrmask(); 157 } 158 159 static inline void 160 ixp425_disable_irq(int irq) 161 { 162 163 intr_enabled &= ~(1U << irq); 164 ixp425_set_intrmask(); 165 } 166 167 static inline u_int32_t 168 ixp425_irq2gpio_bit(int irq) 169 { 170 171 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 172 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 173 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 174 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 175 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 176 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 177 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 178 0xff, 0xff /* INT#30 -> INT#31 */ 179 }; 180 181 #ifdef DEBUG 182 if (int2gpio[irq] == 0xff) 183 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 184 #endif 185 return (1U << int2gpio[irq]); 186 } 187 188 /* 189 * NOTE: This routine must be called with interrupts disabled in the CPSR. 190 */ 191 static void 192 ixp425_intr_calculate_masks(void) 193 { 194 struct intrq *iq; 195 struct intrhand *ih; 196 int irq, ipl; 197 198 /* First, figure out which IPLs each IRQ has. */ 199 for (irq = 0; irq < NIRQ; irq++) { 200 int levels = 0; 201 iq = &intrq[irq]; 202 ixp425_disable_irq(irq); 203 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 204 ih = TAILQ_NEXT(ih, ih_list)) 205 levels |= (1U << ih->ih_ipl); 206 iq->iq_levels = levels; 207 } 208 209 /* Next, figure out which IRQs are used by each IPL. */ 210 for (ipl = 0; ipl < NIPL; ipl++) { 211 int irqs = 0; 212 for (irq = 0; irq < NIRQ; irq++) { 213 if (intrq[irq].iq_levels & (1U << ipl)) 214 irqs |= (1U << irq); 215 } 216 ixp425_imask[ipl] = irqs; 217 } 218 219 KASSERT(ixp425_imask[IPL_NONE] == 0); 220 221 #ifdef __HAVE_FAST_SOFTINTS 222 /* 223 * Initialize the soft interrupt masks to block themselves. 224 */ 225 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 226 ixp425_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO); 227 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 228 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 229 #endif 230 231 /* 232 * Enforce a hierarchy that gives "slow" device (or devices with 233 * limited input buffer space/"real-time" requirements) a better 234 * chance at not dropping data. 235 */ 236 ixp425_imask[IPL_SOFTBIO] |= ixp425_imask[IPL_SOFTCLOCK]; 237 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTBIO]; 238 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_SOFTNET]; 239 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_SOFTSERIAL]; 240 ixp425_imask[IPL_SCHED] |= ixp425_imask[IPL_VM]; 241 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED]; 242 243 /* 244 * Now compute which IRQs must be blocked when servicing any 245 * given IRQ. 246 */ 247 for (irq = 0; irq < NIRQ; irq++) { 248 int irqs = (1U << irq); 249 iq = &intrq[irq]; 250 if (TAILQ_FIRST(&iq->iq_list) != NULL) 251 ixp425_enable_irq(irq); 252 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 253 ih = TAILQ_NEXT(ih, ih_list)) 254 irqs |= ixp425_imask[ih->ih_ipl]; 255 iq->iq_mask = irqs; 256 } 257 } 258 259 void 260 splx(int new) 261 { 262 ixp425_splx(new); 263 } 264 265 int 266 _spllower(int ipl) 267 { 268 return (ixp425_spllower(ipl)); 269 } 270 271 int 272 _splraise(int ipl) 273 { 274 return (ixp425_splraise(ipl)); 275 } 276 277 /* 278 * ixp425_icu_init: 279 * 280 * Called early in bootstrap to make clear interrupt register 281 */ 282 void 283 ixp425_icu_init(void) 284 { 285 286 intr_enabled = 0; /* All interrupts disabled */ 287 ixp425_set_intrmask(); 288 289 intr_steer = 0; /* All interrupts steered to IRQ */ 290 ixp425_set_intrsteer(); 291 } 292 293 /* 294 * ixp425_intr_init: 295 * 296 * Initialize the rest of the interrupt subsystem, making it 297 * ready to handle interrupts from devices. 298 */ 299 void 300 ixp425_intr_init(void) 301 { 302 struct intrq *iq; 303 int i; 304 305 intr_enabled = 0; 306 307 for (i = 0; i < NIRQ; i++) { 308 iq = &intrq[i]; 309 TAILQ_INIT(&iq->iq_list); 310 311 sprintf(iq->iq_name, "irq %d", i); 312 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 313 NULL, "ixp425", iq->iq_name); 314 } 315 316 ixp425_intr_calculate_masks(); 317 318 /* Enable IRQs (don't yet use FIQs). */ 319 enable_interrupts(I32_bit); 320 } 321 322 void * 323 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 324 { 325 struct intrq *iq; 326 struct intrhand *ih; 327 u_int oldirqstate; 328 329 if (irq < 0 || irq > NIRQ) 330 panic("ixp425_intr_establish: IRQ %d out of range", irq); 331 #ifdef DEBUG 332 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 333 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 334 #endif 335 336 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 337 if (ih == NULL) 338 return (NULL); 339 340 ih->ih_func = func; 341 ih->ih_arg = arg; 342 ih->ih_ipl = ipl; 343 ih->ih_irq = irq; 344 345 iq = &intrq[irq]; 346 347 /* All IXP425 interrupts are level-triggered. */ 348 iq->iq_ist = IST_LEVEL; /* XXX */ 349 350 oldirqstate = disable_interrupts(I32_bit); 351 352 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 353 354 ixp425_intr_calculate_masks(); 355 356 restore_interrupts(oldirqstate); 357 358 return (ih); 359 } 360 361 void 362 ixp425_intr_disestablish(void *cookie) 363 { 364 struct intrhand *ih = cookie; 365 struct intrq *iq = &intrq[ih->ih_irq]; 366 int oldirqstate; 367 368 oldirqstate = disable_interrupts(I32_bit); 369 370 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 371 372 ixp425_intr_calculate_masks(); 373 374 restore_interrupts(oldirqstate); 375 } 376 377 void 378 ixp425_intr_dispatch(struct clockframe *frame) 379 { 380 struct intrq *iq; 381 struct intrhand *ih; 382 int oldirqstate, irq, ibit, hwpend; 383 struct cpu_info * const ci = curcpu(); 384 const int ppl = ci->ci_cpl; 385 const uint32_t imask = ixp425_imask[ppl]; 386 387 hwpend = ixp425_irq_read(); 388 389 /* 390 * Disable all the interrupts that are pending. We will 391 * reenable them once they are processed and not masked. 392 */ 393 intr_enabled &= ~hwpend; 394 ixp425_set_intrmask(); 395 396 while (hwpend != 0) { 397 irq = ffs(hwpend) - 1; 398 ibit = (1U << irq); 399 400 hwpend &= ~ibit; 401 402 if (imask & ibit) { 403 /* 404 * IRQ is masked; mark it as pending and check 405 * the next one. Note: the IRQ is already disabled. 406 */ 407 ixp425_ipending |= ibit; 408 continue; 409 } 410 411 ixp425_ipending &= ~ibit; 412 413 iq = &intrq[irq]; 414 iq->iq_ev.ev_count++; 415 uvmexp.intrs++; 416 417 /* Clear down non-level triggered GPIO interrupts now */ 418 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 419 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 420 ixp425_irq2gpio_bit(irq); 421 } 422 423 TAILQ_FOREACH(ih, &iq->iq_list, ih_list) { 424 ci->ci_cpl = ih->ih_ipl; 425 oldirqstate = enable_interrupts(I32_bit); 426 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 427 restore_interrupts(oldirqstate); 428 } 429 430 /* Clear down level triggered GPIO interrupts now */ 431 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 432 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 433 ixp425_irq2gpio_bit(irq); 434 } 435 436 ci->ci_cpl = ppl; 437 438 /* Re-enable this interrupt now that's it's cleared. */ 439 intr_enabled |= ibit; 440 ixp425_set_intrmask(); 441 442 /* 443 * Don't forget to include interrupts which may have 444 * arrived in the meantime. 445 */ 446 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~imask); 447 } 448 449 #ifdef __HAVE_FAST_SOFTINTS 450 cpu_dosoftints(); 451 #endif 452 } 453
Indexes created Wed Oct 22 06:10:02 GMT 2025