ixp425_intr.c revision 1.3
1 /* $NetBSD: ixp425_intr.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 #include <evbarm/ixdp425/ixdp425reg.h> 96 97 /* Interrupt handler queues. */ 98 struct intrq intrq[NIRQ]; 99 100 /* Interrupts to mask at each level. */ 101 int ixp425_imask[NIPL]; 102 103 /* Current interrupt priority level. */ 104 __volatile int current_spl_level; 105 106 /* Interrupts pending. */ 107 __volatile int ixp425_ipending; 108 109 /* Software copy of the IRQs we have enabled. */ 110 __volatile uint32_t intr_enabled; 111 112 /* Mask if interrupts steered to FIQs. */ 113 uint32_t intr_steer; 114 115 /* 116 * Map a software interrupt queue index 117 */ 118 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 119 IXP425_INT_bit31, /* SI_SOFT */ 120 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 121 IXP425_INT_bit29, /* SI_SOFTNET */ 122 IXP425_INT_bit22, /* SI_SOFTSERIAL */ 123 }; 124 125 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 126 127 /* 128 * Map a software interrupt queue to an interrupt priority level. 129 */ 130 static const int si_to_ipl[SI_NQUEUES] = { 131 IPL_SOFT, /* SI_SOFT */ 132 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 133 IPL_SOFTNET, /* SI_SOFTNET */ 134 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 135 }; 136 137 void ixp425_intr_dispatch(struct clockframe *frame); 138 139 static __inline uint32_t 140 ixp425_irq_read(void) 141 { 142 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 143 } 144 145 static __inline void 146 ixp425_set_intrsteer(void) 147 { 148 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 149 } 150 151 static __inline void 152 ixp425_enable_irq(int irq) 153 { 154 155 intr_enabled |= (1U << irq); 156 ixp425_set_intrmask(); 157 } 158 159 static __inline void 160 ixp425_disable_irq(int irq) 161 { 162 163 intr_enabled &= ~(1U << irq); 164 ixp425_set_intrmask(); 165 } 166 167 /* 168 * NOTE: This routine must be called with interrupts disabled in the CPSR. 169 */ 170 static void 171 ixp425_intr_calculate_masks(void) 172 { 173 struct intrq *iq; 174 struct intrhand *ih; 175 int irq, ipl; 176 177 /* First, figure out which IPLs each IRQ has. */ 178 for (irq = 0; irq < NIRQ; irq++) { 179 int levels = 0; 180 iq = &intrq[irq]; 181 ixp425_disable_irq(irq); 182 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 183 ih = TAILQ_NEXT(ih, ih_list)) 184 levels |= (1U << ih->ih_ipl); 185 iq->iq_levels = levels; 186 } 187 188 /* Next, figure out which IRQs are used by each IPL. */ 189 for (ipl = 0; ipl < NIPL; ipl++) { 190 int irqs = 0; 191 for (irq = 0; irq < NIRQ; irq++) { 192 if (intrq[irq].iq_levels & (1U << ipl)) 193 irqs |= (1U << irq); 194 } 195 ixp425_imask[ipl] = irqs; 196 } 197 198 ixp425_imask[IPL_NONE] = 0; 199 200 /* 201 * Initialize the soft interrupt masks to block themselves. 202 */ 203 ixp425_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 204 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 205 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 206 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 207 208 /* 209 * splsoftclock() is the only interface that users of the 210 * generic software interrupt facility have to block their 211 * soft intrs, so splsoftclock() must also block IPL_SOFT. 212 */ 213 ixp425_imask[IPL_SOFTCLOCK] |= ixp425_imask[IPL_SOFT]; 214 215 /* 216 * splsoftnet() must also block splsoftclock(), since we don't 217 * want timer-driven network events to occur while we're 218 * processing incoming packets. 219 */ 220 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTCLOCK]; 221 222 /* 223 * Enforce a heirarchy that gives "slow" device (or devices with 224 * limited input buffer space/"real-time" requirements) a better 225 * chance at not dropping data. 226 */ 227 ixp425_imask[IPL_BIO] |= ixp425_imask[IPL_SOFTNET]; 228 ixp425_imask[IPL_NET] |= ixp425_imask[IPL_BIO]; 229 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_NET]; 230 ixp425_imask[IPL_TTY] |= ixp425_imask[IPL_SOFTSERIAL]; 231 232 /* 233 * splvm() blocks all interrupts that use the kernel memory 234 * allocation facilities. 235 */ 236 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_TTY]; 237 238 /* 239 * Audio devices are not allowed to perform memory allocation 240 * in their interrupt routines, and they have fairly "real-time" 241 * requirements, so give them a high interrupt priority. 242 */ 243 ixp425_imask[IPL_AUDIO] |= ixp425_imask[IPL_VM]; 244 245 /* 246 * splclock() must block anything that uses the scheduler. 247 */ 248 ixp425_imask[IPL_CLOCK] |= ixp425_imask[IPL_AUDIO]; 249 250 /* 251 * No separate statclock on the IQ80310. 252 */ 253 ixp425_imask[IPL_STATCLOCK] |= ixp425_imask[IPL_CLOCK]; 254 255 /* 256 * splhigh() must block "everything". 257 */ 258 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_STATCLOCK]; 259 260 /* 261 * XXX We need serial drivers to run at the absolute highest priority 262 * in order to avoid overruns, so serial > high. 263 */ 264 ixp425_imask[IPL_SERIAL] |= ixp425_imask[IPL_HIGH]; 265 266 /* 267 * Now compute which IRQs must be blocked when servicing any 268 * given IRQ. 269 */ 270 for (irq = 0; irq < NIRQ; irq++) { 271 int irqs = (1U << irq); 272 iq = &intrq[irq]; 273 if (TAILQ_FIRST(&iq->iq_list) != NULL) 274 ixp425_enable_irq(irq); 275 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 276 ih = TAILQ_NEXT(ih, ih_list)) 277 irqs |= ixp425_imask[ih->ih_ipl]; 278 iq->iq_mask = irqs; 279 } 280 } 281 282 __inline void 283 ixp425_do_pending(void) 284 { 285 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 286 int new, oldirqstate; 287 288 if (__cpu_simple_lock_try(&processing) == 0) 289 return; 290 291 new = current_spl_level; 292 293 oldirqstate = disable_interrupts(I32_bit); 294 295 #define DO_SOFTINT(si) \ 296 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 297 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 298 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 299 restore_interrupts(oldirqstate); \ 300 softintr_dispatch(si); \ 301 oldirqstate = disable_interrupts(I32_bit); \ 302 current_spl_level = new; \ 303 } 304 305 DO_SOFTINT(SI_SOFTSERIAL); 306 DO_SOFTINT(SI_SOFTNET); 307 DO_SOFTINT(SI_SOFTCLOCK); 308 DO_SOFTINT(SI_SOFT); 309 310 __cpu_simple_unlock(&processing); 311 312 restore_interrupts(oldirqstate); 313 } 314 315 void 316 splx(int new) 317 { 318 319 ixp425_splx(new); 320 } 321 322 int 323 _spllower(int ipl) 324 { 325 326 return (ixp425_spllower(ipl)); 327 } 328 329 int 330 _splraise(int ipl) 331 { 332 333 return (ixp425_splraise(ipl)); 334 } 335 336 void 337 _setsoftintr(int si) 338 { 339 int oldirqstate; 340 341 oldirqstate = disable_interrupts(I32_bit); 342 ixp425_ipending |= SI_TO_IRQBIT(si); 343 restore_interrupts(oldirqstate); 344 345 /* Process unmasked pending soft interrupts. */ 346 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 347 ixp425_do_pending(); 348 } 349 350 /* 351 * ixp425_icu_init: 352 * 353 * Called early in bootstrap to make clear interrupt register 354 */ 355 void 356 ixp425_icu_init(void) 357 { 358 359 intr_enabled = 0; /* All interrupts disabled */ 360 ixp425_set_intrmask(); 361 362 intr_steer = 0; /* All interrupts steered to IRQ */ 363 ixp425_set_intrsteer(); 364 } 365 366 /* 367 * ixp425_intr_init: 368 * 369 * Initialize the rest of the interrupt subsystem, making it 370 * ready to handle interrupts from devices. 371 */ 372 void 373 ixp425_intr_init(void) 374 { 375 struct intrq *iq; 376 int i; 377 378 intr_enabled = 0; 379 380 for (i = 0; i < NIRQ; i++) { 381 iq = &intrq[i]; 382 TAILQ_INIT(&iq->iq_list); 383 384 sprintf(iq->iq_name, "irq %d", i); 385 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 386 NULL, "ixp425", iq->iq_name); 387 } 388 389 ixp425_intr_calculate_masks(); 390 391 /* Enable IRQs (don't yet use FIQs). */ 392 enable_interrupts(I32_bit); 393 } 394 395 void * 396 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 397 { 398 struct intrq *iq; 399 struct intrhand *ih; 400 u_int oldirqstate; 401 402 if (irq < 0 || irq > NIRQ) 403 panic("ixp425_intr_establish: IRQ %d out of range", irq); 404 #ifdef DEBUG 405 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 406 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 407 #endif 408 409 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 410 if (ih == NULL) 411 return (NULL); 412 413 ih->ih_func = func; 414 ih->ih_arg = arg; 415 ih->ih_ipl = ipl; 416 ih->ih_irq = irq; 417 418 iq = &intrq[irq]; 419 420 /* All IXP425 interrupts are level-triggered. */ 421 iq->iq_ist = IST_LEVEL; /* XXX */ 422 423 oldirqstate = disable_interrupts(I32_bit); 424 425 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 426 427 ixp425_intr_calculate_masks(); 428 429 restore_interrupts(oldirqstate); 430 431 return (ih); 432 } 433 434 void 435 ixp425_intr_disestablish(void *cookie) 436 { 437 struct intrhand *ih = cookie; 438 struct intrq *iq = &intrq[ih->ih_irq]; 439 int oldirqstate; 440 441 oldirqstate = disable_interrupts(I32_bit); 442 443 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 444 445 ixp425_intr_calculate_masks(); 446 447 restore_interrupts(oldirqstate); 448 } 449 450 void 451 ixp425_intr_dispatch(struct clockframe *frame) 452 { 453 struct intrq *iq; 454 struct intrhand *ih; 455 int oldirqstate, pcpl, irq, ibit, hwpend; 456 457 pcpl = current_spl_level; 458 459 hwpend = ixp425_irq_read(); 460 461 /* 462 * Disable all the interrupts that are pending. We will 463 * reenable them once they are processed and not masked. 464 */ 465 466 /* Clear GPIO interrupts pending for PCI(A..D) */ 467 if (hwpend & (1U << PCI_INT_A)) { 468 #ifdef DEBUG 469 printf("ixp425_intr_dispatch: PCI_INT_A\n"); 470 #endif 471 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 472 (1U << GPIO_PCI_INTA); 473 } 474 if (hwpend & (1U << PCI_INT_B)) { 475 #ifdef DEBUG 476 printf("ixp425_intr_dispatch: PCI_INT_B\n"); 477 #endif 478 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 479 (1U << GPIO_PCI_INTB); 480 } 481 if (hwpend & (1U << PCI_INT_C)) { 482 #ifdef DEBUG 483 printf("ixp425_intr_dispatch: PCI_INT_C\n"); 484 #endif 485 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 486 (1U << GPIO_PCI_INTC); 487 } 488 if (hwpend & (1U << PCI_INT_D)) { 489 #ifdef DEBUG 490 printf("ixp425_intr_dispatch: PCI_INT_D\n"); 491 #endif 492 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 493 (1U << GPIO_PCI_INTD); 494 } 495 496 intr_enabled &= ~hwpend; 497 ixp425_set_intrmask(); 498 499 while (hwpend != 0) { 500 irq = ffs(hwpend) - 1; 501 ibit = (1U << irq); 502 503 hwpend &= ~ibit; 504 505 if (pcpl & ibit) { 506 /* 507 * IRQ is masked; mark it as pending and check 508 * the next one. Note: the IRQ is already disabled. 509 */ 510 ixp425_ipending |= ibit; 511 continue; 512 } 513 514 ixp425_ipending &= ~ibit; 515 516 iq = &intrq[irq]; 517 iq->iq_ev.ev_count++; 518 uvmexp.intrs++; 519 current_spl_level |= iq->iq_mask; 520 oldirqstate = enable_interrupts(I32_bit); 521 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 522 ih = TAILQ_NEXT(ih, ih_list)) { 523 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 524 } 525 restore_interrupts(oldirqstate); 526 527 current_spl_level = pcpl; 528 529 /* Re-enable this interrupt now that's it's cleared. */ 530 intr_enabled |= ibit; 531 ixp425_set_intrmask(); 532 } 533 534 /* Check for pendings soft intrs. */ 535 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 536 oldirqstate = enable_interrupts(I32_bit); 537 ixp425_do_pending(); 538 restore_interrupts(oldirqstate); 539 } 540 } 541
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