ixp425_intr.c revision 1.5
1 /* $NetBSD: ixp425_intr.c,v 1.5 2003/10/08 19:31:17 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.5 2003/10/08 19:31:17 scw Exp $"); 72 73 #ifndef EVBARM_SPL_NOINLINE 74 #define EVBARM_SPL_NOINLINE 75 #endif 76 77 /* 78 * Interrupt support for the Intel IXP425 NetworkProcessor. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 90 #include <arm/cpufunc.h> 91 92 #include <arm/xscale/ixp425reg.h> 93 #include <arm/xscale/ixp425var.h> 94 95 /* Interrupt handler queues. */ 96 struct intrq intrq[NIRQ]; 97 98 /* Interrupts to mask at each level. */ 99 int ixp425_imask[NIPL]; 100 101 /* Current interrupt priority level. */ 102 __volatile int current_spl_level; 103 104 /* Interrupts pending. */ 105 __volatile int ixp425_ipending; 106 107 /* Software copy of the IRQs we have enabled. */ 108 __volatile uint32_t intr_enabled; 109 110 /* Mask if interrupts steered to FIQs. */ 111 uint32_t intr_steer; 112 113 /* 114 * Map a software interrupt queue index 115 */ 116 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 117 IXP425_INT_bit31, /* SI_SOFT */ 118 IXP425_INT_bit30, /* SI_SOFTCLOCK */ 119 IXP425_INT_bit29, /* SI_SOFTNET */ 120 IXP425_INT_bit22, /* SI_SOFTSERIAL */ 121 }; 122 123 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 124 125 /* 126 * Map a software interrupt queue to an interrupt priority level. 127 */ 128 static const int si_to_ipl[SI_NQUEUES] = { 129 IPL_SOFT, /* SI_SOFT */ 130 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 131 IPL_SOFTNET, /* SI_SOFTNET */ 132 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 133 }; 134 135 void ixp425_intr_dispatch(struct clockframe *frame); 136 137 static __inline uint32_t 138 ixp425_irq_read(void) 139 { 140 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 141 } 142 143 static __inline void 144 ixp425_set_intrsteer(void) 145 { 146 IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; 147 } 148 149 static __inline void 150 ixp425_enable_irq(int irq) 151 { 152 153 intr_enabled |= (1U << irq); 154 ixp425_set_intrmask(); 155 } 156 157 static __inline void 158 ixp425_disable_irq(int irq) 159 { 160 161 intr_enabled &= ~(1U << irq); 162 ixp425_set_intrmask(); 163 } 164 165 static __inline u_int32_t 166 ixp425_irq2gpio_bit(int irq) 167 { 168 169 static const u_int8_t int2gpio[32] __attribute__ ((aligned(32))) = { 170 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 171 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 172 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 173 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 174 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 175 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 176 0xff, 0xff /* INT#30 -> INT#31 */ 177 }; 178 179 #ifdef DEBUG 180 if (int2gpio[irq] == 0xff) 181 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq); 182 #endif 183 return (1U << int2gpio[irq]); 184 } 185 186 /* 187 * NOTE: This routine must be called with interrupts disabled in the CPSR. 188 */ 189 static void 190 ixp425_intr_calculate_masks(void) 191 { 192 struct intrq *iq; 193 struct intrhand *ih; 194 int irq, ipl; 195 196 /* First, figure out which IPLs each IRQ has. */ 197 for (irq = 0; irq < NIRQ; irq++) { 198 int levels = 0; 199 iq = &intrq[irq]; 200 ixp425_disable_irq(irq); 201 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 202 ih = TAILQ_NEXT(ih, ih_list)) 203 levels |= (1U << ih->ih_ipl); 204 iq->iq_levels = levels; 205 } 206 207 /* Next, figure out which IRQs are used by each IPL. */ 208 for (ipl = 0; ipl < NIPL; ipl++) { 209 int irqs = 0; 210 for (irq = 0; irq < NIRQ; irq++) { 211 if (intrq[irq].iq_levels & (1U << ipl)) 212 irqs |= (1U << irq); 213 } 214 ixp425_imask[ipl] = irqs; 215 } 216 217 ixp425_imask[IPL_NONE] = 0; 218 219 /* 220 * Initialize the soft interrupt masks to block themselves. 221 */ 222 ixp425_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 223 ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 224 ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 225 ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 226 227 /* 228 * splsoftclock() is the only interface that users of the 229 * generic software interrupt facility have to block their 230 * soft intrs, so splsoftclock() must also block IPL_SOFT. 231 */ 232 ixp425_imask[IPL_SOFTCLOCK] |= ixp425_imask[IPL_SOFT]; 233 234 /* 235 * splsoftnet() must also block splsoftclock(), since we don't 236 * want timer-driven network events to occur while we're 237 * processing incoming packets. 238 */ 239 ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTCLOCK]; 240 241 /* 242 * Enforce a heirarchy that gives "slow" device (or devices with 243 * limited input buffer space/"real-time" requirements) a better 244 * chance at not dropping data. 245 */ 246 ixp425_imask[IPL_BIO] |= ixp425_imask[IPL_SOFTNET]; 247 ixp425_imask[IPL_NET] |= ixp425_imask[IPL_BIO]; 248 ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_NET]; 249 ixp425_imask[IPL_TTY] |= ixp425_imask[IPL_SOFTSERIAL]; 250 251 /* 252 * splvm() blocks all interrupts that use the kernel memory 253 * allocation facilities. 254 */ 255 ixp425_imask[IPL_VM] |= ixp425_imask[IPL_TTY]; 256 257 /* 258 * Audio devices are not allowed to perform memory allocation 259 * in their interrupt routines, and they have fairly "real-time" 260 * requirements, so give them a high interrupt priority. 261 */ 262 ixp425_imask[IPL_AUDIO] |= ixp425_imask[IPL_VM]; 263 264 /* 265 * splclock() must block anything that uses the scheduler. 266 */ 267 ixp425_imask[IPL_CLOCK] |= ixp425_imask[IPL_AUDIO]; 268 269 /* 270 * No separate statclock on the IQ80310. 271 */ 272 ixp425_imask[IPL_STATCLOCK] |= ixp425_imask[IPL_CLOCK]; 273 274 /* 275 * splhigh() must block "everything". 276 */ 277 ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_STATCLOCK]; 278 279 /* 280 * XXX We need serial drivers to run at the absolute highest priority 281 * in order to avoid overruns, so serial > high. 282 */ 283 ixp425_imask[IPL_SERIAL] |= ixp425_imask[IPL_HIGH]; 284 285 /* 286 * Now compute which IRQs must be blocked when servicing any 287 * given IRQ. 288 */ 289 for (irq = 0; irq < NIRQ; irq++) { 290 int irqs = (1U << irq); 291 iq = &intrq[irq]; 292 if (TAILQ_FIRST(&iq->iq_list) != NULL) 293 ixp425_enable_irq(irq); 294 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 295 ih = TAILQ_NEXT(ih, ih_list)) 296 irqs |= ixp425_imask[ih->ih_ipl]; 297 iq->iq_mask = irqs; 298 } 299 } 300 301 __inline void 302 ixp425_do_pending(void) 303 { 304 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 305 int new, oldirqstate; 306 307 if (__cpu_simple_lock_try(&processing) == 0) 308 return; 309 310 new = current_spl_level; 311 312 oldirqstate = disable_interrupts(I32_bit); 313 314 #define DO_SOFTINT(si) \ 315 if ((ixp425_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 316 ixp425_ipending &= ~SI_TO_IRQBIT(si); \ 317 current_spl_level |= ixp425_imask[si_to_ipl[(si)]]; \ 318 restore_interrupts(oldirqstate); \ 319 softintr_dispatch(si); \ 320 oldirqstate = disable_interrupts(I32_bit); \ 321 current_spl_level = new; \ 322 } 323 324 DO_SOFTINT(SI_SOFTSERIAL); 325 DO_SOFTINT(SI_SOFTNET); 326 DO_SOFTINT(SI_SOFTCLOCK); 327 DO_SOFTINT(SI_SOFT); 328 329 __cpu_simple_unlock(&processing); 330 331 restore_interrupts(oldirqstate); 332 } 333 334 void 335 splx(int new) 336 { 337 338 ixp425_splx(new); 339 } 340 341 int 342 _spllower(int ipl) 343 { 344 345 return (ixp425_spllower(ipl)); 346 } 347 348 int 349 _splraise(int ipl) 350 { 351 352 return (ixp425_splraise(ipl)); 353 } 354 355 void 356 _setsoftintr(int si) 357 { 358 int oldirqstate; 359 360 oldirqstate = disable_interrupts(I32_bit); 361 ixp425_ipending |= SI_TO_IRQBIT(si); 362 restore_interrupts(oldirqstate); 363 364 /* Process unmasked pending soft interrupts. */ 365 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) 366 ixp425_do_pending(); 367 } 368 369 /* 370 * ixp425_icu_init: 371 * 372 * Called early in bootstrap to make clear interrupt register 373 */ 374 void 375 ixp425_icu_init(void) 376 { 377 378 intr_enabled = 0; /* All interrupts disabled */ 379 ixp425_set_intrmask(); 380 381 intr_steer = 0; /* All interrupts steered to IRQ */ 382 ixp425_set_intrsteer(); 383 } 384 385 /* 386 * ixp425_intr_init: 387 * 388 * Initialize the rest of the interrupt subsystem, making it 389 * ready to handle interrupts from devices. 390 */ 391 void 392 ixp425_intr_init(void) 393 { 394 struct intrq *iq; 395 int i; 396 397 intr_enabled = 0; 398 399 for (i = 0; i < NIRQ; i++) { 400 iq = &intrq[i]; 401 TAILQ_INIT(&iq->iq_list); 402 403 sprintf(iq->iq_name, "irq %d", i); 404 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 405 NULL, "ixp425", iq->iq_name); 406 } 407 408 ixp425_intr_calculate_masks(); 409 410 /* Enable IRQs (don't yet use FIQs). */ 411 enable_interrupts(I32_bit); 412 } 413 414 void * 415 ixp425_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 416 { 417 struct intrq *iq; 418 struct intrhand *ih; 419 u_int oldirqstate; 420 421 if (irq < 0 || irq > NIRQ) 422 panic("ixp425_intr_establish: IRQ %d out of range", irq); 423 #ifdef DEBUG 424 printf("ixp425_intr_establish(irq=%d, ipl=%d, func=%08x, arg=%08x)\n", 425 irq, ipl, (u_int32_t) func, (u_int32_t) arg); 426 #endif 427 428 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 429 if (ih == NULL) 430 return (NULL); 431 432 ih->ih_func = func; 433 ih->ih_arg = arg; 434 ih->ih_ipl = ipl; 435 ih->ih_irq = irq; 436 437 iq = &intrq[irq]; 438 439 /* All IXP425 interrupts are level-triggered. */ 440 iq->iq_ist = IST_LEVEL; /* XXX */ 441 442 oldirqstate = disable_interrupts(I32_bit); 443 444 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 445 446 ixp425_intr_calculate_masks(); 447 448 restore_interrupts(oldirqstate); 449 450 return (ih); 451 } 452 453 void 454 ixp425_intr_disestablish(void *cookie) 455 { 456 struct intrhand *ih = cookie; 457 struct intrq *iq = &intrq[ih->ih_irq]; 458 int oldirqstate; 459 460 oldirqstate = disable_interrupts(I32_bit); 461 462 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 463 464 ixp425_intr_calculate_masks(); 465 466 restore_interrupts(oldirqstate); 467 } 468 469 void 470 ixp425_intr_dispatch(struct clockframe *frame) 471 { 472 struct intrq *iq; 473 struct intrhand *ih; 474 int oldirqstate, pcpl, irq, ibit, hwpend, handled; 475 476 pcpl = current_spl_level; 477 478 hwpend = ixp425_irq_read(); 479 480 /* 481 * Disable all the interrupts that are pending. We will 482 * reenable them once they are processed and not masked. 483 */ 484 intr_enabled &= ~hwpend; 485 ixp425_set_intrmask(); 486 487 while (hwpend != 0) { 488 irq = ffs(hwpend) - 1; 489 ibit = (1U << irq); 490 491 hwpend &= ~ibit; 492 493 if (pcpl & ibit) { 494 /* 495 * IRQ is masked; mark it as pending and check 496 * the next one. Note: the IRQ is already disabled. 497 */ 498 ixp425_ipending |= ibit; 499 continue; 500 } 501 502 ixp425_ipending &= ~ibit; 503 504 iq = &intrq[irq]; 505 iq->iq_ev.ev_count++; 506 uvmexp.intrs++; 507 current_spl_level |= iq->iq_mask; 508 509 /* Clear down non-level triggered GPIO interrupts now */ 510 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist != IST_LEVEL) { 511 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 512 ixp425_irq2gpio_bit(irq); 513 } 514 515 oldirqstate = enable_interrupts(I32_bit); 516 for (handled = 0, ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 517 ih = TAILQ_NEXT(ih, ih_list)) { 518 handled |= 519 (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 520 } 521 restore_interrupts(oldirqstate); 522 523 /* Clear down level triggered GPIO interrupts now */ 524 if ((ibit & IXP425_INT_GPIOMASK) && iq->iq_ist == IST_LEVEL) { 525 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 526 ixp425_irq2gpio_bit(irq); 527 } 528 529 if (handled == 0 && iq->iq_ist == IST_LEVEL) { 530 /* 531 * Let's see if the interrupt really did clear down. 532 * We sometimes see spurious (GPIO) interrupts from 533 * some PCIbus cards on certain boards. 534 */ 535 if ((ibit & IXP425_INT_GPIOMASK) == 0 || 536 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) & 537 ixp425_irq2gpio_bit(irq)) { 538 /* 539 * Nope, still asserted. We're toast. 540 */ 541 panic("ixp425_intr_dispatch: unhandled " 542 "level-triggered interrupt: irq %d", irq); 543 } 544 } 545 546 current_spl_level = pcpl; 547 548 /* Re-enable this interrupt now that's it's cleared. */ 549 intr_enabled |= ibit; 550 ixp425_set_intrmask(); 551 } 552 553 /* Check for pendings soft intrs. */ 554 if ((ixp425_ipending & INT_SWMASK) & ~current_spl_level) { 555 oldirqstate = enable_interrupts(I32_bit); 556 ixp425_do_pending(); 557 restore_interrupts(oldirqstate); 558 } 559 } 560
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