ixp425_npe.c revision 1.11.34.1
1 /* $NetBSD: ixp425_npe.c,v 1.11.34.1 2021/03/20 19:33:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 /*- 33 * Copyright (c) 2001-2005, Intel Corporation. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the Intel Corporation nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 #include <sys/cdefs.h> 62 #if 0 63 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/ixp425_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 64 #endif 65 __KERNEL_RCSID(0, "$NetBSD: ixp425_npe.c,v 1.11.34.1 2021/03/20 19:33:32 thorpej Exp $"); 66 67 /* 68 * Intel XScale Network Processing Engine (NPE) support. 69 * 70 * Each NPE has an ixpnpeX device associated with it that is 71 * attached at boot. Depending on the microcode loaded into 72 * an NPE there may be an Ethernet interface (npeX) or some 73 * other network interface (e.g. for ATM). This file has support 74 * for loading microcode images and the associated NPE CPU 75 * manipulations (start, stop, reset). 76 * 77 * The code here basically replaces the npeDl and npeMh classes 78 * in the Intel Access Library (IAL). 79 * 80 * NB: Microcode images are loaded with firmware(9). To 81 * include microcode in a static kernel include the 82 * ixpnpe_fw device. Otherwise the firmware will be 83 * automatically loaded from the filesystem. 84 */ 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/time.h> 91 #include <sys/proc.h> 92 93 #include <dev/firmload.h> 94 95 #include <sys/bus.h> 96 #include <machine/cpu.h> 97 #include <machine/intr.h> 98 99 #include <arm/xscale/ixp425reg.h> 100 #include <arm/xscale/ixp425var.h> 101 #include <arm/xscale/ixp425_ixmevar.h> 102 103 #include <arm/xscale/ixp425_npereg.h> 104 #include <arm/xscale/ixp425_npevar.h> 105 #include <arm/xscale/ixp425_if_npereg.h> 106 107 #include "locators.h" 108 109 /* 110 * IXP425_NPE_MICROCODE will be defined by ixp425-fw.mk IFF the 111 * microcode object file exists in sys/arch/arm/xscale. 112 * 113 * To permit building the NPE drivers without microcode (so they 114 * don't bitrot due to lack of use), we use "empty" microcode so 115 * that the NPE drivers will simply fail to start at runtime. 116 */ 117 #ifdef IXP425_NPE_MICROCODE 118 extern char _binary_IxNpeMicrocode_dat_start[]; 119 #else 120 static char _binary_IxNpeMicrocode_dat_start[] = { 121 0xfe, 0xed, 0xf0, 0x0d, 0xfe, 0xed, 0xf0, 0x0d 122 }; 123 #endif 124 125 #define IX_NPEDL_NPEIMAGE_FIELD_MASK 0xff 126 127 /* used to read download map from version in microcode image */ 128 #define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000 129 #define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001 130 #define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002 131 #define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F 132 133 /* 134 * masks used to extract address info from State information context 135 * register addresses as read from microcode image 136 */ 137 #define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F 138 #define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 139 140 /* LSB offset of Context Number field in State-Info Context Address */ 141 #define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4 142 143 /* size (in words) of single State Information entry (ctxt reg address|data) */ 144 #define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2 145 146 typedef struct { 147 uint32_t type; 148 uint32_t offset; 149 } IxNpeDlNpeMgrDownloadMapBlockEntry; 150 151 typedef union { 152 IxNpeDlNpeMgrDownloadMapBlockEntry block; 153 uint32_t eodmMarker; 154 } IxNpeDlNpeMgrDownloadMapEntry; 155 156 typedef struct { 157 /* 1st entry in the download map (there may be more than one) */ 158 IxNpeDlNpeMgrDownloadMapEntry entry[1]; 159 } IxNpeDlNpeMgrDownloadMap; 160 161 /* used to access an instruction or data block in a microcode image */ 162 typedef struct { 163 uint32_t npeMemAddress; 164 uint32_t size; 165 uint32_t data[1]; 166 } IxNpeDlNpeMgrCodeBlock; 167 168 /* used to access each Context Reg entry state-information block */ 169 typedef struct { 170 uint32_t addressInfo; 171 uint32_t value; 172 } IxNpeDlNpeMgrStateInfoCtxtRegEntry; 173 174 /* used to access a state-information block in a microcode image */ 175 typedef struct { 176 uint32_t size; 177 IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; 178 } IxNpeDlNpeMgrStateInfoBlock; 179 180 static int npe_debug = 0; 181 #define DPRINTF(dev, fmt, ...) do { \ 182 if (npe_debug) printf(fmt, __VA_ARGS__); \ 183 } while (0) 184 #define DPRINTFn(n, dev, fmt, ...) do { \ 185 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 186 } while (0) 187 188 static int npe_checkbits(struct ixpnpe_softc *, uint32_t reg, uint32_t); 189 static int npe_isstopped(struct ixpnpe_softc *); 190 static int npe_load_ins(struct ixpnpe_softc *, 191 const IxNpeDlNpeMgrCodeBlock *bp, int verify); 192 static int npe_load_data(struct ixpnpe_softc *, 193 const IxNpeDlNpeMgrCodeBlock *bp, int verify); 194 static int npe_load_stateinfo(struct ixpnpe_softc *, 195 const IxNpeDlNpeMgrStateInfoBlock *bp, int verify); 196 static int npe_load_image(struct ixpnpe_softc *, 197 const uint32_t *imageCodePtr, int verify); 198 static int npe_cpu_reset(struct ixpnpe_softc *); 199 static int npe_cpu_start(struct ixpnpe_softc *); 200 static int npe_cpu_stop(struct ixpnpe_softc *); 201 static void npe_cmd_issue_write(struct ixpnpe_softc *, 202 uint32_t cmd, uint32_t addr, uint32_t data); 203 static uint32_t npe_cmd_issue_read(struct ixpnpe_softc *, 204 uint32_t cmd, uint32_t addr); 205 static int npe_ins_write(struct ixpnpe_softc *, 206 uint32_t addr, uint32_t data, int verify); 207 static int npe_data_write(struct ixpnpe_softc *, 208 uint32_t addr, uint32_t data, int verify); 209 static void npe_ecs_reg_write(struct ixpnpe_softc *, 210 uint32_t reg, uint32_t data); 211 static uint32_t npe_ecs_reg_read(struct ixpnpe_softc *, uint32_t reg); 212 static void npe_issue_cmd(struct ixpnpe_softc *, uint32_t command); 213 static void npe_cpu_step_save(struct ixpnpe_softc *); 214 static int npe_cpu_step(struct ixpnpe_softc *, uint32_t npeInstruction, 215 uint32_t ctxtNum, uint32_t ldur); 216 static void npe_cpu_step_restore(struct ixpnpe_softc *); 217 static int npe_logical_reg_read(struct ixpnpe_softc *, 218 uint32_t regAddr, uint32_t regSize, 219 uint32_t ctxtNum, uint32_t *regVal); 220 static int npe_logical_reg_write(struct ixpnpe_softc *, 221 uint32_t regAddr, uint32_t regVal, 222 uint32_t regSize, uint32_t ctxtNum, int verify); 223 static int npe_physical_reg_write(struct ixpnpe_softc *, 224 uint32_t regAddr, uint32_t regValue, int verify); 225 static int npe_ctx_reg_write(struct ixpnpe_softc *, uint32_t ctxtNum, 226 uint32_t ctxtReg, uint32_t ctxtRegVal, int verify); 227 228 static int ixpnpe_intr(void *arg); 229 230 static uint32_t 231 npe_reg_read(struct ixpnpe_softc *sc, bus_size_t off) 232 { 233 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 234 DPRINTFn(9, sc->sc_dev, "%s(0x%lx) => 0x%x\n", __func__, off, v); 235 return v; 236 } 237 238 static void 239 npe_reg_write(struct ixpnpe_softc *sc, bus_size_t off, uint32_t val) 240 { 241 DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val); 242 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 243 } 244 245 static int ixpnpe_match(device_t, cfdata_t, void *); 246 static void ixpnpe_attach(device_t, device_t, void *); 247 static int ixpnpe_print(void *, const char *); 248 static int ixpnpe_search(device_t, cfdata_t, const int *, void *); 249 250 CFATTACH_DECL_NEW(ixpnpe, sizeof(struct ixpnpe_softc), 251 ixpnpe_match, ixpnpe_attach, NULL, NULL); 252 253 static int 254 ixpnpe_match(device_t parent, cfdata_t match, void *arg) 255 { 256 struct ixme_attach_args *ixa = arg; 257 258 return (ixa->ixa_npe == 1 || ixa->ixa_npe == 2); 259 } 260 261 static void 262 ixpnpe_attach(device_t parent, device_t self, void *arg) 263 { 264 struct ixpnpe_softc *sc = device_private(self); 265 struct ixme_attach_args *ixa = arg; 266 bus_addr_t base; 267 int irq; 268 269 aprint_naive("\n"); 270 aprint_normal("\n"); 271 272 sc->sc_dev = self; 273 sc->sc_iot = ixa->ixa_iot; 274 sc->sc_dt = ixa->ixa_dt; 275 sc->sc_unit = ixa->ixa_npe; 276 277 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 278 279 /* XXX: Check features to ensure this NPE is enabled */ 280 281 switch (ixa->ixa_npe) { 282 default: 283 panic("%s: Invalid NPE!", device_xname(self)); 284 285 case 1: 286 base = IXP425_NPE_B_HWBASE; 287 sc->sc_size = IXP425_NPE_B_SIZE; 288 irq = IXP425_INT_NPE_B; 289 290 /* size of instruction memory */ 291 sc->insMemSize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEB; 292 /* size of data memory */ 293 sc->dataMemSize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB; 294 break; 295 296 case 2: 297 base = IXP425_NPE_C_HWBASE; 298 sc->sc_size = IXP425_NPE_C_SIZE; 299 irq = IXP425_INT_NPE_C; 300 301 /* size of instruction memory */ 302 sc->insMemSize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEC; 303 /* size of data memory */ 304 sc->dataMemSize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC; 305 break; 306 } 307 if (bus_space_map(sc->sc_iot, base, sc->sc_size, 0, &sc->sc_ioh)) 308 panic("%s: Cannot map registers", device_xname(self)); 309 310 /* 311 * Setup IRQ and handler for NPE message support. 312 */ 313 sc->sc_ih = ixp425_intr_establish(irq, IPL_NET, ixpnpe_intr, sc); 314 if (sc->sc_ih == NULL) 315 panic("%s: Unable to establish irq %u", device_xname(self), irq); 316 /* enable output fifo interrupts (NB: must also set OFIFO Write Enable) */ 317 npe_reg_write(sc, IX_NPECTL, 318 npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE)); 319 320 config_search(self, ixa, 321 CFARG_SUBMATCH, ixpnpe_search, 322 CFARG_IATTR, "ixpnpe", 323 CFARG_EOL); 324 } 325 326 static int 327 ixpnpe_print(void *arg, const char *name) 328 { 329 330 return (UNCONF); 331 } 332 333 static int 334 ixpnpe_search(device_t parent, cfdata_t cf, const int *ldesc, void *arg) 335 { 336 struct ixpnpe_softc *sc = device_private(parent); 337 struct ixme_attach_args *ixa = arg; 338 struct ixpnpe_attach_args na; 339 340 na.na_unit = ixa->ixa_npe; 341 na.na_phy = cf->cf_loc[IXPNPECF_PHY]; 342 na.na_npe = sc; 343 na.na_iot = ixa->ixa_iot; 344 na.na_dt = ixa->ixa_dt; 345 346 if (config_match(parent, cf, &na) > 0) { 347 config_attach(parent, cf, &na, ixpnpe_print); 348 return (1); 349 } 350 351 return (0); 352 } 353 354 int 355 ixpnpe_stopandreset(struct ixpnpe_softc *sc) 356 { 357 int error; 358 359 mutex_enter(&sc->sc_lock); 360 error = npe_cpu_stop(sc); /* stop NPE */ 361 if (error == 0) 362 error = npe_cpu_reset(sc); /* reset it */ 363 if (error == 0) 364 sc->started = 0; /* mark stopped */ 365 mutex_exit(&sc->sc_lock); 366 367 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); 368 return error; 369 } 370 371 static int 372 ixpnpe_start_locked(struct ixpnpe_softc *sc) 373 { 374 int error; 375 376 if (!sc->started) { 377 error = npe_cpu_start(sc); 378 if (error == 0) 379 sc->started = 1; 380 } else 381 error = 0; 382 383 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); 384 return error; 385 } 386 387 int 388 ixpnpe_start(struct ixpnpe_softc *sc) 389 { 390 int ret; 391 392 mutex_enter(&sc->sc_lock); 393 ret = ixpnpe_start_locked(sc); 394 mutex_exit(&sc->sc_lock); 395 return (ret); 396 } 397 398 int 399 ixpnpe_stop(struct ixpnpe_softc *sc) 400 { 401 int error; 402 403 mutex_enter(&sc->sc_lock); 404 error = npe_cpu_stop(sc); 405 if (error == 0) 406 sc->started = 0; 407 mutex_exit(&sc->sc_lock); 408 409 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); 410 return error; 411 } 412 413 /* 414 * Indicates the start of an NPE Image, in new NPE Image Library format. 415 * 2 consecutive occurances indicates the end of the NPE Image Library 416 */ 417 #define NPE_IMAGE_MARKER 0xfeedf00d 418 419 /* 420 * NPE Image Header definition, used in new NPE Image Library format 421 */ 422 typedef struct { 423 uint32_t marker; 424 uint32_t id; 425 uint32_t size; 426 } IxNpeDlImageMgrImageHeader; 427 428 static int 429 npe_findimage(struct ixpnpe_softc *sc, 430 const uint32_t *imageLibrary, uint32_t imageId, 431 const uint32_t **imagePtr, uint32_t *imageSize) 432 { 433 const IxNpeDlImageMgrImageHeader *image; 434 uint32_t offset = 0; 435 436 while (imageLibrary[offset] == NPE_IMAGE_MARKER) { 437 image = (const IxNpeDlImageMgrImageHeader *)&imageLibrary[offset]; 438 offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(uint32_t); 439 440 DPRINTF(sc->sc_dev, "%s: off %u mark 0x%x id 0x%x size %u\n", 441 __func__, offset, image->marker, image->id, image->size); 442 if (image->id == imageId) { 443 *imagePtr = imageLibrary + offset; 444 *imageSize = image->size; 445 return 0; 446 } 447 /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ 448 if (image->id == NPE_IMAGE_MARKER) { 449 printf("%s: imageId 0x%08x not found in image library header\n", 450 device_xname(sc->sc_dev), imageId); 451 /* reached end of library, image not found */ 452 return EIO; 453 } 454 offset += image->size; 455 } 456 return EIO; 457 } 458 459 int 460 ixpnpe_init(struct ixpnpe_softc *sc, const char *imageName, uint32_t imageId) 461 { 462 uint32_t imageSize; 463 const uint32_t *imageCodePtr; 464 void *fw; 465 int error; 466 467 DPRINTF(sc->sc_dev, "load %s, imageId 0x%08x\n", imageName, imageId); 468 469 #if 0 470 IxFeatureCtrlDeviceId devid = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId); 471 /* 472 * Checking if image being loaded is meant for device that is running. 473 * Image is forward compatible. i.e Image built for IXP42X should run 474 * on IXP46X but not vice versa. 475 */ 476 if (devid > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK)) 477 return EINVAL; 478 #endif 479 error = ixpnpe_stopandreset(sc); /* stop and reset the NPE */ 480 if (error != 0) 481 return error; 482 483 fw = (void *)_binary_IxNpeMicrocode_dat_start; 484 485 /* Locate desired image in files w/ combined images */ 486 error = npe_findimage(sc, (void *)fw /*fw->data*/, imageId, &imageCodePtr, &imageSize); 487 if (error != 0) 488 goto done; 489 490 /* 491 * If download was successful, store image Id in list of 492 * currently loaded images. If a critical error occured 493 * during download, record that the NPE has an invalid image 494 */ 495 mutex_enter(&sc->sc_lock); 496 error = npe_load_image(sc, imageCodePtr, 1 /*VERIFY*/); 497 if (error == 0) { 498 sc->validImage = 1; 499 error = ixpnpe_start_locked(sc); 500 } else { 501 sc->validImage = 0; 502 } 503 sc->functionalityId = IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId); 504 mutex_exit(&sc->sc_lock); 505 done: 506 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); 507 return error; 508 } 509 510 int 511 ixpnpe_getfunctionality(struct ixpnpe_softc *sc) 512 { 513 return (sc->validImage ? sc->functionalityId : 0); 514 } 515 516 static int 517 npe_checkbits(struct ixpnpe_softc *sc, uint32_t reg, uint32_t expectedBitsSet) 518 { 519 uint32_t val; 520 521 val = npe_reg_read(sc, reg); 522 DPRINTFn(5, sc->sc_dev, "%s(0x%x, 0x%x) => 0x%x (%u)\n", 523 __func__, reg, expectedBitsSet, val, 524 (val & expectedBitsSet) == expectedBitsSet); 525 return ((val & expectedBitsSet) == expectedBitsSet); 526 } 527 528 static int 529 npe_isstopped(struct ixpnpe_softc *sc) 530 { 531 return npe_checkbits(sc, 532 IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP); 533 } 534 535 static int 536 npe_load_ins(struct ixpnpe_softc *sc, 537 const IxNpeDlNpeMgrCodeBlock *bp, int verify) 538 { 539 uint32_t npeMemAddress; 540 int i, blockSize; 541 542 npeMemAddress = bp->npeMemAddress; 543 blockSize = bp->size; /* NB: instruction/data count */ 544 if (npeMemAddress + blockSize > sc->insMemSize) { 545 printf("%s: Block size too big for NPE memory\n", device_xname(sc->sc_dev)); 546 return EINVAL; /* XXX */ 547 } 548 for (i = 0; i < blockSize; i++, npeMemAddress++) { 549 if (npe_ins_write(sc, npeMemAddress, bp->data[i], verify) != 0) { 550 printf("%s: NPE instruction write failed", device_xname(sc->sc_dev)); 551 return EIO; 552 } 553 } 554 return 0; 555 } 556 557 static int 558 npe_load_data(struct ixpnpe_softc *sc, 559 const IxNpeDlNpeMgrCodeBlock *bp, int verify) 560 { 561 uint32_t npeMemAddress; 562 int i, blockSize; 563 564 npeMemAddress = bp->npeMemAddress; 565 blockSize = bp->size; /* NB: instruction/data count */ 566 if (npeMemAddress + blockSize > sc->dataMemSize) { 567 printf("%s: Block size too big for NPE memory\n", device_xname(sc->sc_dev)); 568 return EINVAL; 569 } 570 for (i = 0; i < blockSize; i++, npeMemAddress++) { 571 if (npe_data_write(sc, npeMemAddress, bp->data[i], verify) != 0) { 572 printf("%s: NPE data write failed\n", device_xname(sc->sc_dev)); 573 return EIO; 574 } 575 } 576 return 0; 577 } 578 579 static int 580 npe_load_stateinfo(struct ixpnpe_softc *sc, 581 const IxNpeDlNpeMgrStateInfoBlock *bp, int verify) 582 { 583 int i, nentries, error; 584 585 npe_cpu_step_save(sc); 586 587 /* for each state-info context register entry in block */ 588 nentries = bp->size / IX_NPEDL_STATE_INFO_ENTRY_SIZE; 589 error = 0; 590 for (i = 0; i < nentries; i++) { 591 /* each state-info entry is 2 words (address, value) in length */ 592 uint32_t regVal = bp->ctxtRegEntry[i].value; 593 uint32_t addrInfo = bp->ctxtRegEntry[i].addressInfo; 594 595 uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG); 596 uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> 597 IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM; 598 599 /* error-check Context Register No. and Context Number values */ 600 if (reg >= IX_NPEDL_CTXT_REG_MAX) { 601 printf("%s: invalid Context Register %u\n", device_xname(sc->sc_dev), 602 reg); 603 error = EINVAL; 604 break; 605 } 606 if (cNum >= IX_NPEDL_CTXT_NUM_MAX) { 607 printf("%s: invalid Context Number %u\n", device_xname(sc->sc_dev), 608 cNum); 609 error = EINVAL; 610 break; 611 } 612 /* NOTE that there is no STEVT register for Context 0 */ 613 if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) { 614 printf("%s: no STEVT for Context 0\n", device_xname(sc->sc_dev)); 615 error = EINVAL; 616 break; 617 } 618 619 if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) { 620 printf("%s: write of state-info to NPE failed\n", 621 device_xname(sc->sc_dev)); 622 error = EIO; 623 break; 624 } 625 } 626 627 npe_cpu_step_restore(sc); 628 return error; 629 } 630 631 static int 632 npe_load_image(struct ixpnpe_softc *sc, 633 const uint32_t *imageCodePtr, int verify) 634 { 635 #define EOM(marker) ((marker) == IX_NPEDL_END_OF_DOWNLOAD_MAP) 636 const IxNpeDlNpeMgrDownloadMap *downloadMap; 637 int i, error; 638 639 if (!npe_isstopped(sc)) { /* verify NPE is stopped */ 640 printf("%s: cannot load image, NPE not stopped\n", device_xname(sc->sc_dev)); 641 return EIO; 642 } 643 644 /* 645 * Read Download Map, checking each block type and calling 646 * appropriate function to perform download 647 */ 648 error = 0; 649 downloadMap = (const IxNpeDlNpeMgrDownloadMap *) imageCodePtr; 650 for (i = 0; !EOM(downloadMap->entry[i].eodmMarker); i++) { 651 /* calculate pointer to block to be downloaded */ 652 const uint32_t *bp = imageCodePtr + downloadMap->entry[i].block.offset; 653 switch (downloadMap->entry[i].block.type) { 654 case IX_NPEDL_BLOCK_TYPE_INSTRUCTION: 655 error = npe_load_ins(sc, 656 (const IxNpeDlNpeMgrCodeBlock *) bp, verify); 657 DPRINTF(sc->sc_dev, "%s: inst, error %d\n", __func__, error); 658 break; 659 case IX_NPEDL_BLOCK_TYPE_DATA: 660 error = npe_load_data(sc, 661 (const IxNpeDlNpeMgrCodeBlock *) bp, verify); 662 DPRINTF(sc->sc_dev, "%s: data, error %d\n", __func__, error); 663 break; 664 case IX_NPEDL_BLOCK_TYPE_STATE: 665 error = npe_load_stateinfo(sc, 666 (const IxNpeDlNpeMgrStateInfoBlock *) bp, verify); 667 DPRINTF(sc->sc_dev, "%s: state, error %d\n", __func__, error); 668 break; 669 default: 670 printf("%s: unknown block type 0x%x in download map\n", 671 device_xname(sc->sc_dev), downloadMap->entry[i].block.type); 672 error = EIO; /* XXX */ 673 break; 674 } 675 if (error != 0) 676 break; 677 } 678 return error; 679 #undef EOM 680 } 681 682 /* contains Reset values for Context Store Registers */ 683 static const struct { 684 uint32_t regAddr; 685 uint32_t regResetVal; 686 } ixNpeDlEcsRegResetValues[] = { 687 { IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET }, 688 { IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET }, 689 { IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET }, 690 { IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET }, 691 { IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET }, 692 { IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET }, 693 { IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET }, 694 { IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET }, 695 { IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET }, 696 { IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET }, 697 { IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET }, 698 { IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET }, 699 { IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET } 700 }; 701 702 /* contains Reset values for Context Store Registers */ 703 static const uint32_t ixNpeDlCtxtRegResetValues[] = { 704 IX_NPEDL_CTXT_REG_RESET_STEVT, 705 IX_NPEDL_CTXT_REG_RESET_STARTPC, 706 IX_NPEDL_CTXT_REG_RESET_REGMAP, 707 IX_NPEDL_CTXT_REG_RESET_CINDEX, 708 }; 709 710 #define IX_NPEDL_RESET_NPE_PARITY 0x0800 711 #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF 712 #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF 713 714 static int 715 npe_cpu_reset(struct ixpnpe_softc *sc) 716 { 717 #define N(a) (sizeof(a) / sizeof(a[0])) 718 uint32_t ctxtReg; /* identifies Context Store reg (0-3) */ 719 uint32_t regAddr; 720 uint32_t regVal; 721 uint32_t resetNpeParity; 722 uint32_t ixNpeConfigCtrlRegVal; 723 int i, error = 0; 724 725 /* pre-store the NPE Config Control Register Value */ 726 ixNpeConfigCtrlRegVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL); 727 ixNpeConfigCtrlRegVal |= 0x3F000000; 728 729 /* disable the parity interrupt */ 730 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL, 731 (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK)); 732 DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n", 733 __func__, ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK); 734 735 npe_cpu_step_save(sc); 736 737 /* 738 * Clear the FIFOs. 739 */ 740 while (npe_checkbits(sc, 741 IX_NPEDL_REG_OFFSET_WFIFO, IX_NPEDL_MASK_WFIFO_VALID)) { 742 /* read from the Watch-point FIFO until empty */ 743 (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WFIFO); 744 } 745 746 while (npe_checkbits(sc, 747 IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_OFNE)) { 748 /* read from the outFIFO until empty */ 749 (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_FIFO); 750 } 751 752 while (npe_checkbits(sc, 753 IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) { 754 /* 755 * Step execution of the NPE intruction to read inFIFO using 756 * the Debug Executing Context stack. 757 */ 758 error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0); 759 if (error != 0) { 760 DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n", 761 __func__, error); 762 npe_cpu_step_restore(sc); 763 return error; 764 } 765 } 766 767 /* 768 * Reset the mailbox reg 769 */ 770 /* ...from XScale side */ 771 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_MBST, IX_NPEDL_REG_RESET_MBST); 772 /* ...from NPE side */ 773 error = npe_cpu_step(sc, IX_NPEDL_INSTR_RESET_MBOX, 0, 0); 774 if (error != 0) { 775 DPRINTF(sc->sc_dev, "%s: cannot step (2), error %u\n", __func__, error); 776 npe_cpu_step_restore(sc); 777 return error; 778 } 779 780 /* 781 * Reset the physical registers in the NPE register file: 782 * Note: no need to save/restore REGMAP for Context 0 here 783 * since all Context Store regs are reset in subsequent code. 784 */ 785 for (regAddr = 0; 786 regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG && error == 0; 787 regAddr++) { 788 /* for each physical register in the NPE reg file, write 0 : */ 789 error = npe_physical_reg_write(sc, regAddr, 0, true); 790 if (error != 0) { 791 DPRINTF(sc->sc_dev, "%s: cannot write phy reg, error %u\n", 792 __func__, error); 793 npe_cpu_step_restore(sc); 794 return error; /* abort reset */ 795 } 796 } 797 798 /* 799 * Reset the context store: 800 */ 801 for (i = IX_NPEDL_CTXT_NUM_MIN; i <= IX_NPEDL_CTXT_NUM_MAX; i++) { 802 /* set each context's Context Store registers to reset values: */ 803 for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) { 804 /* NOTE that there is no STEVT register for Context 0 */ 805 if (!(i == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STEVT)) { 806 regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; 807 error = npe_ctx_reg_write(sc, i, ctxtReg, regVal, true); 808 if (error != 0) { 809 DPRINTF(sc->sc_dev, "%s: cannot write ctx reg, error %u\n", 810 __func__, error); 811 npe_cpu_step_restore(sc); 812 return error; /* abort reset */ 813 } 814 } 815 } 816 } 817 818 npe_cpu_step_restore(sc); 819 820 /* write Reset values to Execution Context Stack registers */ 821 for (i = 0; i < N(ixNpeDlEcsRegResetValues); i++) 822 npe_ecs_reg_write(sc, 823 ixNpeDlEcsRegResetValues[i].regAddr, 824 ixNpeDlEcsRegResetValues[i].regResetVal); 825 826 /* clear the profile counter */ 827 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT); 828 829 /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ 830 for (regAddr = IX_NPEDL_REG_OFFSET_EXCT; 831 regAddr <= IX_NPEDL_REG_OFFSET_AP3; 832 regAddr += sizeof(uint32_t)) 833 npe_reg_write(sc, regAddr, 0); 834 835 /* Reset the Watch-count register */ 836 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_WC, 0); 837 838 /* 839 * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation 840 */ 841 842 /* 843 * Reset the NPE and its coprocessor - to reset internal 844 * states and remove parity error. Note this makes no 845 * sense based on the documentation. The feature control 846 * register always reads back as 0 on the ixp425 and further 847 * the bit definition of NPEA/NPEB is off by 1 according to 848 * the Intel documention--so we're blindly following the 849 * Intel code w/o any real understanding. 850 */ 851 regVal = EXP_BUS_READ_4(ixp425_softc, EXP_FCTRL_OFFSET); 852 DPRINTFn(2, sc->sc_dev, "%s: FCTRL 0x%x\n", __func__, regVal); 853 resetNpeParity = 854 IX_NPEDL_RESET_NPE_PARITY << (1 + sc->sc_unit); 855 DPRINTFn(2, sc->sc_dev, "%s: FCTRL fuse parity, write 0x%x\n", 856 __func__, regVal | resetNpeParity); 857 EXP_BUS_WRITE_4(ixp425_softc, EXP_FCTRL_OFFSET, regVal | resetNpeParity); 858 859 /* un-fuse and un-reset the NPE & coprocessor */ 860 DPRINTFn(2, sc->sc_dev, "%s: FCTRL unfuse parity, write 0x%x\n", 861 __func__, regVal & ~resetNpeParity); 862 EXP_BUS_WRITE_4(ixp425_softc, EXP_FCTRL_OFFSET, regVal &~ resetNpeParity); 863 864 /* 865 * Call NpeMgr function to stop the NPE again after the Feature Control 866 * has unfused and Un-Reset the NPE and its associated Coprocessors. 867 */ 868 error = npe_cpu_stop(sc); 869 870 /* restore NPE configuration bus Control Register - Parity Settings */ 871 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL, 872 (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK)); 873 DPRINTFn(2, sc->sc_dev, "%s: restore CTL => 0x%x\n", 874 __func__, npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL)); 875 876 return error; 877 #undef N 878 } 879 880 static int 881 npe_cpu_start(struct ixpnpe_softc *sc) 882 { 883 uint32_t ecsRegVal; 884 885 /* 886 * Ensure only Background Context Stack Level is Active by turning off 887 * the Active bit in each of the other Executing Context Stack levels. 888 */ 889 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0); 890 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; 891 npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, ecsRegVal); 892 893 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0); 894 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; 895 npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, ecsRegVal); 896 897 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0); 898 ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; 899 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsRegVal); 900 901 /* clear the pipeline */ 902 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); 903 904 /* start NPE execution by issuing command through EXCTL register on NPE */ 905 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_START); 906 907 /* 908 * Check execution status of NPE to verify operation was successful. 909 */ 910 return npe_checkbits(sc, 911 IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_RUN) ? 0 : EIO; 912 } 913 914 static int 915 npe_cpu_stop(struct ixpnpe_softc *sc) 916 { 917 /* stop NPE execution by issuing command through EXCTL register on NPE */ 918 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STOP); 919 920 /* verify that NPE Stop was successful */ 921 return npe_checkbits(sc, 922 IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP) ? 0 : EIO; 923 } 924 925 #define IX_NPEDL_REG_SIZE_BYTE 8 926 #define IX_NPEDL_REG_SIZE_SHORT 16 927 #define IX_NPEDL_REG_SIZE_WORD 32 928 929 /* 930 * Introduce extra read cycles after issuing read command to NPE 931 * so that we read the register after the NPE has updated it 932 * This is to overcome race condition between XScale and NPE 933 */ 934 #define IX_NPEDL_DELAY_READ_CYCLES 2 935 /* 936 * To mask top three MSBs of 32bit word to download into NPE IMEM 937 */ 938 #define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF; 939 940 static void 941 npe_cmd_issue_write(struct ixpnpe_softc *sc, 942 uint32_t cmd, uint32_t addr, uint32_t data) 943 { 944 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, data); 945 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr); 946 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd); 947 } 948 949 static uint32_t 950 npe_cmd_issue_read(struct ixpnpe_softc *sc, uint32_t cmd, uint32_t addr) 951 { 952 uint32_t data; 953 int i; 954 955 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr); 956 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd); 957 for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++) 958 data = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA); 959 return data; 960 } 961 962 static int 963 npe_ins_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify) 964 { 965 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data); 966 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_INS_MEM, addr, data); 967 if (verify) { 968 uint32_t rdata; 969 970 /* 971 * Write invalid data to this reg, so we can see if we're reading 972 * the EXDATA register too early. 973 */ 974 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data); 975 976 /* Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/ 977 data &= IX_NPEDL_MASK_UNUSED_IMEM_BITS; 978 979 rdata = npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_INS_MEM, addr); 980 rdata &= IX_NPEDL_MASK_UNUSED_IMEM_BITS; 981 982 if (data != rdata) 983 return EIO; 984 } 985 return 0; 986 } 987 988 static int 989 npe_data_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify) 990 { 991 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data); 992 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, addr, data); 993 if (verify) { 994 /* 995 * Write invalid data to this reg, so we can see if we're reading 996 * the EXDATA register too early. 997 */ 998 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data); 999 if (data != npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, addr)) 1000 return EIO; 1001 } 1002 return 0; 1003 } 1004 1005 static void 1006 npe_ecs_reg_write(struct ixpnpe_softc *sc, uint32_t reg, uint32_t data) 1007 { 1008 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_ECS_REG, reg, data); 1009 } 1010 1011 static uint32_t 1012 npe_ecs_reg_read(struct ixpnpe_softc *sc, uint32_t reg) 1013 { 1014 return npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_ECS_REG, reg); 1015 } 1016 1017 static void 1018 npe_issue_cmd(struct ixpnpe_softc *sc, uint32_t command) 1019 { 1020 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, command); 1021 } 1022 1023 static void 1024 npe_cpu_step_save(struct ixpnpe_softc *sc) 1025 { 1026 /* turn off the halt bit by clearing Execution Count register. */ 1027 /* save reg contents 1st and restore later */ 1028 sc->savedExecCount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXCT); 1029 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, 0); 1030 1031 /* ensure that IF and IE are on (temporarily), so that we don't end up 1032 * stepping forever */ 1033 sc->savedEcsDbgCtxtReg2 = npe_ecs_reg_read(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2); 1034 1035 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2, 1036 (sc->savedEcsDbgCtxtReg2 | IX_NPEDL_MASK_ECS_DBG_REG_2_IF | 1037 IX_NPEDL_MASK_ECS_DBG_REG_2_IE)); 1038 } 1039 1040 static int 1041 npe_cpu_step(struct ixpnpe_softc *sc, uint32_t npeInstruction, 1042 uint32_t ctxtNum, uint32_t ldur) 1043 { 1044 #define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 1045 uint32_t ecsDbgRegVal; 1046 uint32_t oldWatchcount, newWatchcount; 1047 int tries; 1048 1049 /* set the Active bit, and the LDUR, in the debug level */ 1050 ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE | 1051 (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR); 1052 1053 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsDbgRegVal); 1054 1055 /* 1056 * Set CCTXT at ECS DEBUG L3 to specify in which context to execute the 1057 * instruction, and set SELCTXT at ECS DEBUG Level to specify which context 1058 * store to access. 1059 * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number 1060 */ 1061 ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) | 1062 (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT); 1063 1064 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_1, ecsDbgRegVal); 1065 1066 /* clear the pipeline */ 1067 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); 1068 1069 /* load NPE instruction into the instruction register */ 1070 npe_ecs_reg_write(sc, IX_NPEDL_ECS_INSTRUCT_REG, npeInstruction); 1071 1072 /* we need this value later to wait for completion of NPE execution step */ 1073 oldWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); 1074 1075 /* issue a Step One command via the Execution Control register */ 1076 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STEP); 1077 1078 /* 1079 * Force the XScale to wait until the NPE has finished execution step 1080 * NOTE that this delay will be very small, just long enough to allow a 1081 * single NPE instruction to complete execution; if instruction execution 1082 * is not completed before timeout retries, exit the while loop. 1083 */ 1084 newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); 1085 for (tries = 0; tries < IX_NPE_DL_MAX_NUM_OF_RETRIES && 1086 newWatchcount == oldWatchcount; tries++) { 1087 /* Watch Count register increments when NPE completes an instruction */ 1088 newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); 1089 } 1090 return (tries < IX_NPE_DL_MAX_NUM_OF_RETRIES) ? 0 : EIO; 1091 #undef IX_NPE_DL_MAX_NUM_OF_RETRIES 1092 } 1093 1094 static void 1095 npe_cpu_step_restore(struct ixpnpe_softc *sc) 1096 { 1097 /* clear active bit in debug level */ 1098 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, 0); 1099 1100 /* clear the pipeline */ 1101 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); 1102 1103 /* restore Execution Count register contents. */ 1104 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, sc->savedExecCount); 1105 1106 /* restore IF and IE bits to original values */ 1107 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2, sc->savedEcsDbgCtxtReg2); 1108 } 1109 1110 static int 1111 npe_logical_reg_read(struct ixpnpe_softc *sc, 1112 uint32_t regAddr, uint32_t regSize, 1113 uint32_t ctxtNum, uint32_t *regVal) 1114 { 1115 uint32_t npeInstruction, mask; 1116 int error; 1117 1118 switch (regSize) { 1119 case IX_NPEDL_REG_SIZE_BYTE: 1120 npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE; 1121 mask = 0xff; 1122 break; 1123 case IX_NPEDL_REG_SIZE_SHORT: 1124 npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT; 1125 mask = 0xffff; 1126 break; 1127 case IX_NPEDL_REG_SIZE_WORD: 1128 npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD; 1129 mask = 0xffffffff; 1130 break; 1131 default: 1132 return EINVAL; 1133 } 1134 1135 /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ 1136 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | 1137 (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); 1138 1139 /* step execution of NPE intruction using Debug Executing Context stack */ 1140 error = npe_cpu_step(sc, npeInstruction, ctxtNum, IX_NPEDL_RD_INSTR_LDUR); 1141 if (error != 0) { 1142 DPRINTF(sc->sc_dev, "%s(0x%x, %u, %u), cannot step, error %d\n", 1143 __func__, regAddr, regSize, ctxtNum, error); 1144 return error; 1145 } 1146 /* read value of register from Execution Data register */ 1147 *regVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA); 1148 1149 /* align value from left to right */ 1150 *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; 1151 1152 return 0; 1153 } 1154 1155 static int 1156 npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal, 1157 uint32_t regSize, uint32_t ctxtNum, int verify) 1158 { 1159 int error; 1160 1161 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x, %u, %u)\n", 1162 __func__, regAddr, regVal, regSize, ctxtNum); 1163 if (regSize == IX_NPEDL_REG_SIZE_WORD) { 1164 /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ 1165 /* Write upper half-word (short) to |d0|d1| */ 1166 error = npe_logical_reg_write(sc, regAddr, 1167 regVal >> IX_NPEDL_REG_SIZE_SHORT, 1168 IX_NPEDL_REG_SIZE_SHORT, ctxtNum, verify); 1169 if (error != 0) 1170 return error; 1171 1172 /* Write lower half-word (short) to |d2|d3| */ 1173 error = npe_logical_reg_write(sc, 1174 regAddr + sizeof(uint16_t), 1175 regVal & 0xffff, 1176 IX_NPEDL_REG_SIZE_SHORT, ctxtNum, verify); 1177 } else { 1178 uint32_t npeInstruction; 1179 1180 switch (regSize) { 1181 case IX_NPEDL_REG_SIZE_BYTE: 1182 npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; 1183 regVal &= 0xff; 1184 break; 1185 case IX_NPEDL_REG_SIZE_SHORT: 1186 npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; 1187 regVal &= 0xffff; 1188 break; 1189 default: 1190 return EINVAL; 1191 } 1192 /* fill dest operand field of instruction with destination reg addr */ 1193 npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); 1194 1195 /* fill src operand field of instruction with least-sig 5 bits of val*/ 1196 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << 1197 IX_NPEDL_OFFSET_INSTR_SRC); 1198 1199 /* fill coprocessor field of instruction with most-sig 11 bits of val*/ 1200 npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << 1201 IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); 1202 1203 /* step execution of NPE intruction using Debug ECS */ 1204 error = npe_cpu_step(sc, npeInstruction, 1205 ctxtNum, IX_NPEDL_WR_INSTR_LDUR); 1206 } 1207 if (error != 0) { 1208 DPRINTF(sc->sc_dev, "%s(0x%x, 0x%x, %u, %u), error %u writing reg\n", 1209 __func__, regAddr, regVal, regSize, ctxtNum, error); 1210 return error; 1211 } 1212 if (verify) { 1213 uint32_t retRegVal; 1214 1215 error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum, &retRegVal); 1216 if (error == 0 && regVal != retRegVal) 1217 error = EIO; /* XXX ambiguous */ 1218 } 1219 return error; 1220 } 1221 1222 /* 1223 * There are 32 physical registers used in an NPE. These are 1224 * treated as 16 pairs of 32-bit registers. To write one of the pair, 1225 * write the pair number (0-16) to the REGMAP for Context 0. Then write 1226 * the value to register 0 or 4 in the regfile, depending on which 1227 * register of the pair is to be written 1228 */ 1229 static int 1230 npe_physical_reg_write(struct ixpnpe_softc *sc, 1231 uint32_t regAddr, uint32_t regValue, int verify) 1232 { 1233 int error; 1234 1235 /* 1236 * Set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) 1237 * of physical registers to write . 1238 */ 1239 error = npe_logical_reg_write(sc, IX_NPEDL_CTXT_REG_ADDR_REGMAP, 1240 (regAddr >> IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP), 1241 IX_NPEDL_REG_SIZE_SHORT, 0, verify); 1242 if (error == 0) { 1243 /* regAddr = 0 or 4 */ 1244 regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * 1245 sizeof(uint32_t); 1246 error = npe_logical_reg_write(sc, regAddr, regValue, 1247 IX_NPEDL_REG_SIZE_WORD, 0, verify); 1248 } 1249 return error; 1250 } 1251 1252 static int 1253 npe_ctx_reg_write(struct ixpnpe_softc *sc, uint32_t ctxtNum, 1254 uint32_t ctxtReg, uint32_t ctxtRegVal, int verify) 1255 { 1256 DPRINTFn(4, sc->sc_dev, "%s(%u, %u, %u)\n", 1257 __func__, ctxtNum, ctxtReg, ctxtRegVal); 1258 /* 1259 * Context 0 has no STARTPC. Instead, this value is used to set 1260 * NextPC for Background ECS, to set where NPE starts executing code 1261 */ 1262 if (ctxtNum == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STARTPC) { 1263 /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ 1264 uint32_t v = npe_ecs_reg_read(sc, IX_NPEDL_ECS_BG_CTXT_REG_0); 1265 v &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC; 1266 v |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) & 1267 IX_NPEDL_MASK_ECS_REG_0_NEXTPC; 1268 1269 npe_ecs_reg_write(sc, IX_NPEDL_ECS_BG_CTXT_REG_0, v); 1270 return 0; 1271 } else { 1272 static const struct { 1273 uint32_t regAddress; 1274 uint32_t regSize; 1275 } regAccInfo[IX_NPEDL_CTXT_REG_MAX] = { 1276 { IX_NPEDL_CTXT_REG_ADDR_STEVT, IX_NPEDL_REG_SIZE_BYTE }, 1277 { IX_NPEDL_CTXT_REG_ADDR_STARTPC, IX_NPEDL_REG_SIZE_SHORT }, 1278 { IX_NPEDL_CTXT_REG_ADDR_REGMAP, IX_NPEDL_REG_SIZE_SHORT }, 1279 { IX_NPEDL_CTXT_REG_ADDR_CINDEX, IX_NPEDL_REG_SIZE_BYTE } 1280 }; 1281 return npe_logical_reg_write(sc, regAccInfo[ctxtReg].regAddress, 1282 ctxtRegVal, regAccInfo[ctxtReg].regSize, ctxtNum, verify); 1283 } 1284 } 1285 1286 /* 1287 * NPE Mailbox support. 1288 */ 1289 #define IX_NPEMH_MAXTRIES 100000 1290 1291 static int 1292 ixpnpe_ofifo_wait(struct ixpnpe_softc *sc) 1293 { 1294 int i; 1295 1296 for (i = 0; i < IX_NPEMH_MAXTRIES; i++) { 1297 if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_OFNE) 1298 return 1; 1299 DELAY(10); 1300 } 1301 printf("%s: %s: timeout, last status 0x%x\n", device_xname(sc->sc_dev), 1302 __func__, npe_reg_read(sc, IX_NPESTAT)); 1303 return 0; 1304 } 1305 1306 static int 1307 ixpnpe_intr(void *arg) 1308 { 1309 struct ixpnpe_softc *sc = arg; 1310 uint32_t status; 1311 1312 status = npe_reg_read(sc, IX_NPESTAT); 1313 if ((status & IX_NPESTAT_OFINT) == 0) { 1314 /* NB: should not happen */ 1315 printf("%s: %s: status 0x%x\n", device_xname(sc->sc_dev), __func__, status); 1316 /* XXX must silence interrupt? */ 1317 return(1); 1318 } 1319 /* 1320 * A message is waiting in the output FIFO, copy it so 1321 * the interrupt will be silenced; then signal anyone 1322 * waiting to collect the result. 1323 */ 1324 sc->sc_msgwaiting = -1; /* NB: error indicator */ 1325 if (ixpnpe_ofifo_wait(sc)) { 1326 sc->sc_msg[0] = npe_reg_read(sc, IX_NPEFIFO); 1327 if (ixpnpe_ofifo_wait(sc)) { 1328 sc->sc_msg[1] = npe_reg_read(sc, IX_NPEFIFO); 1329 sc->sc_msgwaiting = 1; /* successful fetch */ 1330 } 1331 } 1332 if (sc->sc_msg[0] == (NPE_MACRECOVERYSTART << NPE_MAC_MSGID_SHL)) { 1333 int s; 1334 1335 s = splnet(); 1336 delay(100); /* delay 100usec */ 1337 if (sc->macresetcbfunc != NULL) 1338 sc->macresetcbfunc(sc->macresetcbarg); 1339 splx(s); 1340 } 1341 1342 #if 0 1343 /* XXX Too dangerous! see ixpnpe_recvmsg_locked() */ 1344 wakeup(sc); 1345 #endif 1346 1347 return (1); 1348 } 1349 1350 static int 1351 ixpnpe_ififo_wait(struct ixpnpe_softc *sc) 1352 { 1353 int i; 1354 1355 for (i = 0; i < IX_NPEMH_MAXTRIES; i++) { 1356 if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_IFNF) 1357 return 1; 1358 DELAY(10); 1359 } 1360 return 0; 1361 } 1362 1363 static int 1364 ixpnpe_sendmsg_locked(struct ixpnpe_softc *sc, const uint32_t msg[2]) 1365 { 1366 int error = 0; 1367 1368 sc->sc_msgwaiting = 0; 1369 if (ixpnpe_ififo_wait(sc)) { 1370 npe_reg_write(sc, IX_NPEFIFO, msg[0]); 1371 if (ixpnpe_ififo_wait(sc)) 1372 npe_reg_write(sc, IX_NPEFIFO, msg[1]); 1373 else 1374 error = EIO; 1375 } else 1376 error = EIO; 1377 1378 if (error) 1379 printf("%s: input FIFO timeout, msg [0x%x,0x%x]\n", 1380 device_xname(sc->sc_dev), msg[0], msg[1]); 1381 return error; 1382 } 1383 1384 static int 1385 ixpnpe_recvmsg_locked(struct ixpnpe_softc *sc, uint32_t msg[2]) 1386 { 1387 1388 if (!sc->sc_msgwaiting) { 1389 /* XXX interrupt context - cannot sleep */ 1390 delay(1000); /* wait 1ms (is it ok?)*/ 1391 } 1392 memcpy(msg, sc->sc_msg, sizeof(sc->sc_msg)); 1393 /* NB: sc_msgwaiting != 1 means the ack fetch failed */ 1394 return sc->sc_msgwaiting != 1 ? EIO : 0; 1395 } 1396 1397 /* 1398 * Send a msg to the NPE and wait for a reply. We use the 1399 * private mutex and sleep until an interrupt is received 1400 * signalling the availability of data in the output FIFO 1401 * so the caller cannot be holding a mutex. May be better 1402 * piggyback on the caller's mutex instead but that would 1403 * make other locking confusing. 1404 */ 1405 int 1406 ixpnpe_sendandrecvmsg(struct ixpnpe_softc *sc, 1407 const uint32_t send[2], uint32_t recv[2]) 1408 { 1409 int error; 1410 1411 mutex_enter(&sc->sc_lock); 1412 error = ixpnpe_sendmsg_locked(sc, send); 1413 if (error == 0) 1414 error = ixpnpe_recvmsg_locked(sc, recv); 1415 mutex_exit(&sc->sc_lock); 1416 1417 return error; 1418 } 1419 1420 /* XXX temporary, not reliable */ 1421 1422 int 1423 ixpnpe_sendmsg(struct ixpnpe_softc *sc, const uint32_t msg[2]) 1424 { 1425 int error; 1426 1427 mutex_enter(&sc->sc_lock); 1428 error = ixpnpe_sendmsg_locked(sc, msg); 1429 mutex_exit(&sc->sc_lock); 1430 1431 return error; 1432 } 1433 1434 int 1435 ixpnpe_recvmsg(struct ixpnpe_softc *sc, uint32_t msg[2]) 1436 { 1437 int error; 1438 1439 mutex_enter(&sc->sc_lock); 1440 if (sc->sc_msgwaiting) 1441 memcpy(msg, sc->sc_msg, sizeof(sc->sc_msg)); 1442 /* NB: sc_msgwaiting != 1 means the ack fetch failed */ 1443 error = sc->sc_msgwaiting != 1 ? EIO : 0; 1444 mutex_exit(&sc->sc_lock); 1445 1446 return error; 1447 } 1448
Indexes created Thu Oct 23 22:10:10 GMT 2025