ixp425_npereg.h revision 1.2
1 /* $NetBSD: ixp425_npereg.h,v 1.2 2021/07/24 21:31:32 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 * 31 * $FreeBSD: src/sys/arm/xscale/ixp425/ixp425_npereg.h,v 1.1 2006/11/19 23:55:23 sam Exp $ 32 */ 33 34 /*- 35 * Copyright (c) 2001-2005, Intel Corporation. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. Neither the name of the Intel Corporation nor the names of its contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 52 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #ifndef _IXP425_NPEREG_H_ 65 #define _IXP425_NPEREG_H_ 66 67 /* signature found as 1st word in a microcode image library */ 68 #define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF 69 /* marks end of header in a microcode image library */ 70 #define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF 71 72 /* 73 * Intel (R) IXP400 Software NPE Image ID Definition 74 * 75 * Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart() 76 * as input of type uint32_t which has the following fields format: 77 * 78 * Field [Bit Location] 79 * ----------------------------------- 80 * Device ID [31 - 28] 81 * NPE ID [27 - 24] 82 * NPE Functionality ID [23 - 16] 83 * Major Release Number [15 - 8] 84 * Minor Release Number [7 - 0] 85 */ 86 #define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \ 87 (((imageId) >> 24) & 0xf) 88 #define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \ 89 (((imageId) >> 28) & 0xf) 90 #define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ 91 (((imageId) >> 16) & 0xff) 92 #define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ 93 (((imageId) >> 8) & 0xff) 94 #define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ 95 (((imageId) >> 0) & 0xff) 96 97 /* 98 * Instruction and Data Memory Size (in words) for each NPE 99 */ 100 #ifndef __ixp46X 101 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 102 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 103 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 104 105 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 106 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 107 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 108 #else 109 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 110 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 4096 111 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 4096 112 113 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 4096 114 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 4096 115 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 4096 116 #endif 117 118 /* BAR offsets */ 119 #define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */ 120 #define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */ 121 #define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */ 122 #define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */ 123 #define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */ 124 #define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */ 125 #define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */ 126 #define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */ 127 #define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */ 128 #define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */ 129 #define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */ 130 #define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */ 131 #define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */ 132 #define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */ 133 #define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */ 134 135 /* 136 * Reset value for Mailbox (MBST) register 137 * NOTE that if used, it should be complemented with an NPE instruction 138 * to clear the Mailbox at the NPE side as well 139 */ 140 #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 141 142 #define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ 143 #define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ 144 #define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ 145 146 /* 147 * EXCTL (Execution Control) Register commands 148 */ 149 #define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ 150 #define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ 151 #define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ 152 #define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ 153 154 /* 155 * Read/write operations use address in EXAD and data in EXDATA. 156 */ 157 #define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */ 158 #define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */ 159 #define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */ 160 #define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */ 161 #define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */ 162 #define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */ 163 164 #define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */ 165 166 167 /* 168 * EXCTL (Execution Control) Register status bit masks 169 */ 170 #define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 171 #define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 172 #define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 173 #define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ 174 175 /* 176 * Executing Context Stack (ECS) level registers 177 */ 178 #define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ 179 #define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ 180 #define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ 181 182 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ 183 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ 184 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ 185 186 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */ 187 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */ 188 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */ 189 190 #define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */ 191 #define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */ 192 #define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */ 193 194 #define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */ 195 196 /* 197 * Execution Access register reset values 198 */ 199 #define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000 200 #define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000 201 #define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000 202 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080 203 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000 204 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000 205 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080 206 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000 207 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000 208 #define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000 209 #define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000 210 #define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000 211 #define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F 212 213 /* 214 * Masks used to read/write particular bits in Execution Access registers 215 */ 216 217 #define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */ 218 #define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */ 219 #define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */ 220 221 #define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */ 222 #define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F 223 224 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ 225 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ 226 227 228 /* 229 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. 230 */ 231 232 #define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 233 #define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 234 235 #define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 236 #define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 237 238 /* 239 * NPE core & co-processor instruction templates to load into NPE Instruction 240 * Register, for read/write of NPE register file registers. 241 */ 242 243 /* 244 * Read an 8-bit NPE internal logical register 245 * and return the value in the EXDATA register (aligned to MSB). 246 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 247 */ 248 #define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000 249 250 /* 251 * Read a 16-bit NPE internal logical register 252 * and return the value in the EXDATA register (aligned to MSB). 253 * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" 254 */ 255 #define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010 256 257 /* 258 * Read a 16-bit NPE internal logical register 259 * and return the value in the EXDATA register. 260 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" 261 */ 262 #define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210 263 264 /* 265 * Write an 8-bit NPE internal logical register. 266 * NPE Assembler instruction: "mov8 d0, #0" 267 */ 268 #define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000 269 270 /* 271 * Write a 16-bit NPE internal logical register. 272 * NPE Assembler instruction: "mov16 d0, #0" 273 */ 274 #define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 275 276 /* 277 * Write a 16-bit NPE internal logical register. 278 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 279 */ 280 #define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 281 282 /* 283 * Reset Mailbox (MBST) register 284 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 285 */ 286 #define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 287 288 289 /* 290 * Bit-offsets from LSB, of particular bit-fields in an NPE instruction 291 */ 292 #define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */ 293 #define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */ 294 #define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */ 295 296 /* 297 * Masks used to read/write particular bits of an NPE Instruction 298 */ 299 300 /** 301 * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 302 * SRC field of immediate-mode NPE instruction 303 */ 304 #define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F 305 306 /** 307 * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 308 * COPROC field of immediate-mode NPE instruction 309 */ 310 #define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 311 312 /** 313 * LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) 314 * to be used in COPROC field of immediate-mode NPE instruction 315 */ 316 #define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5 317 318 /** 319 * Number of left-shifts required to align most-sig 11 bits of 16-bit 320 * data value into COPROC field of immediate-mode NPE instruction 321 */ 322 #define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ 323 (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA) 324 325 /** 326 * LDUR value used with immediate-mode NPE Instructions by the NpeDl 327 * for writing to NPE internal logical registers 328 */ 329 #define IX_NPEDL_WR_INSTR_LDUR 1 330 331 /** 332 * LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl 333 * for reading from NPE internal logical registers 334 */ 335 #define IX_NPEDL_RD_INSTR_LDUR 0 336 337 338 /** 339 * NPE internal Context Store registers. 340 */ 341 typedef enum 342 { 343 IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ 344 IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ 345 IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ 346 IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ 347 IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */ 348 } IxNpeDlCtxtRegNum; 349 350 351 /* 352 * NPE Context Store register logical addresses 353 */ 354 #define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B 355 #define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C 356 #define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E 357 #define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F 358 359 /* 360 * NPE Context Store register reset values 361 */ 362 363 /** 364 * Reset value of STEVT NPE internal Context Store register 365 * (STEVT = off, 0x80) 366 */ 367 #define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80 368 369 /** 370 * Reset value of STARTPC NPE internal Context Store register 371 * (STARTPC = 0x0000) 372 */ 373 #define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000 374 375 /** 376 * Reset value of REGMAP NPE internal Context Store register 377 * (REGMAP = d0->p0, d8->p2, d16->p4) 378 */ 379 #define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820 380 381 /** 382 * Reset value of CINDEX NPE internal Context Store register 383 * (CINDEX = 0) 384 */ 385 #define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00 386 387 388 /* 389 * Numeric range of context levels available on an NPE 390 */ 391 #define IX_NPEDL_CTXT_NUM_MIN 0 392 #define IX_NPEDL_CTXT_NUM_MAX 15 393 394 395 /** 396 * Number of Physical registers currently supported 397 * Initial NPE implementations will have a 32-word register file. 398 * Later implementations may have a 64-word register file. 399 */ 400 #define IX_NPEDL_TOTAL_NUM_PHYS_REG 32 401 402 /** 403 * LSB-offset of Regmap number in Physical NPE register address, used 404 * for Physical To Logical register address mapping in the NPE 405 */ 406 #define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1 407 408 /** 409 * Mask to extract a logical NPE register address from a physical 410 * register address, used for Physical To Logical address mapping 411 */ 412 #define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1 413 414 /* 415 * NPE Message/Mailbox interface. 416 */ 417 #define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */ 418 #define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */ 419 #define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */ 420 421 /* control register */ 422 #define IX_NPECTL_OFE 0x00010000 /* output fifo enable */ 423 #define IX_NPECTL_IFE 0x00020000 /* input fifo enable */ 424 #define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */ 425 #define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */ 426 427 /* status register */ 428 #define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */ 429 #define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */ 430 #define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */ 431 #define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */ 432 #define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */ 433 #define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */ 434 #define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */ 435 #define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */ 436 #endif /* _IXP425_NPEREG_H_ */ 437
Indexes created Thu Oct 02 14:10:14 GMT 2025