ixp425_pci.c revision 1.1
1 /* $NetBSD: ixp425_pci.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <machine/bus.h> 48 49 #include <arm/xscale/ixp425reg.h> 50 #include <arm/xscale/ixp425var.h> 51 52 #include <evbarm/ixdp425/ixdp425reg.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pciconf.h> 57 58 #include "opt_pci.h" 59 #include "pci.h" 60 61 void ixp425_pci_attach_hook(struct device *, struct device *, 62 struct pcibus_attach_args *); 63 int ixp425_pci_bus_maxdevs(void *, int); 64 void ixp425_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 65 void ixp425_pci_conf_setup(void *, struct ixp425_softc *, pcitag_t, int); 66 void ixp425_pci_conf_write(void *, pcitag_t, int, pcireg_t); 67 pcitag_t ixp425_pci_make_tag(void *, int, int, int); 68 pcireg_t ixp425_pci_conf_read(void *, pcitag_t, int); 69 70 #define MAX_PCI_DEVICES 32 71 72 void 73 ixp425_pci_init(pci_chipset_tag_t pc, void *cookie) 74 { 75 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 76 struct ixp425_softc *sc = cookie; 77 struct extent *ioext, *memext; 78 #endif 79 pc->pc_conf_v = cookie; 80 pc->pc_attach_hook = ixp425_pci_attach_hook; 81 pc->pc_bus_maxdevs = ixp425_pci_bus_maxdevs; 82 pc->pc_make_tag = ixp425_pci_make_tag; 83 pc->pc_decompose_tag = ixp425_pci_decompose_tag; 84 pc->pc_conf_read = ixp425_pci_conf_read; 85 pc->pc_conf_write = ixp425_pci_conf_write; 86 87 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 88 ioext = extent_create("pciio", 0, IXP425_PCI_IO_SIZE - 1, 89 M_DEVBUF, NULL, 0, EX_NOWAIT); 90 /* PCI MEM space is mapped same address as real memory */ 91 memext = extent_create("pcimem", IXP425_PCI_MEM_VBASE, 92 IXP425_PCI_MEM_VBASE + 93 IXP425_PCI_MEM_SIZE - 1, 94 M_DEVBUF, NULL, 0, EX_NOWAIT); 95 printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 96 pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */, 97 arm_dcache_align); 98 99 extent_destroy(ioext); 100 extent_destroy(memext); 101 #endif 102 } 103 104 void 105 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 106 { 107 } 108 109 void 110 ixp425_pci_attach_hook(struct device *parent, struct device *self, 111 struct pcibus_attach_args *pba) 112 { 113 /* Nothing to do. */ 114 } 115 116 int 117 ixp425_pci_bus_maxdevs(void *v, int busno) 118 { 119 return(MAX_PCI_DEVICES); 120 } 121 122 pcitag_t 123 ixp425_pci_make_tag(void *v, int bus, int device, int function) 124 { 125 #ifdef PCI_DEBUG 126 printf("ixp425_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 127 v, bus, device, function); 128 #endif 129 return ((bus << 16) | (device << 11) | (function << 8)); 130 } 131 132 void 133 ixp425_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, 134 int *functionp) 135 { 136 #ifdef PCI_DEBUG 137 printf("ixp425_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 138 v, tag, (int)busp, (int)devicep, (int)functionp); 139 #endif 140 if (busp != NULL) 141 *busp = (tag >> 16) & 0xff; 142 if (devicep != NULL) 143 *devicep = (tag >> 11) & 0x1f; 144 if (functionp != NULL) 145 *functionp = (tag >> 8) & 0x7; 146 } 147 148 void 149 ixp425_pci_conf_setup(void *v, struct ixp425_softc *sc, pcitag_t tag, int offset) 150 { 151 int bus, device, function; 152 153 ixp425_pci_decompose_tag(v, tag, &bus, &device, &function); 154 155 if (bus == 0) { 156 if (device == 0 && function == 0) { 157 PCI_CSR_WRITE_4(sc, PCI_NP_AD, (offset & ~3)); 158 } else { 159 /* configuration type 0 */ 160 PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - device)) | 161 (function << 8) | (offset & ~3)); 162 } 163 } else { 164 /* configuration type 1 */ 165 PCI_CSR_WRITE_4(sc, PCI_NP_AD, 166 (bus << 16) | (device << 11) | 167 (function << 8) | (offset & ~3) | 1); 168 } 169 } 170 171 /* read/write PCI Non-Pre-fetch Data */ 172 173 pcireg_t 174 ixp425_pci_conf_read(void *v, pcitag_t tag, int offset) 175 { 176 struct ixp425_softc *sc = v; 177 u_int32_t data; 178 pcireg_t rv; 179 int s; 180 #define PCI_NP_HAVE_BUG 181 #ifdef PCI_NP_HAVE_BUG 182 int i; 183 #endif 184 185 PCI_CONF_LOCK(s); 186 ixp425_pci_conf_setup(v, sc, tag, offset); 187 188 #ifdef PCI_DEBUG 189 printf("ixp425_pci_conf_read: tag=%lx,offset=%x\n", 190 tag, offset); 191 #endif 192 193 #ifdef PCI_NP_HAVE_BUG 194 /* PCI NP Bug workaround */ 195 for (i = 0; i < 8; i++) { 196 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); 197 rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 198 rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 199 } 200 #else 201 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); 202 rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 203 #endif 204 205 /* check&clear PCI abort */ 206 data = PCI_CSR_READ_4(sc, PCI_ISR); 207 if (data & ISR_PFE) { 208 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 209 PCI_CONF_UNLOCK(s); 210 return -1; 211 } else { 212 PCI_CONF_UNLOCK(s); 213 return rv; 214 } 215 } 216 217 void 218 ixp425_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 219 { 220 struct ixp425_softc *sc = v; 221 u_int32_t data; 222 int s; 223 224 PCI_CONF_LOCK(s); 225 226 ixp425_pci_conf_setup(v, sc, tag, offset); 227 #ifdef PCI_DEBUG 228 printf("ixp425_pci_conf_write: tag=%lx offset=%x <- val=%x\n", 229 tag, offset, val); 230 #endif 231 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE); 232 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val); 233 234 /* check&clear PCI abort */ 235 data = PCI_CSR_READ_4(sc, PCI_ISR); 236 if (data & ISR_PFE) 237 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 238 239 PCI_CONF_UNLOCK(s); 240 } 241 242 /* read/write pci configuration data */ 243 244 uint32_t 245 ixp425_pci_conf_reg_read(struct ixp425_softc *sc, uint32_t reg) 246 { 247 uint32_t data; 248 249 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 250 PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_READ)); 251 data = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 252 PCI_CRP_AD_RDATA); 253 254 return data; 255 } 256 257 void 258 ixp425_pci_conf_reg_write(struct ixp425_softc *sc, uint32_t reg, 259 uint32_t data) 260 { 261 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 262 PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); 263 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 264 PCI_CRP_AD_WDATA, data); 265 } 266
Indexes created Mon Oct 20 08:09:54 GMT 2025