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ixp425_pci.c revision 1.12 
      1 /*	$NetBSD: ixp425_pci.c,v 1.12 2015/10/02 05:22:50 msaitoh Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2003
      5  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  * SUCH DAMAGE.
     28  */
     29 
     30 #include <sys/cdefs.h>
     31 __KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.12 2015/10/02 05:22:50 msaitoh Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/device.h>
     36 #include <sys/extent.h>
     37 #include <sys/malloc.h>
     38 
     39 #include <uvm/uvm_extern.h>
     40 
     41 #include <sys/bus.h>
     42 
     43 #include <arm/xscale/ixp425reg.h>
     44 #include <arm/xscale/ixp425var.h>
     45 
     46 #include <evbarm/ixdp425/ixdp425reg.h>
     47 
     48 #include <dev/pci/pcireg.h>
     49 #include <dev/pci/pcivar.h>
     50 #include <dev/pci/pciconf.h>
     51 
     52 #include "opt_pci.h"
     53 #include "pci.h"
     54 
     55 void	ixp425_pci_attach_hook(device_t, device_t,
     56 	    struct pcibus_attach_args *);
     57 int	ixp425_pci_bus_maxdevs(void *, int);
     58 void	ixp425_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
     59 void	ixp425_pci_conf_setup(void *, struct ixp425_softc *, pcitag_t, int);
     60 void	ixp425_pci_conf_write(void *, pcitag_t, int, pcireg_t);
     61 void	ixp425_pci_conf_interrupt(void *, int, int, int, int, int *);
     62 pcitag_t ixp425_pci_make_tag(void *, int, int, int);
     63 pcireg_t ixp425_pci_conf_read(void *, pcitag_t, int);
     64 
     65 #define	MAX_PCI_DEVICES	32
     66 
     67 void
     68 ixp425_pci_init(struct ixp425_softc *sc)
     69 {
     70 	pci_chipset_tag_t pc = &sc->ia_pci_chipset;
     71 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
     72 	struct extent *ioext, *memext;
     73 #endif
     74 	/*
     75 	 * Initialise the PCI chipset tag
     76 	 */
     77 	pc->pc_conf_v = sc;
     78 	pc->pc_attach_hook = ixp425_pci_attach_hook;
     79 	pc->pc_bus_maxdevs = ixp425_pci_bus_maxdevs;
     80 	pc->pc_make_tag = ixp425_pci_make_tag;
     81 	pc->pc_decompose_tag = ixp425_pci_decompose_tag;
     82 	pc->pc_conf_read = ixp425_pci_conf_read;
     83 	pc->pc_conf_write = ixp425_pci_conf_write;
     84 	pc->pc_conf_interrupt = ixp425_pci_conf_interrupt;
     85 
     86 	/*
     87 	 * Initialize the bus space tags.
     88 	 */
     89 	ixp425_io_bs_init(&sc->sc_pci_iot, sc);
     90 	ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
     91 
     92 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
     93 	ioext  = extent_create("pciio", 0, IXP425_PCI_IO_SIZE - 1,
     94 				NULL, 0, EX_NOWAIT);
     95 	/* PCI MEM space is mapped same address as real memory */
     96 	memext = extent_create("pcimem", IXP425_PCI_MEM_HWBASE,
     97 				IXP425_PCI_MEM_HWBASE +
     98 				IXP425_PCI_MEM_SIZE - 1,
     99 				NULL, 0, EX_NOWAIT);
    100 	aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
    101 	pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
    102 			  arm_dcache_align);
    103 
    104 	extent_destroy(ioext);
    105 	extent_destroy(memext);
    106 #endif
    107 }
    108 
    109 void
    110 ixp425_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p)
    111 {
    112 }
    113 
    114 void
    115 ixp425_pci_attach_hook(device_t parent, device_t self,
    116 	struct pcibus_attach_args *pba)
    117 {
    118 	/* Nothing to do. */
    119 }
    120 
    121 int
    122 ixp425_pci_bus_maxdevs(void *v, int busno)
    123 {
    124 	return(MAX_PCI_DEVICES);
    125 }
    126 
    127 pcitag_t
    128 ixp425_pci_make_tag(void *v, int bus, int device, int function)
    129 {
    130 #ifdef PCI_DEBUG
    131 	printf("ixp425_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n",
    132 		v, bus, device, function);
    133 #endif
    134 	return ((bus << 16) | (device << 11) | (function << 8));
    135 }
    136 
    137 void
    138 ixp425_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep,
    139 	int *functionp)
    140 {
    141 #ifdef PCI_DEBUG
    142 	printf("ixp425_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n",
    143 		v, tag, (int)busp, (int)devicep, (int)functionp);
    144 #endif
    145 	if (busp != NULL)
    146 		*busp = (tag >> 16) & 0xff;
    147 	if (devicep != NULL)
    148 		*devicep = (tag >> 11) & 0x1f;
    149 	if (functionp != NULL)
    150 		*functionp = (tag >> 8) & 0x7;
    151 }
    152 
    153 void
    154 ixp425_pci_conf_setup(void *v, struct ixp425_softc *sc, pcitag_t tag, int offset)
    155 {
    156 	int bus, device, function;
    157 
    158 	ixp425_pci_decompose_tag(v, tag, &bus, &device, &function);
    159 
    160 	if (bus == 0) {
    161 		if (device == 0 && function == 0) {
    162 			PCI_CSR_WRITE_4(sc, PCI_NP_AD, (offset & ~3));
    163 		} else {
    164 			/* configuration type 0 */
    165 			PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - device)) |
    166 				(function << 8) | (offset & ~3));
    167 		}
    168 	} else {
    169 			/* configuration type 1 */
    170 		PCI_CSR_WRITE_4(sc, PCI_NP_AD,
    171 			(bus << 16) | (device << 11) |
    172 			(function << 8) | (offset & ~3) | 1);
    173 	}
    174 }
    175 
    176 /* read/write PCI Non-Pre-fetch Data */
    177 
    178 pcireg_t
    179 ixp425_pci_conf_read(void *v, pcitag_t tag, int offset)
    180 {
    181 	struct ixp425_softc *sc = v;
    182 	uint32_t data;
    183 	pcireg_t rv;
    184 	int s;
    185 #define PCI_NP_HAVE_BUG
    186 #ifdef PCI_NP_HAVE_BUG
    187 	int i;
    188 #endif
    189 
    190 	if ((unsigned int)offset >= PCI_CONF_SIZE)
    191 		return (pcireg_t) -1;
    192 
    193 	PCI_CONF_LOCK(s);
    194 	ixp425_pci_conf_setup(v, sc, tag, offset);
    195 
    196 #ifdef PCI_DEBUG
    197 	printf("ixp425_pci_conf_read: tag=%lx,offset=%x\n",
    198 		tag, offset);
    199 #endif
    200 
    201 #ifdef PCI_NP_HAVE_BUG
    202 	/* PCI NP Bug workaround */
    203 	for (i = 0; i < 8; i++) {
    204 		PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
    205 		rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
    206 		rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
    207 	}
    208 #else
    209 	PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
    210 	rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
    211 #endif
    212 
    213 	/* check&clear PCI abort */
    214 	data = PCI_CSR_READ_4(sc, PCI_ISR);
    215 	if (data & ISR_PFE) {
    216 		PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
    217 		PCI_CONF_UNLOCK(s);
    218 		return -1;
    219 	} else {
    220 		PCI_CONF_UNLOCK(s);
    221 		return rv;
    222 	}
    223 }
    224 
    225 void
    226 ixp425_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
    227 {
    228 	struct ixp425_softc *sc = v;
    229 	uint32_t data;
    230 	int s;
    231 
    232 	if ((unsigned int)offset >= PCI_CONF_SIZE)
    233 		return;
    234 
    235 	PCI_CONF_LOCK(s);
    236 
    237 	ixp425_pci_conf_setup(v, sc, tag, offset);
    238 #ifdef PCI_DEBUG
    239 	printf("ixp425_pci_conf_write: tag=%lx offset=%x <- val=%x\n",
    240 		tag, offset, val);
    241 #endif
    242 	PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE);
    243 	PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val);
    244 
    245 	/* check&clear PCI abort */
    246 	data = PCI_CSR_READ_4(sc, PCI_ISR);
    247 	if (data & ISR_PFE)
    248 		PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
    249 
    250 	PCI_CONF_UNLOCK(s);
    251 }
    252 
    253 /* read/write pci configuration data */
    254 
    255 uint32_t
    256 ixp425_pci_conf_reg_read(struct ixp425_softc *sc, uint32_t reg)
    257 {
    258 	uint32_t data;
    259 
    260 	bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
    261 		PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_READ));
    262 	data = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
    263 		PCI_CRP_AD_RDATA);
    264 
    265 	return data;
    266 }
    267 
    268 void
    269 ixp425_pci_conf_reg_write(struct ixp425_softc *sc, uint32_t reg,
    270 	uint32_t data)
    271 {
    272 	bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
    273 		PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
    274 	bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
    275 		PCI_CRP_AD_WDATA, data);
    276 }
    277