ixp425_pci_space.c revision 1.2.4.2
1 1.2.4.2 skrll /* $NetBSD: ixp425_pci_space.c,v 1.2.4.2 2004/08/03 10:32:58 skrll Exp $ */ 2 1.2.4.2 skrll 3 1.2.4.2 skrll /* 4 1.2.4.2 skrll * Copyright (c) 2003 5 1.2.4.2 skrll * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 1.2.4.2 skrll * All rights reserved. 7 1.2.4.2 skrll * 8 1.2.4.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.2.4.2 skrll * modification, are permitted provided that the following conditions 10 1.2.4.2 skrll * are met: 11 1.2.4.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.2.4.2 skrll * notice, this list of conditions and the following disclaimer. 13 1.2.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 14 1.2.4.2 skrll * notice, this list of conditions and the following disclaimer in the 15 1.2.4.2 skrll * documentation and/or other materials provided with the distribution. 16 1.2.4.2 skrll * 3. All advertising materials mentioning features or use of this software 17 1.2.4.2 skrll * must display the following acknowledgement: 18 1.2.4.2 skrll * This product includes software developed by Ichiro FUKUHARA. 19 1.2.4.2 skrll * 4. The name of the company nor the name of the author may be used to 20 1.2.4.2 skrll * endorse or promote products derived from this software without specific 21 1.2.4.2 skrll * prior written permission. 22 1.2.4.2 skrll * 23 1.2.4.2 skrll * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 1.2.4.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 1.2.4.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 1.2.4.2 skrll * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 1.2.4.2 skrll * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 1.2.4.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 1.2.4.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 1.2.4.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 1.2.4.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 1.2.4.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 1.2.4.2 skrll * SUCH DAMAGE. 34 1.2.4.2 skrll */ 35 1.2.4.2 skrll 36 1.2.4.2 skrll #include <sys/cdefs.h> 37 1.2.4.2 skrll __KERNEL_RCSID(0, "$NetBSD: ixp425_pci_space.c,v 1.2.4.2 2004/08/03 10:32:58 skrll Exp $"); 38 1.2.4.2 skrll 39 1.2.4.2 skrll /* 40 1.2.4.2 skrll * bus_space PCI functions for ixp425 41 1.2.4.2 skrll */ 42 1.2.4.2 skrll 43 1.2.4.2 skrll #include <sys/param.h> 44 1.2.4.2 skrll #include <sys/systm.h> 45 1.2.4.2 skrll #include <sys/queue.h> 46 1.2.4.2 skrll 47 1.2.4.2 skrll #include <uvm/uvm.h> 48 1.2.4.2 skrll 49 1.2.4.2 skrll #include <machine/bus.h> 50 1.2.4.2 skrll 51 1.2.4.2 skrll #include <arm/xscale/ixp425reg.h> 52 1.2.4.2 skrll #include <arm/xscale/ixp425var.h> 53 1.2.4.2 skrll 54 1.2.4.2 skrll /* 55 1.2.4.2 skrll * Macros to read/write registers 56 1.2.4.2 skrll */ 57 1.2.4.2 skrll #define CSR_READ_4(x) *(__volatile uint32_t *) \ 58 1.2.4.2 skrll (IXP425_PCI_CSR_BASE + (x)) 59 1.2.4.2 skrll #define CSR_WRITE_4(x, v) *(__volatile uint32_t *) \ 60 1.2.4.2 skrll (IXP425_PCI_CSR_BASE + (x)) = (v) 61 1.2.4.2 skrll 62 1.2.4.2 skrll /* Proto types for all the bus_space structure functions */ 63 1.2.4.2 skrll bs_protos(ixp425_pci); 64 1.2.4.2 skrll bs_protos(ixp425_pci_io); 65 1.2.4.2 skrll bs_protos(ixp425_pci_mem); 66 1.2.4.2 skrll bs_protos(bs_notimpl); 67 1.2.4.2 skrll 68 1.2.4.2 skrll /* special I/O functions */ 69 1.2.4.2 skrll #if 1 /* XXX */ 70 1.2.4.2 skrll inline u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t); 71 1.2.4.2 skrll inline u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t); 72 1.2.4.2 skrll inline u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t); 73 1.2.4.2 skrll 74 1.2.4.2 skrll inline void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); 75 1.2.4.2 skrll inline void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); 76 1.2.4.2 skrll inline void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); 77 1.2.4.2 skrll #endif 78 1.2.4.2 skrll 79 1.2.4.2 skrll struct bus_space ixp425_pci_bs_tag_template = { 80 1.2.4.2 skrll /* cookie */ 81 1.2.4.2 skrll (void *) 0, 82 1.2.4.2 skrll 83 1.2.4.2 skrll /* mapping/unmapping */ 84 1.2.4.2 skrll NULL, 85 1.2.4.2 skrll NULL, 86 1.2.4.2 skrll ixp425_pci_bs_subregion, 87 1.2.4.2 skrll 88 1.2.4.2 skrll /* allocation/deallocation */ 89 1.2.4.2 skrll NULL, 90 1.2.4.2 skrll NULL, 91 1.2.4.2 skrll 92 1.2.4.2 skrll /* get kernel virtual address */ 93 1.2.4.2 skrll NULL, 94 1.2.4.2 skrll 95 1.2.4.2 skrll /* mmap bus space for userland */ 96 1.2.4.2 skrll ixp425_pci_bs_mmap, 97 1.2.4.2 skrll 98 1.2.4.2 skrll /* barrier */ 99 1.2.4.2 skrll ixp425_pci_bs_barrier, 100 1.2.4.2 skrll 101 1.2.4.2 skrll /* read (single) */ 102 1.2.4.2 skrll bs_notimpl_bs_r_1, 103 1.2.4.2 skrll bs_notimpl_bs_r_2, 104 1.2.4.2 skrll bs_notimpl_bs_r_4, 105 1.2.4.2 skrll bs_notimpl_bs_r_8, 106 1.2.4.2 skrll 107 1.2.4.2 skrll /* read multiple */ 108 1.2.4.2 skrll bs_notimpl_bs_rm_1, 109 1.2.4.2 skrll bs_notimpl_bs_rm_2, 110 1.2.4.2 skrll bs_notimpl_bs_rm_4, 111 1.2.4.2 skrll bs_notimpl_bs_rm_8, 112 1.2.4.2 skrll 113 1.2.4.2 skrll /* read region */ 114 1.2.4.2 skrll bs_notimpl_bs_rr_1, 115 1.2.4.2 skrll bs_notimpl_bs_rr_2, 116 1.2.4.2 skrll bs_notimpl_bs_rr_4, 117 1.2.4.2 skrll bs_notimpl_bs_rr_8, 118 1.2.4.2 skrll 119 1.2.4.2 skrll /* write (single) */ 120 1.2.4.2 skrll bs_notimpl_bs_w_1, 121 1.2.4.2 skrll bs_notimpl_bs_w_2, 122 1.2.4.2 skrll bs_notimpl_bs_w_4, 123 1.2.4.2 skrll bs_notimpl_bs_w_8, 124 1.2.4.2 skrll 125 1.2.4.2 skrll /* write multiple */ 126 1.2.4.2 skrll bs_notimpl_bs_wm_1, 127 1.2.4.2 skrll bs_notimpl_bs_wm_2, 128 1.2.4.2 skrll bs_notimpl_bs_wm_4, 129 1.2.4.2 skrll bs_notimpl_bs_wm_8, 130 1.2.4.2 skrll 131 1.2.4.2 skrll /* write region */ 132 1.2.4.2 skrll bs_notimpl_bs_wr_1, 133 1.2.4.2 skrll bs_notimpl_bs_wr_2, 134 1.2.4.2 skrll bs_notimpl_bs_wr_4, 135 1.2.4.2 skrll bs_notimpl_bs_wr_8, 136 1.2.4.2 skrll 137 1.2.4.2 skrll /* set multiple */ 138 1.2.4.2 skrll bs_notimpl_bs_sm_1, 139 1.2.4.2 skrll bs_notimpl_bs_sm_2, 140 1.2.4.2 skrll bs_notimpl_bs_sm_4, 141 1.2.4.2 skrll bs_notimpl_bs_sm_8, 142 1.2.4.2 skrll 143 1.2.4.2 skrll /* set region */ 144 1.2.4.2 skrll bs_notimpl_bs_sr_1, 145 1.2.4.2 skrll bs_notimpl_bs_sr_2, 146 1.2.4.2 skrll bs_notimpl_bs_sr_4, 147 1.2.4.2 skrll bs_notimpl_bs_sr_8, 148 1.2.4.2 skrll 149 1.2.4.2 skrll /* copy */ 150 1.2.4.2 skrll bs_notimpl_bs_c_1, 151 1.2.4.2 skrll bs_notimpl_bs_c_2, 152 1.2.4.2 skrll bs_notimpl_bs_c_4, 153 1.2.4.2 skrll bs_notimpl_bs_c_8, 154 1.2.4.2 skrll }; 155 1.2.4.2 skrll 156 1.2.4.2 skrll void 157 1.2.4.2 skrll ixp425_io_bs_init(bus_space_tag_t bs, void *cookie) 158 1.2.4.2 skrll { 159 1.2.4.2 skrll *bs = ixp425_pci_bs_tag_template; 160 1.2.4.2 skrll bs->bs_cookie = cookie; 161 1.2.4.2 skrll 162 1.2.4.2 skrll bs->bs_map = ixp425_pci_io_bs_map; 163 1.2.4.2 skrll bs->bs_unmap = ixp425_pci_io_bs_unmap; 164 1.2.4.2 skrll bs->bs_alloc = ixp425_pci_io_bs_alloc; 165 1.2.4.2 skrll bs->bs_free = ixp425_pci_io_bs_free; 166 1.2.4.2 skrll bs->bs_vaddr = ixp425_pci_io_bs_vaddr; 167 1.2.4.2 skrll 168 1.2.4.2 skrll /* 169 1.2.4.2 skrll * IXP425 processor does not have PCI I/O windows 170 1.2.4.2 skrll */ 171 1.2.4.2 skrll /* read (single) */ 172 1.2.4.2 skrll bs->bs_r_1 = _pci_io_bs_r_1; 173 1.2.4.2 skrll bs->bs_r_2 = _pci_io_bs_r_2; 174 1.2.4.2 skrll bs->bs_r_4 = _pci_io_bs_r_4; 175 1.2.4.2 skrll 176 1.2.4.2 skrll /* write (single) */ 177 1.2.4.2 skrll bs->bs_w_1 = _pci_io_bs_w_1; 178 1.2.4.2 skrll bs->bs_w_2 = _pci_io_bs_w_2; 179 1.2.4.2 skrll bs->bs_w_4 = _pci_io_bs_w_4; 180 1.2.4.2 skrll } 181 1.2.4.2 skrll 182 1.2.4.2 skrll void 183 1.2.4.2 skrll ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie) 184 1.2.4.2 skrll { 185 1.2.4.2 skrll *bs = ixp425_pci_bs_tag_template; 186 1.2.4.2 skrll bs->bs_cookie = cookie; 187 1.2.4.2 skrll 188 1.2.4.2 skrll bs->bs_map = ixp425_pci_mem_bs_map; 189 1.2.4.2 skrll bs->bs_unmap = ixp425_pci_mem_bs_unmap; 190 1.2.4.2 skrll bs->bs_alloc = ixp425_pci_mem_bs_alloc; 191 1.2.4.2 skrll bs->bs_free = ixp425_pci_mem_bs_free; 192 1.2.4.2 skrll bs->bs_vaddr = ixp425_pci_mem_bs_vaddr; 193 1.2.4.2 skrll 194 1.2.4.2 skrll /* read (single) */ 195 1.2.4.2 skrll bs->bs_r_1 = ixp425_pci_mem_bs_r_1; 196 1.2.4.2 skrll bs->bs_r_2 = ixp425_pci_mem_bs_r_2; 197 1.2.4.2 skrll bs->bs_r_4 = ixp425_pci_mem_bs_r_4; 198 1.2.4.2 skrll 199 1.2.4.2 skrll /* write (single) */ 200 1.2.4.2 skrll bs->bs_w_1 = ixp425_pci_mem_bs_w_1; 201 1.2.4.2 skrll bs->bs_w_2 = ixp425_pci_mem_bs_w_2; 202 1.2.4.2 skrll bs->bs_w_4 = ixp425_pci_mem_bs_w_4; 203 1.2.4.2 skrll } 204 1.2.4.2 skrll 205 1.2.4.2 skrll /* common routine */ 206 1.2.4.2 skrll int 207 1.2.4.2 skrll ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, 208 1.2.4.2 skrll bus_size_t size, bus_space_handle_t *nbshp) 209 1.2.4.2 skrll { 210 1.2.4.2 skrll *nbshp = bsh + offset; 211 1.2.4.2 skrll return (0); 212 1.2.4.2 skrll } 213 1.2.4.2 skrll 214 1.2.4.2 skrll void 215 1.2.4.2 skrll ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, 216 1.2.4.2 skrll bus_size_t len, int flags) 217 1.2.4.2 skrll { 218 1.2.4.2 skrll /* NULL */ 219 1.2.4.2 skrll } 220 1.2.4.2 skrll 221 1.2.4.2 skrll paddr_t 222 1.2.4.2 skrll ixp425_pci_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags) 223 1.2.4.2 skrll { 224 1.2.4.2 skrll /* Not supported. */ 225 1.2.4.2 skrll return (-1); 226 1.2.4.2 skrll } 227 1.2.4.2 skrll 228 1.2.4.2 skrll /* io bs */ 229 1.2.4.2 skrll int 230 1.2.4.2 skrll ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, 231 1.2.4.2 skrll int cacheable, bus_space_handle_t *bshp) 232 1.2.4.2 skrll { 233 1.2.4.2 skrll *bshp = bpa; 234 1.2.4.2 skrll return (0); 235 1.2.4.2 skrll } 236 1.2.4.2 skrll 237 1.2.4.2 skrll void 238 1.2.4.2 skrll ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 239 1.2.4.2 skrll { 240 1.2.4.2 skrll /* Nothing to do. */ 241 1.2.4.2 skrll } 242 1.2.4.2 skrll 243 1.2.4.2 skrll int 244 1.2.4.2 skrll ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, 245 1.2.4.2 skrll bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, 246 1.2.4.2 skrll bus_addr_t *bpap, bus_space_handle_t *bshp) 247 1.2.4.2 skrll { 248 1.2.4.2 skrll panic("ixp425_pci_io_bs_alloc(): not implemented\n"); 249 1.2.4.2 skrll } 250 1.2.4.2 skrll 251 1.2.4.2 skrll void 252 1.2.4.2 skrll ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) 253 1.2.4.2 skrll { 254 1.2.4.2 skrll panic("ixp425_pci_io_bs_free(): not implemented\n"); 255 1.2.4.2 skrll } 256 1.2.4.2 skrll 257 1.2.4.2 skrll void * 258 1.2.4.2 skrll ixp425_pci_io_bs_vaddr(void *t, bus_space_handle_t bsh) 259 1.2.4.2 skrll { 260 1.2.4.2 skrll /* Not supported. */ 261 1.2.4.2 skrll return (NULL); 262 1.2.4.2 skrll } 263 1.2.4.2 skrll 264 1.2.4.2 skrll /* special I/O functions */ 265 1.2.4.2 skrll #if 1 /* _pci_io_bs_{rw}_{124} */ 266 1.2.4.2 skrll inline u_int8_t 267 1.2.4.2 skrll _pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) 268 1.2.4.2 skrll { 269 1.2.4.2 skrll u_int32_t data, n, be; 270 1.2.4.2 skrll int s; 271 1.2.4.2 skrll 272 1.2.4.2 skrll n = (ioh + off) % 4; 273 1.2.4.2 skrll be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; 274 1.2.4.2 skrll 275 1.2.4.2 skrll PCI_CONF_LOCK(s); 276 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 277 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 278 1.2.4.2 skrll data = CSR_READ_4(PCI_NP_RDATA); 279 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 280 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 281 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 282 1.2.4.2 skrll 283 1.2.4.2 skrll return data >> (8 * n); 284 1.2.4.2 skrll } 285 1.2.4.2 skrll 286 1.2.4.2 skrll inline u_int16_t 287 1.2.4.2 skrll _pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) 288 1.2.4.2 skrll { 289 1.2.4.2 skrll u_int32_t data, n, be; 290 1.2.4.2 skrll int s; 291 1.2.4.2 skrll 292 1.2.4.2 skrll n = (ioh + off) % 4; 293 1.2.4.2 skrll be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; 294 1.2.4.2 skrll 295 1.2.4.2 skrll PCI_CONF_LOCK(s); 296 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 297 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 298 1.2.4.2 skrll data = CSR_READ_4(PCI_NP_RDATA); 299 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 300 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 301 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 302 1.2.4.2 skrll 303 1.2.4.2 skrll return data >> (8 * n); 304 1.2.4.2 skrll } 305 1.2.4.2 skrll 306 1.2.4.2 skrll inline u_int32_t 307 1.2.4.2 skrll _pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) 308 1.2.4.2 skrll { 309 1.2.4.2 skrll u_int32_t data; 310 1.2.4.2 skrll int s; 311 1.2.4.2 skrll 312 1.2.4.2 skrll PCI_CONF_LOCK(s); 313 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 314 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); 315 1.2.4.2 skrll data = CSR_READ_4(PCI_NP_RDATA); 316 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 317 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 318 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 319 1.2.4.2 skrll 320 1.2.4.2 skrll return data; 321 1.2.4.2 skrll } 322 1.2.4.2 skrll 323 1.2.4.2 skrll inline void 324 1.2.4.2 skrll _pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, 325 1.2.4.2 skrll u_int8_t val) 326 1.2.4.2 skrll { 327 1.2.4.2 skrll u_int32_t data, n, be; 328 1.2.4.2 skrll int s; 329 1.2.4.2 skrll 330 1.2.4.2 skrll n = (ioh + off) % 4; 331 1.2.4.2 skrll be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; 332 1.2.4.2 skrll data = val << (8 * n); 333 1.2.4.2 skrll 334 1.2.4.2 skrll PCI_CONF_LOCK(s); 335 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 336 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); 337 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_WDATA, data); 338 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 339 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 340 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 341 1.2.4.2 skrll } 342 1.2.4.2 skrll 343 1.2.4.2 skrll inline void 344 1.2.4.2 skrll _pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, 345 1.2.4.2 skrll u_int16_t val) 346 1.2.4.2 skrll { 347 1.2.4.2 skrll u_int32_t data, n, be; 348 1.2.4.2 skrll int s; 349 1.2.4.2 skrll 350 1.2.4.2 skrll n = (ioh + off) % 4; 351 1.2.4.2 skrll be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; 352 1.2.4.2 skrll data = val << (8 * n); 353 1.2.4.2 skrll 354 1.2.4.2 skrll PCI_CONF_LOCK(s); 355 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 356 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); 357 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_WDATA, data); 358 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 359 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 360 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 361 1.2.4.2 skrll } 362 1.2.4.2 skrll 363 1.2.4.2 skrll inline void 364 1.2.4.2 skrll _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, 365 1.2.4.2 skrll u_int32_t val) 366 1.2.4.2 skrll { 367 1.2.4.2 skrll int s; 368 1.2.4.2 skrll 369 1.2.4.2 skrll PCI_CONF_LOCK(s); 370 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 371 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE); 372 1.2.4.2 skrll CSR_WRITE_4(PCI_NP_WDATA, val); 373 1.2.4.2 skrll if (CSR_READ_4(PCI_ISR) & ISR_PFE) 374 1.2.4.2 skrll CSR_WRITE_4(PCI_ISR, ISR_PFE); 375 1.2.4.2 skrll PCI_CONF_UNLOCK(s); 376 1.2.4.2 skrll } 377 1.2.4.2 skrll #endif /* _pci_io_bs_{rw}_{124} */ 378 1.2.4.2 skrll 379 1.2.4.2 skrll /* mem bs */ 380 1.2.4.2 skrll int 381 1.2.4.2 skrll ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, 382 1.2.4.2 skrll int cacheable, bus_space_handle_t *bshp) 383 1.2.4.2 skrll { 384 1.2.4.2 skrll const struct pmap_devmap *pd; 385 1.2.4.2 skrll 386 1.2.4.2 skrll paddr_t startpa; 387 1.2.4.2 skrll paddr_t endpa; 388 1.2.4.2 skrll paddr_t pa; 389 1.2.4.2 skrll paddr_t offset; 390 1.2.4.2 skrll vaddr_t va; 391 1.2.4.2 skrll pt_entry_t *pte; 392 1.2.4.2 skrll 393 1.2.4.2 skrll if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) { 394 1.2.4.2 skrll /* Device was statically mapped. */ 395 1.2.4.2 skrll *bshp = pd->pd_va + (bpa - pd->pd_pa); 396 1.2.4.2 skrll return 0; 397 1.2.4.2 skrll } 398 1.2.4.2 skrll 399 1.2.4.2 skrll endpa = round_page(bpa + size); 400 1.2.4.2 skrll offset = bpa & PAGE_MASK; 401 1.2.4.2 skrll startpa = trunc_page(bpa); 402 1.2.4.2 skrll 403 1.2.4.2 skrll /* Get some VM. */ 404 1.2.4.2 skrll if ((va = uvm_km_valloc(kernel_map, endpa - startpa)) == 0) 405 1.2.4.2 skrll return ENOMEM; 406 1.2.4.2 skrll 407 1.2.4.2 skrll /* Store the bus space handle */ 408 1.2.4.2 skrll *bshp = va + offset; 409 1.2.4.2 skrll 410 1.2.4.2 skrll /* Now map the pages */ 411 1.2.4.2 skrll for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 412 1.2.4.2 skrll pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 413 1.2.4.2 skrll pte = vtopte(va); 414 1.2.4.2 skrll *pte &= ~L2_S_CACHE_MASK; 415 1.2.4.2 skrll PTE_SYNC(pte); 416 1.2.4.2 skrll } 417 1.2.4.2 skrll pmap_update(pmap_kernel()); 418 1.2.4.2 skrll 419 1.2.4.2 skrll return(0); 420 1.2.4.2 skrll } 421 1.2.4.2 skrll 422 1.2.4.2 skrll void 423 1.2.4.2 skrll ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 424 1.2.4.2 skrll { 425 1.2.4.2 skrll vaddr_t va; 426 1.2.4.2 skrll vaddr_t endva; 427 1.2.4.2 skrll 428 1.2.4.2 skrll if (pmap_devmap_find_va(bsh, size) != NULL) { 429 1.2.4.2 skrll /* Device was statically mapped; nothing to do. */ 430 1.2.4.2 skrll return; 431 1.2.4.2 skrll } 432 1.2.4.2 skrll 433 1.2.4.2 skrll endva = round_page(bsh + size); 434 1.2.4.2 skrll va = trunc_page(bsh); 435 1.2.4.2 skrll 436 1.2.4.2 skrll pmap_kremove(va, endva - va); 437 1.2.4.2 skrll uvm_km_free(kernel_map, va, endva - va); 438 1.2.4.2 skrll } 439 1.2.4.2 skrll 440 1.2.4.2 skrll int 441 1.2.4.2 skrll ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, 442 1.2.4.2 skrll bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, 443 1.2.4.2 skrll bus_addr_t *bpap, bus_space_handle_t *bshp) 444 1.2.4.2 skrll { 445 1.2.4.2 skrll panic("ixp425_mem_bs_alloc(): not implemented\n"); 446 1.2.4.2 skrll } 447 1.2.4.2 skrll 448 1.2.4.2 skrll void 449 1.2.4.2 skrll ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) 450 1.2.4.2 skrll { 451 1.2.4.2 skrll panic("ixp425_mem_bs_free(): not implemented\n"); 452 1.2.4.2 skrll } 453 1.2.4.2 skrll 454 1.2.4.2 skrll void * 455 1.2.4.2 skrll ixp425_pci_mem_bs_vaddr(void *t, bus_space_handle_t bsh) 456 1.2.4.2 skrll { 457 1.2.4.2 skrll return ((void *)bsh); 458 1.2.4.2 skrll } 459 1.2.4.2 skrll /* End of ixp425_pci_space.c */ 460
Indexes created Sun Oct 26 13:09:57 GMT 2025