ixp425_pci_space.c revision 1.1
1 /* $NetBSD: ixp425_pci_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ixp425_pci_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $"); 38 39 /* 40 * bus_space PCI functions for ixp425 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/queue.h> 46 47 #include <uvm/uvm.h> 48 49 #include <machine/bus.h> 50 51 #include <arm/xscale/ixp425reg.h> 52 #include <arm/xscale/ixp425var.h> 53 54 /* 55 * Macros to read/write registers 56 */ 57 #define CSR_READ_4(x) *(__volatile uint32_t *) \ 58 (IXP425_PCI_CSR_BASE + (x)) 59 #define CSR_WRITE_4(x, v) *(__volatile uint32_t *) \ 60 (IXP425_PCI_CSR_BASE + (x)) = (v) 61 62 /* Proto types for all the bus_space structure functions */ 63 bs_protos(ixp425_pci); 64 bs_protos(ixp425_pci_io); 65 bs_protos(ixp425_pci_mem); 66 bs_protos(bs_notimpl); 67 68 /* special I/O functions */ 69 #if 1 /* XXX */ 70 inline u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t); 71 inline u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t); 72 inline u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t); 73 74 inline void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); 75 inline void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); 76 inline void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); 77 #endif 78 79 struct bus_space ixp425_pci_bs_tag_template = { 80 /* cookie */ 81 (void *) 0, 82 83 /* mapping/unmapping */ 84 NULL, 85 NULL, 86 ixp425_pci_bs_subregion, 87 88 /* allocation/deallocation */ 89 NULL, 90 NULL, 91 92 /* get kernel virtual address */ 93 NULL, 94 95 /* mmap bus space for userland */ 96 ixp425_pci_bs_mmap, 97 98 /* barrier */ 99 ixp425_pci_bs_barrier, 100 101 /* read (single) */ 102 bs_notimpl_bs_r_1, 103 bs_notimpl_bs_r_2, 104 bs_notimpl_bs_r_4, 105 bs_notimpl_bs_r_8, 106 107 /* read multiple */ 108 bs_notimpl_bs_rm_1, 109 bs_notimpl_bs_rm_2, 110 bs_notimpl_bs_rm_4, 111 bs_notimpl_bs_rm_8, 112 113 /* read region */ 114 bs_notimpl_bs_rr_1, 115 bs_notimpl_bs_rr_2, 116 bs_notimpl_bs_rr_4, 117 bs_notimpl_bs_rr_8, 118 119 /* write (single) */ 120 bs_notimpl_bs_w_1, 121 bs_notimpl_bs_w_2, 122 bs_notimpl_bs_w_4, 123 bs_notimpl_bs_w_8, 124 125 /* write multiple */ 126 bs_notimpl_bs_wm_1, 127 bs_notimpl_bs_wm_2, 128 bs_notimpl_bs_wm_4, 129 bs_notimpl_bs_wm_8, 130 131 /* write region */ 132 bs_notimpl_bs_wr_1, 133 bs_notimpl_bs_wr_2, 134 bs_notimpl_bs_wr_4, 135 bs_notimpl_bs_wr_8, 136 137 /* set multiple */ 138 bs_notimpl_bs_sm_1, 139 bs_notimpl_bs_sm_2, 140 bs_notimpl_bs_sm_4, 141 bs_notimpl_bs_sm_8, 142 143 /* set region */ 144 bs_notimpl_bs_sr_1, 145 bs_notimpl_bs_sr_2, 146 bs_notimpl_bs_sr_4, 147 bs_notimpl_bs_sr_8, 148 149 /* copy */ 150 bs_notimpl_bs_c_1, 151 bs_notimpl_bs_c_2, 152 bs_notimpl_bs_c_4, 153 bs_notimpl_bs_c_8, 154 }; 155 156 void 157 ixp425_io_bs_init(bus_space_tag_t bs, void *cookie) 158 { 159 *bs = ixp425_pci_bs_tag_template; 160 bs->bs_cookie = cookie; 161 162 bs->bs_map = ixp425_pci_io_bs_map; 163 bs->bs_unmap = ixp425_pci_io_bs_unmap; 164 bs->bs_alloc = ixp425_pci_io_bs_alloc; 165 bs->bs_free = ixp425_pci_io_bs_free; 166 bs->bs_vaddr = ixp425_pci_io_bs_vaddr; 167 168 /* read (single) */ 169 bs->bs_r_1 = _pci_io_bs_r_1; 170 bs->bs_r_2 = _pci_io_bs_r_2; 171 bs->bs_r_4 = _pci_io_bs_r_4; 172 173 /* write (single) */ 174 bs->bs_w_1 = _pci_io_bs_w_1; 175 bs->bs_w_2 = _pci_io_bs_w_2; 176 bs->bs_w_4 = _pci_io_bs_w_4; 177 } 178 179 void 180 ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie) 181 { 182 *bs = ixp425_pci_bs_tag_template; 183 bs->bs_cookie = cookie; 184 185 bs->bs_map = ixp425_pci_mem_bs_map; 186 bs->bs_unmap = ixp425_pci_mem_bs_unmap; 187 bs->bs_alloc = ixp425_pci_mem_bs_alloc; 188 bs->bs_free = ixp425_pci_mem_bs_free; 189 bs->bs_vaddr = ixp425_pci_mem_bs_vaddr; 190 191 /* read (single) */ 192 bs->bs_r_1 = ixp425_pci_mem_bs_r_1; 193 bs->bs_r_2 = ixp425_pci_mem_bs_r_2; 194 bs->bs_r_4 = ixp425_pci_mem_bs_r_4; 195 196 /* write (single) */ 197 bs->bs_w_1 = ixp425_pci_mem_bs_w_1; 198 bs->bs_w_2 = ixp425_pci_mem_bs_w_2; 199 bs->bs_w_4 = ixp425_pci_mem_bs_w_4; 200 } 201 202 /* common routine */ 203 int 204 ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, 205 bus_size_t size, bus_space_handle_t *nbshp) 206 { 207 *nbshp = bsh + offset; 208 return (0); 209 } 210 211 void 212 ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, 213 bus_size_t len, int flags) 214 { 215 /* NULL */ 216 } 217 218 paddr_t 219 ixp425_pci_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags) 220 { 221 /* Not supported. */ 222 return (-1); 223 } 224 225 /* io bs */ 226 int 227 ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, 228 int cacheable, bus_space_handle_t *bshp) 229 { 230 *bshp = bpa; 231 return (0); 232 } 233 234 void 235 ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 236 { 237 /* Nothing to do. */ 238 } 239 240 int 241 ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, 242 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, 243 bus_addr_t *bpap, bus_space_handle_t *bshp) 244 { 245 panic("ixp425_pci_io_bs_alloc(): not implemented\n"); 246 } 247 248 void 249 ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) 250 { 251 panic("ixp425_pci_io_bs_free(): not implemented\n"); 252 } 253 254 void * 255 ixp425_pci_io_bs_vaddr(void *t, bus_space_handle_t bsh) 256 { 257 /* Not supported. */ 258 return (NULL); 259 } 260 261 /* special I/O functions */ 262 #if 1 /* _pci_io_bs_{rw}_{124} */ 263 inline u_int8_t 264 _pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) 265 { 266 u_int32_t data, n, be; 267 int s; 268 269 n = (ioh + off) % 4; 270 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; 271 272 PCI_CONF_LOCK(s); 273 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 274 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 275 data = CSR_READ_4(PCI_NP_RDATA); 276 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 277 CSR_WRITE_4(PCI_ISR, ISR_PFE); 278 PCI_CONF_UNLOCK(s); 279 280 return data >> (8 * n); 281 } 282 283 inline u_int16_t 284 _pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) 285 { 286 u_int32_t data, n, be; 287 int s; 288 289 n = (ioh + off) % 4; 290 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; 291 292 PCI_CONF_LOCK(s); 293 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 294 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 295 data = CSR_READ_4(PCI_NP_RDATA); 296 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 297 CSR_WRITE_4(PCI_ISR, ISR_PFE); 298 PCI_CONF_UNLOCK(s); 299 300 return data >> (8 * n); 301 } 302 303 inline u_int32_t 304 _pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) 305 { 306 u_int32_t data; 307 int s; 308 309 PCI_CONF_LOCK(s); 310 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 311 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); 312 data = CSR_READ_4(PCI_NP_RDATA); 313 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 314 CSR_WRITE_4(PCI_ISR, ISR_PFE); 315 PCI_CONF_UNLOCK(s); 316 317 return data; 318 } 319 320 inline void 321 _pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, 322 u_int8_t val) 323 { 324 u_int32_t data, n, be; 325 int s; 326 327 n = (ioh + off) % 4; 328 be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; 329 data = val << (8 * n); 330 331 PCI_CONF_LOCK(s); 332 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 333 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); 334 CSR_WRITE_4(PCI_NP_WDATA, data); 335 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 336 CSR_WRITE_4(PCI_ISR, ISR_PFE); 337 PCI_CONF_UNLOCK(s); 338 } 339 340 inline void 341 _pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, 342 u_int16_t val) 343 { 344 u_int32_t data, n, be; 345 int s; 346 347 n = (ioh + off) % 4; 348 be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; 349 data = val << (8 * n); 350 351 PCI_CONF_LOCK(s); 352 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 353 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); 354 CSR_WRITE_4(PCI_NP_WDATA, data); 355 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 356 CSR_WRITE_4(PCI_ISR, ISR_PFE); 357 PCI_CONF_UNLOCK(s); 358 } 359 360 inline void 361 _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, 362 u_int32_t val) 363 { 364 int s; 365 366 PCI_CONF_LOCK(s); 367 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 368 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE); 369 CSR_WRITE_4(PCI_NP_WDATA, val); 370 if (CSR_READ_4(PCI_ISR) & ISR_PFE) 371 CSR_WRITE_4(PCI_ISR, ISR_PFE); 372 PCI_CONF_UNLOCK(s); 373 } 374 #endif /* _pci_io_bs_{rw}_{124} */ 375 376 /* mem bs */ 377 int 378 ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, 379 int cacheable, bus_space_handle_t *bshp) 380 { 381 const struct pmap_devmap *pd; 382 383 paddr_t startpa; 384 paddr_t endpa; 385 paddr_t pa; 386 paddr_t offset; 387 vaddr_t va; 388 pt_entry_t *pte; 389 390 if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) { 391 /* Device was statically mapped. */ 392 *bshp = pd->pd_va + (bpa - pd->pd_pa); 393 return 0; 394 } 395 396 endpa = round_page(bpa + size); 397 offset = bpa & PAGE_MASK; 398 startpa = trunc_page(bpa); 399 400 /* Get some VM. */ 401 if ((va = uvm_km_valloc(kernel_map, endpa - startpa)) == 0) 402 return ENOMEM; 403 404 /* Store the bus space handle */ 405 *bshp = va + offset; 406 407 /* Now map the pages */ 408 for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 409 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 410 pte = vtopte(va); 411 *pte &= ~L2_S_CACHE_MASK; 412 PTE_SYNC(pte); 413 } 414 pmap_update(pmap_kernel()); 415 416 return(0); 417 } 418 419 void 420 ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 421 { 422 vaddr_t va; 423 vaddr_t endva; 424 425 if (pmap_devmap_find_va(bsh, size) != NULL) { 426 /* Device was statically mapped; nothing to do. */ 427 return; 428 } 429 430 endva = round_page(bsh + size); 431 va = trunc_page(bsh); 432 433 pmap_kremove(va, endva - va); 434 uvm_km_free(kernel_map, va, endva - va); 435 } 436 437 int 438 ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, 439 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, 440 bus_addr_t *bpap, bus_space_handle_t *bshp) 441 { 442 panic("ixp425_mem_bs_alloc(): not implemented\n"); 443 } 444 445 void 446 ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) 447 { 448 panic("ixp425_mem_bs_free(): not implemented\n"); 449 } 450 451 void * 452 ixp425_pci_mem_bs_vaddr(void *t, bus_space_handle_t bsh) 453 { 454 return ((void *)bsh); 455 } 456 /* End of ixp425_pci_space.c */ 457
Indexes created Sun Oct 26 13:09:57 GMT 2025