ixp425var.h revision 1.11
1 /* $NetBSD: ixp425var.h,v 1.11 2006/12/10 10:01:49 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _IXP425VAR_H_ 37 #define _IXP425VAR_H_ 38 39 #include <sys/conf.h> 40 #include <sys/device.h> 41 #include <sys/queue.h> 42 43 #include <machine/bus.h> 44 45 #include <dev/pci/pcivar.h> 46 47 #define PCI_CSR_WRITE_4(sc, reg, data) \ 48 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, \ 49 reg, data) 50 51 #define PCI_CSR_READ_4(sc, reg) \ 52 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, reg) 53 54 #define GPIO_CONF_WRITE_4(sc, reg, data) \ 55 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, \ 56 reg, data) 57 58 #define GPIO_CONF_READ_4(sc, reg) \ 59 bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg) 60 61 #define EXP_BUS_WRITE_4(sc, reg, data) \ 62 bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data) 63 64 #define EXP_BUS_READ_4(sc, reg) \ 65 bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg) 66 67 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 68 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 69 70 struct ixp425_softc { 71 struct device sc_dev; 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; /* IRQ handle */ 74 75 u_int32_t sc_intrmask; 76 77 /* Handles for the various subregions. */ 78 bus_space_handle_t sc_pci_ioh; /* PCI mem handler */ 79 bus_space_handle_t sc_gpio_ioh; /* GPIOs handler */ 80 bus_space_handle_t sc_exp_ioh; /* Expansion bus handle */ 81 82 /* Bus space, DMA, and PCI tags for the PCI bus */ 83 struct bus_space sc_pci_iot; 84 struct bus_space sc_pci_memt; 85 struct arm32_bus_dma_tag ia_pci_dmat; 86 struct arm32_pci_chipset ia_pci_chipset; 87 vaddr_t sc_pci_va; 88 89 /* DMA window info for PCI DMA. */ 90 struct arm32_dma_range ia_pci_dma_range; 91 92 /* GPIO configuration */ 93 u_int32_t sc_gpio_out; 94 u_int32_t sc_gpio_oe; 95 u_int32_t sc_gpio_intr1; 96 u_int32_t sc_gpio_intr2; 97 }; 98 99 /* 100 * There are roughly 32 interrupt sources. 101 */ 102 #define NIRQ 32 103 104 struct intrhand { 105 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 106 int (*ih_func)(void *); /* interrupt handler */ 107 void *ih_arg; /* arg for handler */ 108 int ih_ipl; /* IPL_* */ 109 int ih_irq; /* IRQ number */ 110 }; 111 112 #define IRQNAMESIZE sizeof("ixp425 irq xx") 113 114 struct intrq { 115 TAILQ_HEAD(, intrhand) iq_list; /* handler list */ 116 struct evcnt iq_ev; /* event counter */ 117 u_int32_t iq_mask; /* IRQs to mask while handling */ 118 u_int32_t iq_pci_mask; /* PCI IRQs to mask while handling */ 119 u_int32_t iq_levels; /* IPL_*'s this IRQ has */ 120 char iq_name[IRQNAMESIZE]; /* interrupt name */ 121 int iq_ist; /* share type */ 122 }; 123 124 struct pmap_ent { 125 const char* msg; 126 vaddr_t va; 127 paddr_t pa; 128 vsize_t sz; 129 int prot; 130 int cache; 131 }; 132 133 extern struct ixp425_softc *ixp425_softc; 134 135 extern struct bus_space ixpsip_bs_tag; 136 extern struct bus_space ixp425_bs_tag; 137 extern struct bus_space ixp425_a4x_bs_tag; 138 139 void ixp425_bs_init(bus_space_tag_t, void *); 140 void ixp425_md_pci_init(struct ixp425_softc *); 141 void ixp425_md_pci_conf_interrupt(pci_chipset_tag_t, int, int, int, 142 int, int *); 143 void ixp425_pci_init(struct ixp425_softc *); 144 void ixp425_pci_dma_init(struct ixp425_softc *); 145 void ixp425_io_bs_init(bus_space_tag_t, void *); 146 void ixp425_mem_bs_init(bus_space_tag_t, void *); 147 148 void ixp425_pci_conf_reg_write(struct ixp425_softc *, uint32_t, uint32_t); 149 uint32_t ixp425_pci_conf_reg_read(struct ixp425_softc *, uint32_t); 150 151 void ixp425_attach(struct ixp425_softc *); 152 void ixp425_icu_init(void); 153 void ixp425_clk_bootstrap(bus_space_tag_t); 154 void ixp425_intr_init(void); 155 void *ixp425_intr_establish(int, int, int (*)(void *), void *); 156 void ixp425_intr_disestablish(void *); 157 158 uint32_t ixp425_sdram_size(void); 159 160 #endif /* _IXP425VAR_H_ */ 161
Indexes created Tue Sep 30 06:09:59 GMT 2025