ixp425var.h revision 1.5 1 /* $NetBSD: ixp425var.h,v 1.5 2003/10/08 14:55:04 scw Exp $ */
2
3 /*
4 * Copyright (c) 2003
5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Ichiro FUKUHARA.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #ifndef _IXP425VAR_H_
37 #define _IXP425VAR_H_
38
39 #include <sys/conf.h>
40 #include <sys/device.h>
41 #include <sys/queue.h>
42
43 #include <machine/bus.h>
44
45 #include <dev/pci/pcivar.h>
46
47 #define PCI_CSR_WRITE_4(sc, reg, data) \
48 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, \
49 reg, data)
50
51 #define PCI_CSR_READ_4(sc, reg) \
52 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, reg)
53
54 #define GPIO_CONF_WRITE_4(sc, reg, data) \
55 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, \
56 reg, data)
57
58 #define GPIO_CONF_READ_4(sc, reg) \
59 bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
60
61 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
62 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
63
64 struct ixp425_softc {
65 struct device sc_dev;
66 bus_space_tag_t sc_iot;
67 bus_space_handle_t sc_ioh; /* IRQ handle */
68
69 u_int32_t sc_intrmask;
70
71 /* Handles for the various subregions. */
72 bus_space_handle_t sc_pci_ioh; /* PCI mem handler */
73 bus_space_handle_t sc_gpio_ioh; /* GPIOs handler */
74
75 /* Bus space, DMA, and PCI tags for the PCI bus */
76 struct bus_space sc_pci_iot;
77 struct bus_space sc_pci_memt;
78 struct arm32_bus_dma_tag ia_pci_dmat;
79 struct arm32_pci_chipset ia_pci_chipset;
80 vaddr_t sc_pci_va;
81
82 /* DMA window info for PCI DMA. */
83 struct arm32_dma_range ia_pci_dma_range;
84
85 /* GPIO configuration */
86 u_int32_t sc_gpio_out;
87 u_int32_t sc_gpio_oe;
88 u_int32_t sc_gpio_intr1;
89 u_int32_t sc_gpio_intr2;
90 };
91
92 /*
93 * There are roughly 32 interrupt sources.
94 */
95 #define NIRQ 32
96
97 struct intrhand {
98 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
99 int (*ih_func)(void *); /* interrupt handler */
100 void *ih_arg; /* arg for handler */
101 int ih_ipl; /* IPL_* */
102 int ih_irq; /* IRQ number */
103 };
104
105 #define IRQNAMESIZE sizeof("ixp425 irq xx")
106
107 struct intrq {
108 TAILQ_HEAD(, intrhand) iq_list; /* handler list */
109 struct evcnt iq_ev; /* event counter */
110 u_int32_t iq_mask; /* IRQs to mask while handling */
111 u_int32_t iq_pci_mask; /* PCI IRQs to mask while handling */
112 u_int32_t iq_levels; /* IPL_*'s this IRQ has */
113 char iq_name[IRQNAMESIZE]; /* interrupt name */
114 int iq_ist; /* share type */
115 };
116
117 struct pmap_ent {
118 const char* msg;
119 vaddr_t va;
120 paddr_t pa;
121 vsize_t sz;
122 int prot;
123 int cache;
124 };
125
126 extern struct ixp425_softc *ixp425_softc;
127
128 extern struct bus_space ixpsip_bs_tag;
129 extern struct bus_space ixp425_bs_tag;
130 extern struct bus_space ixp425_a4x_bs_tag;
131
132 void ixp425_bs_init(bus_space_tag_t, void *);
133 void ixp425_md_pci_init(struct ixp425_softc *);
134 void ixp425_md_pci_conf_interrupt(pci_chipset_tag_t, int, int, int,
135 int, int *);
136 void ixp425_pci_init(struct ixp425_softc *);
137 void ixp425_pci_dma_init(struct ixp425_softc *);
138 void ixp425_io_bs_init(bus_space_tag_t, void *);
139 void ixp425_mem_bs_init(bus_space_tag_t, void *);
140
141 void ixp425_pci_conf_reg_write(struct ixp425_softc *, uint32_t, uint32_t);
142 uint32_t ixp425_pci_conf_reg_read(struct ixp425_softc *, uint32_t);
143
144 void ixp425_attach(struct ixp425_softc *);
145 void ixp425_icu_init(void);
146 void ixp425_clk_bootstrap(bus_space_tag_t);
147 void ixp425_intr_init(void);
148 void *ixp425_intr_establish(int, int, int (*)(void *), void *);
149 void ixp425_intr_disestablish(void *);
150
151
152 #endif /* _IXP425VAR_H_ */
153