pxa2x0.c revision 1.16
1 /* $NetBSD: pxa2x0.c,v 1.16 2007/02/21 22:59:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2005 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * 36 * Autoconfiguration support for the Intel PXA2[15]0 application 37 * processor. This code is derived from arm/sa11x0/sa11x0.c 38 */ 39 40 /*- 41 * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. 42 * 43 * This code is derived from software contributed to The NetBSD Foundation 44 * by IWAMOTO Toshihiro and Ichiro FUKUHARA. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the NetBSD 57 * Foundation, Inc. and its contributors. 58 * 4. Neither the name of The NetBSD Foundation nor the names of its 59 * contributors may be used to endorse or promote products derived 60 * from this software without specific prior written permission. 61 */ 62 /*- 63 * Copyright (c) 1999 64 * Shin Takemura and PocketBSD Project. All rights reserved. 65 * 66 * Redistribution and use in source and binary forms, with or without 67 * modification, are permitted provided that the following conditions 68 * are met: 69 * 1. Redistributions of source code must retain the above copyright 70 * notice, this list of conditions and the following disclaimer. 71 * 2. Redistributions in binary form must reproduce the above copyright 72 * notice, this list of conditions and the following disclaimer in the 73 * documentation and/or other materials provided with the distribution. 74 * 3. All advertising materials mentioning features or use of this software 75 * must display the following acknowledgement: 76 * This product includes software developed by the PocketBSD project 77 * and its contributors. 78 * 4. Neither the name of the project nor the names of its contributors 79 * may be used to endorse or promote products derived from this software 80 * without specific prior written permission. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 83 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 84 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 85 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 86 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 87 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 88 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 89 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 90 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 91 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 92 * SUCH DAMAGE. 93 * 94 */ 95 96 #include <sys/cdefs.h> 97 __KERNEL_RCSID(0, "$NetBSD: pxa2x0.c,v 1.16 2007/02/21 22:59:39 thorpej Exp $"); 98 99 #include "pxaintc.h" 100 #include "pxagpio.h" 101 #if 0 102 #include "pxadmac.h" /* Not yet */ 103 #endif 104 105 #include "locators.h" 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/device.h> 110 #include <sys/kernel.h> 111 #include <sys/reboot.h> 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 116 #include <arm/cpufunc.h> 117 #include <arm/mainbus/mainbus.h> 118 #include <arm/xscale/pxa2x0cpu.h> 119 #include <arm/xscale/pxa2x0reg.h> 120 #include <arm/xscale/pxa2x0var.h> 121 #include <arm/xscale/xscalereg.h> 122 123 struct pxaip_softc { 124 struct device sc_dev; 125 bus_space_tag_t sc_bust; 126 bus_dma_tag_t sc_dmat; 127 bus_space_handle_t sc_bush_clk; 128 bus_space_handle_t sc_bush_mem; 129 }; 130 131 /* prototypes */ 132 static int pxaip_match(struct device *, struct cfdata *, void *); 133 static void pxaip_attach(struct device *, struct device *, void *); 134 static int pxaip_search(struct device *, struct cfdata *, 135 const int *, void *); 136 static void pxaip_attach_critical(struct pxaip_softc *); 137 static int pxaip_print(void *, const char *); 138 139 static int pxaip_measure_cpuclock(struct pxaip_softc *); 140 141 #if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270) 142 # define SUPPORTED_CPU "PXA250 and PXA270" 143 #elif defined(CPU_XSCALE_PXA250) 144 # define SUPPORTED_CPU "PXA250" 145 #elif defined(CPU_XSCALE_PXA270) 146 # define SUPPORTED_CPU "PXA270" 147 #else 148 # define SUPPORTED_CPU "none of PXA2xx" 149 #endif 150 151 /* attach structures */ 152 CFATTACH_DECL(pxaip, sizeof(struct pxaip_softc), 153 pxaip_match, pxaip_attach, NULL, NULL); 154 155 static struct pxaip_softc *pxaip_sc; 156 static vaddr_t pxamemctl_regs; 157 #define MEMCTL_BOOTSTRAP_REG(reg) \ 158 (*((volatile uint32_t *)(pxamemctl_regs + (reg)))) 159 static vaddr_t pxaclkman_regs; 160 #define CLKMAN_BOOTSTRAP_REG(reg) \ 161 (*((volatile uint32_t *)(pxaclkman_regs + (reg)))) 162 163 static int 164 pxaip_match(struct device *parent, struct cfdata *match, void *aux) 165 { 166 167 #if !defined(CPU_XSCALE_PXA270) 168 if (__CPU_IS_PXA270) 169 goto bad_config; 170 #endif 171 172 #if !defined(CPU_XSCALE_PXA250) 173 if (__CPU_IS_PXA250) 174 goto bad_config; 175 #endif 176 177 return 1; 178 179 #if defined(CPU_XSCALE_PXA250) + defined(CPU_XSCALE_PXA270) != 2 180 bad_config: 181 aprint_error("Kernel is configured for %s, but CPU is %s\n", 182 SUPPORTED_CPU, __CPU_IS_PXA270 ? "PXA270" : "PXA250"); 183 return 0; 184 #endif 185 } 186 187 static void 188 pxaip_attach(struct device *parent, struct device *self, void *aux) 189 { 190 struct pxaip_softc *sc = (struct pxaip_softc *)self; 191 int cpuclock; 192 193 pxaip_sc = sc; 194 sc->sc_bust = &pxa2x0_bs_tag; 195 sc->sc_dmat = &pxa2x0_bus_dma_tag; 196 197 aprint_normal(": PXA2x0 Onchip Peripheral Bus\n"); 198 199 if (bus_space_map(sc->sc_bust, PXA2X0_CLKMAN_BASE, PXA2X0_CLKMAN_SIZE, 200 0, &sc->sc_bush_clk)) 201 panic("pxaip_attach: failed to map CLKMAN"); 202 203 if (bus_space_map(sc->sc_bust, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 204 0, &sc->sc_bush_mem)) 205 panic("pxaip_attach: failed to map MEMCTL"); 206 207 /* 208 * Calculate clock speed 209 * This takes 2 secs at most. 210 */ 211 cpuclock = pxaip_measure_cpuclock(sc) / 1000; 212 printf("%s: CPU clock = %d.%03d MHz\n", self->dv_xname, 213 cpuclock/1000, cpuclock%1000 ); 214 215 aprint_normal("%s: kernel is configured for " SUPPORTED_CPU 216 ", cpu type is %s\n", 217 self->dv_xname, 218 __CPU_IS_PXA270 ? "PXA270" : "PXA250"); 219 220 /* 221 * Attach critical devices 222 */ 223 pxaip_attach_critical(sc); 224 225 /* 226 * Attach all other devices 227 */ 228 config_search_ia(pxaip_search, self, "pxaip", sc); 229 } 230 231 static int 232 pxaip_search(struct device *parent, struct cfdata *cf, 233 const int *ldesc, void *aux) 234 { 235 struct pxaip_softc *sc = aux; 236 struct pxaip_attach_args aa; 237 238 aa.pxa_iot = sc->sc_bust; 239 aa.pxa_dmat = sc->sc_dmat; 240 aa.pxa_addr = cf->cf_loc[PXAIPCF_ADDR]; 241 aa.pxa_size = cf->cf_loc[PXAIPCF_SIZE]; 242 aa.pxa_index = cf->cf_loc[PXAIPCF_INDEX]; 243 aa.pxa_intr = cf->cf_loc[PXAIPCF_INTR]; 244 245 if (config_match(parent, cf, &aa)) 246 config_attach(parent, cf, &aa, pxaip_print); 247 248 return 0; 249 } 250 251 static void 252 pxaip_attach_critical(struct pxaip_softc *sc) 253 { 254 struct pxaip_attach_args aa; 255 256 aa.pxa_iot = sc->sc_bust; 257 aa.pxa_dmat = sc->sc_dmat; 258 aa.pxa_addr = PXA2X0_INTCTL_BASE; 259 aa.pxa_size = PXA2X0_INTCTL_SIZE; 260 aa.pxa_intr = PXAIPCF_INTR_DEFAULT; 261 if (config_found(&sc->sc_dev, &aa, pxaip_print) == NULL) 262 panic("pxaip_attach_critical: failed to attach INTC!"); 263 264 #if NPXAGPIO > 0 265 aa.pxa_iot = sc->sc_bust; 266 aa.pxa_dmat = sc->sc_dmat; 267 aa.pxa_addr = PXA2X0_GPIO_BASE; 268 aa.pxa_size = PXA2X0_GPIO_SIZE; 269 aa.pxa_intr = PXAIPCF_INTR_DEFAULT; 270 if (config_found(&sc->sc_dev, &aa, pxaip_print) == NULL) 271 panic("pxaip_attach_critical: failed to attach GPIO!"); 272 #endif 273 274 #if NPXADMAC > 0 275 aa.pxa_iot = sc->sc_bust; 276 aa.pxa_dmat = sc->sc_dmat; 277 aa.pxa_addr = PXA2X0_DMAC_BASE; 278 aa.pxa_size = PXA2X0_DMAC_SIZE; 279 aa.pxa_intr = PXA2X0_INT_DMA; 280 if (config_found(&sc->sc_dev, &aa, pxaip_print) == NULL) 281 panic("pxaip_attach_critical: failed to attach DMAC!"); 282 #endif 283 } 284 285 static int 286 pxaip_print(void *aux, const char *name) 287 { 288 struct pxaip_attach_args *sa = (struct pxaip_attach_args*)aux; 289 290 if (sa->pxa_addr != PXAIPCF_ADDR_DEFAULT) { 291 aprint_normal(" addr 0x%lx", sa->pxa_addr); 292 if (sa->pxa_size > PXAIPCF_SIZE_DEFAULT) 293 aprint_normal("-0x%lx", sa->pxa_addr + sa->pxa_size-1); 294 } 295 if (sa->pxa_intr != PXAIPCF_INTR_DEFAULT) 296 aprint_normal(" intr %d", sa->pxa_intr); 297 298 return (UNCONF); 299 } 300 301 static inline uint32_t 302 read_clock_counter_xsc1(void) 303 { 304 uint32_t x; 305 __asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (x) ); 306 307 return x; 308 } 309 310 static inline uint32_t 311 read_clock_counter_xsc2(void) 312 { 313 uint32_t x; 314 __asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (x) ); 315 316 return x; 317 } 318 319 static int 320 pxaip_measure_cpuclock(struct pxaip_softc *sc) 321 { 322 uint32_t rtc0, rtc1, start, end; 323 uint32_t pmcr_save; 324 bus_space_handle_t ioh; 325 int irq; 326 int is_xsc2 = CPU_IS_PXA270; 327 #define read_clock_counter() (is_xsc2 ? read_clock_counter_xsc2() : \ 328 read_clock_counter_xsc1()) 329 330 if (bus_space_map(sc->sc_bust, PXA2X0_RTC_BASE, PXA2X0_RTC_SIZE, 0, 331 &ioh)) 332 panic("pxaip_measure_cpuclock: can't map RTC"); 333 334 irq = disable_interrupts(I32_bit|F32_bit); 335 336 if (is_xsc2) { 337 __asm volatile( 338 "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save)); 339 /* Enable clock counter */ 340 __asm volatile( 341 "mcr p14, 0, %0, c0, c1, 0" : : "r" (PMNC_E|PMNC_C)); 342 } 343 else { 344 __asm volatile( 345 "mrc p14, 0, %0, c0, c0, 0" : "=r" (pmcr_save)); 346 /* Enable clock counter */ 347 __asm volatile( 348 "mcr p14, 0, %0, c0, c0, 0" : : "r" (PMNC_E|PMNC_C)); 349 } 350 351 rtc0 = bus_space_read_4(sc->sc_bust, ioh, RTC_RCNR); 352 /* Wait for next second starts */ 353 while ((rtc1 = bus_space_read_4(sc->sc_bust, ioh, RTC_RCNR)) == rtc0) 354 ; 355 start = read_clock_counter(); 356 while(rtc1 == bus_space_read_4(sc->sc_bust, ioh, RTC_RCNR)) 357 ; /* Wait for 1sec */ 358 end = read_clock_counter(); 359 360 if (is_xsc2) 361 __asm volatile( 362 "mcr p14, 0, %0, c0, c1, 0" : : "r" (pmcr_save)); 363 else 364 __asm volatile( 365 "mcr p14, 0, %0, c0, c0, 0" : : "r" (pmcr_save)); 366 restore_interrupts(irq); 367 368 bus_space_unmap(sc->sc_bust, ioh, PXA2X0_RTC_SIZE); 369 370 return end - start; 371 } 372 373 void 374 pxa2x0_turbo_mode(int f) 375 { 376 __asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r" (f)); 377 } 378 379 void 380 pxa2x0_probe_sdram(vaddr_t memctl_va, paddr_t *start, paddr_t *size) 381 { 382 u_int32_t mdcnfg, dwid, dcac, drac, dnb; 383 int i; 384 385 mdcnfg = *((volatile u_int32_t *)(memctl_va + MEMCTL_MDCNFG)); 386 387 /* 388 * Scan all 4 SDRAM banks 389 */ 390 for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) { 391 start[i] = 0; 392 size[i] = 0; 393 394 switch (i) { 395 case 0: 396 case 1: 397 if ((i == 0 && (mdcnfg & MDCNFG_DE0) == 0) || 398 (i == 1 && (mdcnfg & MDCNFG_DE1) == 0)) 399 continue; 400 dwid = mdcnfg >> MDCNFD_DWID01_SHIFT; 401 dcac = mdcnfg >> MDCNFD_DCAC01_SHIFT; 402 drac = mdcnfg >> MDCNFD_DRAC01_SHIFT; 403 dnb = mdcnfg >> MDCNFD_DNB01_SHIFT; 404 break; 405 406 case 2: 407 case 3: 408 if ((i == 2 && (mdcnfg & MDCNFG_DE2) == 0) || 409 (i == 3 && (mdcnfg & MDCNFG_DE3) == 0)) 410 continue; 411 dwid = mdcnfg >> MDCNFD_DWID23_SHIFT; 412 dcac = mdcnfg >> MDCNFD_DCAC23_SHIFT; 413 drac = mdcnfg >> MDCNFD_DRAC23_SHIFT; 414 dnb = mdcnfg >> MDCNFD_DNB23_SHIFT; 415 break; 416 default: 417 panic("pxa2x0_probe_sdram: impossible"); 418 } 419 420 dwid = 2 << (1 - (dwid & MDCNFD_DWID_MASK)); /* 16/32 width */ 421 dcac = 1 << ((dcac & MDCNFD_DCAC_MASK) + 8); /* 8-11 columns */ 422 drac = 1 << ((drac & MDCNFD_DRAC_MASK) + 11); /* 11-13 rows */ 423 dnb = 2 << (dnb & MDCNFD_DNB_MASK); /* # of banks */ 424 425 size[i] = (paddr_t)(dwid * dcac * drac * dnb); 426 start[i] = PXA2X0_SDRAM0_START + (i * PXA2X0_SDRAM_BANK_SIZE); 427 } 428 } 429 430 void 431 pxa2x0_memctl_bootstrap(vaddr_t va) 432 { 433 434 pxamemctl_regs = va; 435 } 436 437 uint32_t 438 pxa2x0_memctl_read(int reg) 439 { 440 struct pxaip_softc *sc; 441 bus_space_tag_t iot; 442 bus_space_handle_t ioh; 443 444 if (__predict_true(pxaip_sc != NULL)) { 445 sc = pxaip_sc; 446 iot = sc->sc_bust; 447 ioh = sc->sc_bush_mem; 448 return (bus_space_read_4(iot, ioh, reg)); 449 } else if (__predict_true(pxamemctl_regs != 0)) { 450 return (MEMCTL_BOOTSTRAP_REG(reg)); 451 } 452 panic("pxa2x0_memctl_read: not bootstrapped"); 453 /*NOTREACHED*/ 454 } 455 456 void 457 pxa2x0_memctl_write(int reg, uint32_t val) 458 { 459 struct pxaip_softc *sc; 460 bus_space_tag_t iot; 461 bus_space_handle_t ioh; 462 463 if (__predict_true(pxaip_sc != NULL)) { 464 sc = pxaip_sc; 465 iot = sc->sc_bust; 466 ioh = sc->sc_bush_mem; 467 bus_space_write_4(iot, ioh, reg, val); 468 } else if (__predict_true(pxamemctl_regs != 0)) { 469 MEMCTL_BOOTSTRAP_REG(reg) = val; 470 } else { 471 panic("pxa2x0_memctl_write: not bootstrapped"); 472 } 473 return; 474 } 475 476 void 477 pxa2x0_clkman_bootstrap(vaddr_t va) 478 { 479 480 pxaclkman_regs = va; 481 } 482 483 void 484 pxa2x0_clkman_config(u_int clk, bool enable) 485 { 486 struct pxaip_softc *sc; 487 bus_space_tag_t iot; 488 bus_space_handle_t ioh; 489 uint32_t rv; 490 491 if (__predict_true(pxaip_sc != NULL)) { 492 sc = pxaip_sc; 493 iot = sc->sc_bust; 494 ioh = sc->sc_bush_clk; 495 496 rv = bus_space_read_4(iot, ioh, CLKMAN_CKEN); 497 rv &= ~clk; 498 if (enable) 499 rv |= clk; 500 bus_space_write_4(iot, ioh, CLKMAN_CKEN, rv); 501 return; 502 } else if (__predict_true(pxaclkman_regs != 0)) { 503 rv = CLKMAN_BOOTSTRAP_REG(CLKMAN_CKEN); 504 rv &= ~clk; 505 if (enable) 506 rv |= clk; 507 CLKMAN_BOOTSTRAP_REG(CLKMAN_CKEN) = rv; 508 return; 509 } 510 panic("pxa2x0_clkman_config: not bootstrapped"); 511 } 512
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