Home | History | Annotate | Line # | Download | only in xscale
pxa2x0_ac97.c revision 1.13.14.1
      1  1.13.14.1     skrll /*	$NetBSD: pxa2x0_ac97.c,v 1.13.14.1 2017/08/28 17:51:32 skrll Exp $	*/
      2        1.1       scw 
      3        1.1       scw /*
      4        1.1       scw  * Copyright (c) 2003, 2005 Wasabi Systems, Inc.
      5        1.1       scw  * All rights reserved.
      6        1.1       scw  *
      7        1.1       scw  * Written by Steve C. Woodford for Wasabi Systems, Inc.
      8        1.1       scw  *
      9        1.1       scw  * Redistribution and use in source and binary forms, with or without
     10        1.1       scw  * modification, are permitted provided that the following conditions
     11        1.1       scw  * are met:
     12        1.1       scw  * 1. Redistributions of source code must retain the above copyright
     13        1.1       scw  *    notice, this list of conditions and the following disclaimer.
     14        1.1       scw  * 2. Redistributions in binary form must reproduce the above copyright
     15        1.1       scw  *    notice, this list of conditions and the following disclaimer in the
     16        1.1       scw  *    documentation and/or other materials provided with the distribution.
     17        1.1       scw  * 3. All advertising materials mentioning features or use of this software
     18        1.1       scw  *    must display the following acknowledgement:
     19        1.1       scw  *	This product includes software developed for the NetBSD Project by
     20        1.1       scw  *	Wasabi Systems, Inc.
     21        1.1       scw  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22        1.1       scw  *    or promote products derived from this software without specific prior
     23        1.1       scw  *    written permission.
     24        1.1       scw  *
     25        1.1       scw  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26        1.1       scw  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27        1.1       scw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28        1.1       scw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29        1.1       scw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30        1.1       scw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31        1.1       scw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32        1.1       scw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33        1.1       scw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34        1.1       scw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35        1.1       scw  * POSSIBILITY OF SUCH DAMAGE.
     36        1.1       scw  */
     37        1.1       scw 
     38        1.1       scw #include <sys/param.h>
     39        1.1       scw #include <sys/systm.h>
     40        1.1       scw #include <sys/device.h>
     41        1.1       scw #include <sys/kernel.h>
     42        1.1       scw #include <sys/malloc.h>
     43        1.1       scw #include <sys/select.h>
     44        1.1       scw #include <sys/audioio.h>
     45       1.10  jmcneill #include <sys/kmem.h>
     46        1.1       scw 
     47        1.1       scw #include <machine/intr.h>
     48        1.9    dyoung #include <sys/bus.h>
     49        1.1       scw 
     50        1.1       scw #include <dev/audio_if.h>
     51        1.1       scw #include <dev/audiovar.h>
     52        1.1       scw #include <dev/mulaw.h>
     53        1.1       scw #include <dev/auconv.h>
     54        1.1       scw #include <dev/ic/ac97reg.h>
     55        1.1       scw #include <dev/ic/ac97var.h>
     56        1.1       scw 
     57        1.6  kiyohara #include <arm/xscale/pxa2x0cpu.h>
     58        1.1       scw #include <arm/xscale/pxa2x0reg.h>
     59        1.1       scw #include <arm/xscale/pxa2x0var.h>
     60        1.1       scw #include <arm/xscale/pxa2x0_gpio.h>
     61        1.1       scw #include <arm/xscale/pxa2x0_dmac.h>
     62        1.1       scw 
     63        1.1       scw #include "locators.h"
     64        1.1       scw 
     65        1.1       scw struct acu_dma {
     66        1.1       scw 	bus_dmamap_t ad_map;
     67        1.5  christos 	void *ad_addr;
     68        1.1       scw #define	ACU_N_SEGS	1	/* XXX: We don't support > 1 */
     69        1.1       scw 	bus_dma_segment_t ad_segs[ACU_N_SEGS];
     70        1.1       scw 	int ad_nsegs;
     71        1.1       scw 	size_t ad_size;
     72        1.1       scw 	struct dmac_xfer *ad_dx;
     73        1.1       scw 	struct acu_dma *ad_next;
     74        1.1       scw };
     75        1.1       scw 
     76        1.1       scw #define KERNADDR(ad) ((void *)((ad)->ad_addr))
     77        1.1       scw 
     78        1.1       scw struct acu_softc {
     79        1.8    nonaka 	device_t sc_dev;
     80        1.1       scw 	bus_space_tag_t sc_bust;
     81        1.1       scw 	bus_dma_tag_t sc_dmat;
     82        1.1       scw 	bus_space_handle_t sc_bush;
     83        1.1       scw 	void *sc_irqcookie;
     84        1.1       scw 	int sc_in_reset;
     85        1.1       scw 	u_int sc_dac_rate;
     86        1.1       scw 	u_int sc_adc_rate;
     87        1.1       scw 
     88        1.1       scw 	/* List of DMA ring-buffers allocated by acu_malloc() */
     89        1.1       scw 	struct acu_dma *sc_dmas;
     90        1.1       scw 
     91        1.1       scw 	/* Dummy DMA segment which points to the AC97 PCM Fifo register */
     92        1.1       scw 	bus_dma_segment_t sc_dr;
     93        1.1       scw 
     94        1.1       scw 	/* PCM Output (Tx) state */
     95        1.1       scw 	dmac_peripheral_t sc_txp;
     96        1.1       scw 	struct acu_dma *sc_txdma;
     97        1.1       scw 	void (*sc_txfunc)(void *);
     98        1.1       scw 	void *sc_txarg;
     99        1.1       scw 
    100        1.1       scw 	/* PCM Input (Rx) state */
    101        1.1       scw 	dmac_peripheral_t sc_rxp;
    102        1.1       scw 	struct acu_dma *sc_rxdma;
    103        1.1       scw 	void (*sc_rxfunc)(void *);
    104        1.1       scw 	void *sc_rxarg;
    105        1.1       scw 
    106        1.1       scw 	/* AC97 Codec State */
    107        1.1       scw 	struct ac97_codec_if *sc_codec_if;
    108        1.1       scw 	struct ac97_host_if sc_host_if;
    109        1.1       scw 
    110        1.1       scw 	/* Child audio(4) device */
    111       1.12       chs 	device_t sc_audiodev;
    112        1.1       scw 
    113        1.1       scw 	/* auconv encodings */
    114        1.1       scw 	struct audio_encoding_set *sc_encodings;
    115       1.10  jmcneill 
    116       1.10  jmcneill 	/* MPSAFE interfaces */
    117       1.10  jmcneill 	kmutex_t sc_lock;
    118       1.10  jmcneill 	kmutex_t sc_intr_lock;
    119        1.1       scw };
    120        1.1       scw 
    121        1.8    nonaka static int	pxaacu_match(device_t, cfdata_t, void *);
    122        1.8    nonaka static void	pxaacu_attach(device_t, device_t, void *);
    123        1.1       scw 
    124        1.8    nonaka CFATTACH_DECL_NEW(pxaacu, sizeof(struct acu_softc),
    125        1.1       scw     pxaacu_match, pxaacu_attach, NULL, NULL);
    126        1.1       scw 
    127        1.1       scw static int acu_codec_attach(void *, struct ac97_codec_if *);
    128       1.13     skrll static int acu_codec_read(void *, uint8_t, uint16_t *);
    129       1.13     skrll static int acu_codec_write(void *, uint8_t, uint16_t);
    130        1.1       scw static int acu_codec_reset(void *);
    131        1.1       scw static int acu_intr(void *);
    132        1.1       scw 
    133        1.1       scw static int acu_open(void *, int);
    134        1.1       scw static void acu_close(void *);
    135        1.1       scw static int acu_query_encoding(void *, struct audio_encoding *);
    136        1.1       scw static int acu_set_params(void *, int, int, audio_params_t *, audio_params_t *,
    137        1.1       scw 	    stream_filter_list_t *, stream_filter_list_t *);
    138        1.1       scw static int acu_round_blocksize(void *, int, int, const audio_params_t *);
    139        1.1       scw static int acu_halt_output(void *);
    140        1.1       scw static int acu_halt_input(void *);
    141        1.1       scw static int acu_trigger_output(void *, void *, void *, int, void (*)(void *),
    142        1.1       scw 	    void *, const audio_params_t *);
    143        1.1       scw static int acu_trigger_input(void *, void *, void *, int, void (*)(void *),
    144        1.1       scw 	    void *, const audio_params_t *);
    145        1.1       scw static void acu_tx_loop_segment(struct dmac_xfer *, int);
    146        1.1       scw static void acu_rx_loop_segment(struct dmac_xfer *, int);
    147        1.1       scw static int acu_getdev(void *, struct audio_device *);
    148        1.1       scw static int acu_mixer_set_port(void *, mixer_ctrl_t *);
    149        1.1       scw static int acu_mixer_get_port(void *, mixer_ctrl_t *);
    150        1.1       scw static int acu_query_devinfo(void *, mixer_devinfo_t *);
    151       1.10  jmcneill static void *acu_malloc(void *, int, size_t);
    152       1.10  jmcneill static void acu_free(void *, void *, size_t);
    153        1.1       scw static size_t acu_round_buffersize(void *, int, size_t);
    154        1.1       scw static paddr_t acu_mappage(void *, void *, off_t, int);
    155        1.1       scw static int acu_get_props(void *);
    156       1.10  jmcneill static void acu_get_locks(void *, kmutex_t **, kmutex_t **);
    157        1.1       scw 
    158        1.1       scw struct audio_hw_if acu_hw_if = {
    159        1.1       scw 	acu_open,
    160        1.1       scw 	acu_close,
    161        1.1       scw 	NULL,
    162        1.1       scw 	acu_query_encoding,
    163        1.1       scw 	acu_set_params,
    164        1.1       scw 	acu_round_blocksize,
    165        1.1       scw 	NULL,
    166        1.1       scw 	NULL,
    167        1.1       scw 	NULL,
    168        1.1       scw 	NULL,
    169        1.1       scw 	NULL,
    170        1.1       scw 	acu_halt_output,
    171        1.1       scw 	acu_halt_input,
    172        1.1       scw 	NULL,
    173        1.1       scw 	acu_getdev,
    174        1.1       scw 	NULL,
    175        1.1       scw 	acu_mixer_set_port,
    176        1.1       scw 	acu_mixer_get_port,
    177        1.1       scw 	acu_query_devinfo,
    178        1.1       scw 	acu_malloc,
    179        1.1       scw 	acu_free,
    180        1.1       scw 	acu_round_buffersize,
    181        1.1       scw 	acu_mappage,
    182        1.1       scw 	acu_get_props,
    183        1.1       scw 	acu_trigger_output,
    184        1.1       scw 	acu_trigger_input,
    185        1.1       scw 	NULL,
    186       1.10  jmcneill 	acu_get_locks,
    187        1.1       scw };
    188        1.1       scw 
    189        1.1       scw struct audio_device acu_device = {
    190        1.1       scw 	"PXA250 AC97",
    191        1.1       scw 	"",
    192        1.1       scw 	"acu"
    193        1.1       scw };
    194        1.1       scw 
    195        1.1       scw static const struct audio_format acu_formats[] = {
    196        1.1       scw 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
    197        1.1       scw 	 2, AUFMT_STEREO, 0, {4000, 48000}}
    198        1.1       scw };
    199        1.1       scw #define	ACU_NFORMATS	(sizeof(acu_formats) / sizeof(struct audio_format))
    200        1.1       scw 
    201       1.13     skrll static inline uint32_t
    202        1.1       scw acu_reg_read(struct acu_softc *sc, int reg)
    203        1.1       scw {
    204        1.1       scw 
    205        1.1       scw 	return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));
    206        1.1       scw }
    207        1.1       scw 
    208        1.3     perry static inline void
    209       1.13     skrll acu_reg_write(struct acu_softc *sc, int reg, uint32_t val)
    210        1.1       scw {
    211        1.1       scw 
    212        1.1       scw 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
    213        1.1       scw }
    214        1.1       scw 
    215        1.3     perry static inline int
    216        1.1       scw acu_codec_ready(struct acu_softc *sc)
    217        1.1       scw {
    218        1.1       scw 
    219        1.1       scw 	return (acu_reg_read(sc, AC97_GSR) & GSR_PCR);
    220        1.1       scw }
    221        1.1       scw 
    222        1.3     perry static inline int
    223       1.13     skrll acu_wait_gsr(struct acu_softc *sc, uint32_t bit)
    224        1.1       scw {
    225        1.1       scw 	int timeout;
    226       1.13     skrll 	uint32_t rv;
    227        1.1       scw 
    228        1.1       scw 	for (timeout = 5000; timeout; timeout--) {
    229        1.1       scw 		if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) {
    230        1.1       scw 			acu_reg_write(sc, AC97_GSR, rv | bit);
    231        1.1       scw 			return (0);
    232        1.1       scw 		}
    233        1.1       scw 		delay(1);
    234        1.1       scw 	}
    235        1.1       scw 
    236        1.1       scw 	return (1);
    237        1.1       scw }
    238        1.1       scw 
    239        1.1       scw static int
    240        1.8    nonaka pxaacu_match(device_t parent, cfdata_t cf, void *aux)
    241        1.1       scw {
    242        1.1       scw 	struct pxaip_attach_args *pxa = aux;
    243        1.6  kiyohara 	struct pxa2x0_gpioconf *gpioconf;
    244        1.6  kiyohara 	u_int gpio;
    245        1.6  kiyohara 	int i;
    246        1.1       scw 
    247        1.1       scw 	if (pxa->pxa_addr != PXA2X0_AC97_BASE ||
    248        1.1       scw 	    pxa->pxa_intr != PXA2X0_INT_AC97)
    249        1.1       scw 		return (0);
    250        1.1       scw 
    251        1.6  kiyohara 	gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf :
    252        1.6  kiyohara 	    pxa27x_pxaacu_gpioconf;
    253        1.6  kiyohara 	for (i = 0; gpioconf[i].pin != -1; i++) {
    254        1.6  kiyohara 		gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
    255        1.6  kiyohara 		if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
    256        1.6  kiyohara 		    GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
    257        1.6  kiyohara 			return (0);
    258        1.6  kiyohara 	}
    259        1.6  kiyohara 
    260        1.1       scw 	pxa->pxa_size = PXA2X0_AC97_SIZE;
    261        1.1       scw 
    262        1.1       scw 	return (1);
    263        1.1       scw }
    264        1.1       scw 
    265        1.1       scw static void
    266        1.8    nonaka pxaacu_attach(device_t parent, device_t self, void *aux)
    267        1.1       scw {
    268        1.8    nonaka 	struct acu_softc *sc = device_private(self);
    269        1.1       scw 	struct pxaip_attach_args *pxa = aux;
    270        1.1       scw 
    271        1.8    nonaka 	sc->sc_dev = self;
    272        1.1       scw 	sc->sc_bust = pxa->pxa_iot;
    273        1.1       scw 	sc->sc_dmat = pxa->pxa_dmat;
    274        1.1       scw 
    275        1.1       scw 	aprint_naive("\n");
    276        1.1       scw 	aprint_normal(": AC97 Controller\n");
    277        1.1       scw 
    278        1.1       scw 	if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0,
    279        1.1       scw 	    &sc->sc_bush)) {
    280        1.8    nonaka 		aprint_error_dev(self, "Can't map registers!\n");
    281        1.1       scw 		return;
    282        1.1       scw 	}
    283        1.1       scw 
    284       1.11       mrg 	sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO,
    285        1.1       scw 	    acu_intr, sc);
    286        1.1       scw 	KASSERT(sc->sc_irqcookie != NULL);
    287        1.1       scw 
    288        1.1       scw 	/* Make sure the AC97 clock is enabled */
    289        1.4   thorpej 	pxa2x0_clkman_config(CKEN_AC97, true);
    290        1.1       scw 	delay(100);
    291        1.1       scw 
    292        1.1       scw 	/* Do a cold reset */
    293        1.1       scw 	acu_reg_write(sc, AC97_GCR, 0);
    294        1.1       scw 	delay(100);
    295        1.1       scw 	acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
    296        1.1       scw 	delay(100);
    297        1.1       scw 	acu_reg_write(sc, AC97_CAR, 0);
    298        1.1       scw 
    299        1.1       scw 	if (acu_wait_gsr(sc, GSR_PCR)) {
    300        1.1       scw 		acu_reg_write(sc, AC97_GCR, 0);
    301        1.1       scw 		delay(100);
    302        1.4   thorpej 		pxa2x0_clkman_config(CKEN_AC97, false);
    303        1.1       scw 		bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
    304        1.8    nonaka 		aprint_error_dev(self, "Primary codec not ready\n");
    305        1.1       scw 		return;
    306        1.1       scw 	}
    307        1.1       scw 
    308        1.1       scw 	sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR;
    309        1.1       scw 	sc->sc_dr.ds_len = 4;
    310        1.1       scw 
    311        1.1       scw 	sc->sc_codec_if = NULL;
    312        1.1       scw 	sc->sc_host_if.arg = sc;
    313        1.1       scw 	sc->sc_host_if.attach = acu_codec_attach;
    314        1.1       scw 	sc->sc_host_if.read = acu_codec_read;
    315        1.1       scw 	sc->sc_host_if.write = acu_codec_write;
    316        1.1       scw 	sc->sc_host_if.reset = acu_codec_reset;
    317        1.1       scw 	sc->sc_host_if.flags = NULL;
    318        1.1       scw 	sc->sc_in_reset = 0;
    319        1.1       scw 	sc->sc_dac_rate = sc->sc_adc_rate = 0;
    320        1.1       scw 
    321       1.10  jmcneill 	if (ac97_attach(&sc->sc_host_if, sc->sc_dev, &sc->sc_lock)) {
    322        1.8    nonaka 		aprint_error_dev(self, "Failed to attach primary codec\n");
    323        1.1       scw  fail:
    324        1.1       scw 		acu_reg_write(sc, AC97_GCR, 0);
    325        1.1       scw 		delay(100);
    326        1.4   thorpej 		pxa2x0_clkman_config(CKEN_AC97, false);
    327        1.1       scw 		bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
    328        1.1       scw 		return;
    329        1.1       scw 	}
    330        1.1       scw 
    331        1.1       scw 	if (auconv_create_encodings(acu_formats, ACU_NFORMATS,
    332        1.1       scw 	    &sc->sc_encodings)) {
    333        1.8    nonaka 		aprint_error_dev(self, "Failed to create encodings\n");
    334        1.1       scw 		if (sc->sc_codec_if != NULL)
    335        1.1       scw 			(sc->sc_codec_if->vtbl->detach)(sc->sc_codec_if);
    336        1.1       scw 		goto fail;
    337        1.1       scw 	}
    338        1.1       scw 
    339        1.8    nonaka 	sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, sc->sc_dev);
    340        1.1       scw 
    341        1.1       scw 	/*
    342        1.1       scw 	 * As a work-around for braindamage in the PXA250's AC97 controller
    343        1.1       scw 	 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until
    344        1.1       scw 	 * acu_open() is called. acu_close() also puts the controller into
    345        1.1       scw 	 * Cold Reset.
    346        1.1       scw 	 *
    347        1.1       scw 	 * While this won't necessarily prevent Rx FIFO overruns, it at least
    348        1.1       scw 	 * allows the user to recover by closing then re-opening the audio
    349        1.1       scw 	 * device.
    350        1.1       scw 	 */
    351        1.1       scw 	acu_reg_write(sc, AC97_GCR, 0);
    352        1.1       scw 	sc->sc_in_reset = 1;
    353        1.1       scw }
    354        1.1       scw 
    355        1.1       scw static int
    356        1.1       scw acu_codec_attach(void *arg, struct ac97_codec_if *aci)
    357        1.1       scw {
    358        1.1       scw 	struct acu_softc *sc = arg;
    359        1.1       scw 
    360        1.1       scw 	sc->sc_codec_if = aci;
    361        1.1       scw 	return (0);
    362        1.1       scw }
    363        1.1       scw 
    364        1.1       scw static int
    365       1.13     skrll acu_codec_read(void *arg, uint8_t codec_reg, uint16_t *valp)
    366        1.1       scw {
    367        1.1       scw 	struct acu_softc *sc = arg;
    368       1.13     skrll 	uint32_t val;
    369       1.10  jmcneill 	int reg, rv = 1;
    370        1.1       scw 
    371        1.1       scw 	/*
    372        1.1       scw 	 * If we're currently closed, return non-zero. The ac97 frontend
    373        1.1       scw 	 * will use its cached copy of the register instead.
    374        1.1       scw 	 */
    375        1.1       scw 	if (sc->sc_in_reset)
    376        1.1       scw 		return (1);
    377        1.1       scw 
    378        1.1       scw 	reg = AC97_CODEC_BASE(0) + codec_reg * 2;
    379        1.1       scw 
    380       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    381        1.1       scw 
    382        1.1       scw 	if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP))
    383        1.1       scw 		goto out_nocar;
    384        1.1       scw 
    385        1.1       scw 	val = acu_reg_read(sc, AC97_GSR);
    386        1.1       scw 	val |= GSR_RDCS | GSR_SDONE;
    387        1.1       scw 	acu_reg_write(sc, AC97_GSR, val);
    388        1.1       scw 
    389        1.1       scw 	/*
    390        1.1       scw 	 * Dummy read to initiate the real read access
    391        1.1       scw 	 */
    392        1.1       scw 	(void) acu_reg_read(sc, reg);
    393        1.1       scw 	if (acu_wait_gsr(sc, GSR_SDONE))
    394        1.1       scw 		goto out;
    395        1.1       scw 
    396        1.1       scw 	(void) acu_reg_read(sc, reg);
    397        1.1       scw 	if (acu_wait_gsr(sc, GSR_SDONE))
    398        1.1       scw 		goto out;
    399        1.1       scw 
    400        1.1       scw 	val = acu_reg_read(sc, AC97_GSR);
    401        1.1       scw 	if (val & GSR_RDCS)
    402        1.1       scw 		goto out;
    403        1.1       scw 
    404        1.1       scw 	*valp = acu_reg_read(sc, reg);
    405        1.1       scw 	if (acu_wait_gsr(sc, GSR_SDONE))
    406        1.1       scw 		goto out;
    407        1.1       scw 
    408        1.1       scw 	rv = 0;
    409        1.1       scw 
    410        1.1       scw out:
    411        1.1       scw 	acu_reg_write(sc, AC97_CAR, 0);
    412        1.1       scw out_nocar:
    413       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    414        1.1       scw 	delay(10);
    415        1.1       scw 	return (rv);
    416        1.1       scw }
    417        1.1       scw 
    418        1.1       scw static int
    419       1.13     skrll acu_codec_write(void *arg, uint8_t codec_reg, uint16_t val)
    420        1.1       scw {
    421        1.1       scw 	struct acu_softc *sc = arg;
    422       1.13     skrll 	uint16_t rv;
    423        1.1       scw 
    424        1.1       scw 	/*
    425        1.1       scw 	 * If we're currently closed, chances are the user is just
    426        1.1       scw 	 * tweaking mixer settings. Pretend the write succeeded.
    427        1.1       scw 	 * The ac97 frontend will cache the value anyway, and it'll
    428        1.1       scw 	 * be written correctly when the driver is opened.
    429        1.1       scw 	 */
    430        1.1       scw 	if (sc->sc_in_reset)
    431        1.1       scw 		return (0);
    432        1.1       scw 
    433       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    434        1.1       scw 
    435        1.1       scw 	if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) {
    436       1.10  jmcneill 		mutex_spin_exit(&sc->sc_intr_lock);
    437        1.1       scw 		return (1);
    438        1.1       scw 	}
    439        1.1       scw 
    440        1.1       scw 	rv = acu_reg_read(sc, AC97_GSR);
    441        1.1       scw 	rv |= GSR_RDCS | GSR_CDONE;
    442        1.1       scw 	acu_reg_write(sc, AC97_GSR, rv);
    443        1.1       scw 
    444        1.1       scw 	acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val);
    445        1.1       scw 
    446        1.1       scw 	/*
    447        1.1       scw 	 * Wait for the write to complete
    448        1.1       scw 	 */
    449        1.1       scw 	(void) acu_wait_gsr(sc, GSR_CDONE);
    450        1.1       scw 	acu_reg_write(sc, AC97_CAR, 0);
    451        1.1       scw 
    452       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    453        1.1       scw 	delay(10);
    454        1.1       scw 	return (0);
    455        1.1       scw }
    456        1.1       scw 
    457        1.1       scw static int
    458        1.1       scw acu_codec_reset(void *arg)
    459        1.1       scw {
    460        1.1       scw 	struct acu_softc *sc = arg;
    461       1.13     skrll 	uint32_t rv;
    462        1.1       scw 
    463        1.1       scw 	rv = acu_reg_read(sc, AC97_GCR);
    464        1.1       scw 	acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST);
    465        1.1       scw 	delay(100);
    466        1.1       scw 	acu_reg_write(sc, AC97_GCR, rv);
    467        1.1       scw 	delay(100);
    468        1.1       scw 
    469        1.1       scw 	if (acu_wait_gsr(sc, GSR_PCR)) {
    470        1.8    nonaka 		aprint_error_dev(sc->sc_dev,
    471        1.8    nonaka 		    "acu_codec_reset: failed to ready after reset\n");
    472        1.1       scw 		return (ETIMEDOUT);
    473        1.1       scw 	}
    474        1.1       scw 
    475        1.1       scw 	return (0);
    476        1.1       scw }
    477        1.1       scw 
    478        1.1       scw static int
    479        1.1       scw acu_intr(void *arg)
    480        1.1       scw {
    481        1.1       scw 	struct acu_softc *sc = arg;
    482       1.13     skrll 	uint32_t gsr, reg;
    483        1.1       scw 
    484       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    485        1.1       scw 	gsr = acu_reg_read(sc, AC97_GSR);
    486        1.1       scw 
    487        1.1       scw 	/*
    488        1.1       scw 	 * Tx FIFO underruns are no big deal. Just log it and ignore and
    489        1.1       scw 	 * subsequent underruns until the next time acu_trigger_output()
    490        1.1       scw 	 * is called.
    491        1.1       scw 	 */
    492        1.1       scw 	if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) {
    493        1.1       scw 		acu_reg_write(sc, AC97_POCR, 0);
    494        1.1       scw 		reg = acu_reg_read(sc, AC97_POSR);
    495        1.1       scw 		acu_reg_write(sc, AC97_POSR, reg);
    496        1.8    nonaka 		aprint_error_dev(sc->sc_dev, "Tx PCM Fifo underrun\n");
    497        1.1       scw 	}
    498        1.1       scw 
    499        1.1       scw 	/*
    500        1.1       scw 	 * Rx FIFO overruns are a different story. See PAX250 Errata #125
    501        1.1       scw 	 * for the gory details.
    502        1.1       scw 	 * I don't see any way to gracefully recover from this problem,
    503        1.1       scw 	 * other than a issuing a Cold Reset in acu_close().
    504        1.1       scw 	 * The best we can do here is to report the problem on the console.
    505        1.1       scw 	 */
    506        1.1       scw 	if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) {
    507        1.1       scw 		acu_reg_write(sc, AC97_PICR, 0);
    508        1.1       scw 		reg = acu_reg_read(sc, AC97_PISR);
    509        1.1       scw 		acu_reg_write(sc, AC97_PISR, reg);
    510        1.8    nonaka 		aprint_error_dev(sc->sc_dev, "Rx PCM Fifo overrun\n");
    511        1.1       scw 	}
    512        1.1       scw 
    513       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    514       1.10  jmcneill 
    515        1.1       scw 	return (1);
    516        1.1       scw }
    517        1.1       scw 
    518        1.1       scw static int
    519        1.1       scw acu_open(void *arg, int flags)
    520        1.1       scw {
    521        1.1       scw 	struct acu_softc *sc = arg;
    522        1.1       scw 
    523        1.1       scw 	/*
    524        1.1       scw 	 * Deassert Cold Reset
    525        1.1       scw 	 */
    526        1.1       scw 	acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
    527        1.1       scw 	delay(100);
    528        1.1       scw 	acu_reg_write(sc, AC97_CAR, 0);
    529        1.1       scw 
    530        1.1       scw 	/*
    531        1.1       scw 	 * Wait for the primary codec to become ready
    532        1.1       scw 	 */
    533        1.1       scw 	if (acu_wait_gsr(sc, GSR_PCR))
    534        1.1       scw 		return (EIO);
    535        1.1       scw 	sc->sc_in_reset = 0;
    536        1.1       scw 
    537        1.1       scw 	/*
    538        1.1       scw 	 * Restore the codec port settings
    539        1.1       scw 	 */
    540        1.1       scw 	sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if);
    541        1.1       scw 
    542        1.1       scw 	/*
    543        1.1       scw 	 * Need to reprogram the sample rates, since 'restore_ports'
    544        1.1       scw 	 * doesn't do it.
    545        1.1       scw 	 *
    546        1.1       scw 	 * XXX: These aren't the only two sample rate registers ...
    547        1.1       scw 	 */
    548        1.1       scw 	if (sc->sc_dac_rate)
    549        1.1       scw 		(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    550        1.1       scw 		    AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate);
    551        1.1       scw 	if (sc->sc_adc_rate)
    552        1.1       scw 		(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    553        1.1       scw 		    AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate);
    554        1.1       scw 
    555        1.1       scw 	return (0);
    556        1.1       scw }
    557        1.1       scw 
    558        1.1       scw static void
    559        1.1       scw acu_close(void *arg)
    560        1.1       scw {
    561        1.1       scw 	struct acu_softc *sc = arg;
    562        1.1       scw 
    563        1.1       scw 	/*
    564        1.1       scw 	 * Make sure the hardware is quiescent
    565        1.1       scw 	 */
    566        1.1       scw 	acu_halt_output(sc);
    567        1.1       scw 	acu_halt_input(sc);
    568        1.1       scw 	delay(100);
    569        1.1       scw 
    570        1.1       scw 	/* Assert Cold Reset */
    571        1.1       scw 	acu_reg_write(sc, AC97_GCR, 0);
    572        1.1       scw 	sc->sc_in_reset = 1;
    573        1.1       scw }
    574        1.1       scw 
    575        1.1       scw static int
    576        1.1       scw acu_query_encoding(void *arg, struct audio_encoding *fp)
    577        1.1       scw {
    578        1.1       scw 	struct acu_softc *sc = arg;
    579        1.1       scw 
    580        1.1       scw 	return (auconv_query_encoding(sc->sc_encodings, fp));
    581        1.1       scw }
    582        1.1       scw 
    583        1.1       scw static int
    584        1.1       scw acu_set_params(void *arg, int setmode, int usemode,
    585        1.1       scw     audio_params_t *play, audio_params_t *rec,
    586        1.1       scw     stream_filter_list_t *pfil, stream_filter_list_t *rfil)
    587        1.1       scw {
    588        1.1       scw 	struct acu_softc *sc = arg;
    589        1.1       scw 	struct audio_params *p;
    590        1.1       scw 	stream_filter_list_t *fil;
    591        1.1       scw 	int mode, err;
    592        1.1       scw 
    593        1.1       scw 	for (mode = AUMODE_RECORD; mode != -1;
    594        1.1       scw 	    mode = (mode == AUMODE_RECORD) ? AUMODE_PLAY : -1) {
    595        1.1       scw 		if ((setmode & mode) == 0)
    596        1.1       scw 			continue;
    597        1.1       scw 
    598        1.1       scw 		p = (mode == AUMODE_PLAY) ? play : rec;
    599        1.1       scw 
    600        1.1       scw 		if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
    601        1.1       scw 		    (p->precision != 8 && p->precision != 16) ||
    602        1.1       scw 		    (p->channels != 1 && p->channels != 2)) {
    603        1.1       scw 			printf("acu_set_params: precision/channels botch\n");
    604        1.1       scw 			printf("acu_set_params: rate %d, prec %d, chan %d\n",
    605        1.1       scw 			    p->sample_rate, p->precision, p->channels);
    606        1.1       scw 			return (EINVAL);
    607        1.1       scw 		}
    608        1.1       scw 
    609        1.1       scw 		fil = (mode == AUMODE_PLAY) ? pfil : rfil;
    610        1.1       scw 		err = auconv_set_converter(acu_formats, ACU_NFORMATS,
    611        1.4   thorpej 		    mode, p, true, fil);
    612        1.1       scw 		if (err < 0)
    613        1.1       scw 			return (EINVAL);
    614        1.1       scw 
    615        1.1       scw 		if (mode == AUMODE_PLAY) {
    616        1.1       scw 			err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    617        1.1       scw 			    AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate);
    618        1.1       scw 			sc->sc_dac_rate = play->sample_rate;
    619        1.1       scw 		} else {
    620        1.1       scw 			err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    621        1.1       scw 			    AC97_REG_PCM_LR_ADC_RATE, &rec->sample_rate);
    622        1.1       scw 			sc->sc_adc_rate = rec->sample_rate;
    623        1.1       scw 		}
    624        1.1       scw 		if (err)
    625        1.1       scw 			return (EINVAL);
    626        1.1       scw 	}
    627        1.1       scw 
    628        1.1       scw 	return (0);
    629        1.1       scw }
    630        1.1       scw 
    631        1.1       scw static int
    632        1.1       scw acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param)
    633        1.1       scw {
    634        1.1       scw 
    635        1.1       scw 	return (blk & ~0x1f);
    636        1.1       scw }
    637        1.1       scw 
    638        1.1       scw static int
    639        1.1       scw acu_getdev(void *addr, struct audio_device *retp)
    640        1.1       scw {
    641        1.1       scw 
    642        1.1       scw 	*retp = acu_device;
    643        1.1       scw 	return (0);
    644        1.1       scw }
    645        1.1       scw 
    646        1.1       scw static int
    647        1.1       scw acu_mixer_set_port(void *arg, mixer_ctrl_t *cp)
    648        1.1       scw {
    649        1.1       scw 	struct acu_softc *sc = arg;
    650        1.1       scw 
    651        1.1       scw 	return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp));
    652        1.1       scw }
    653        1.1       scw 
    654        1.1       scw static int
    655        1.1       scw acu_mixer_get_port(void *arg, mixer_ctrl_t *cp)
    656        1.1       scw {
    657        1.1       scw 	struct acu_softc *sc = arg;
    658        1.1       scw 
    659        1.1       scw 	return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp));
    660        1.1       scw }
    661        1.1       scw 
    662        1.1       scw static int
    663        1.1       scw acu_query_devinfo(void *arg, mixer_devinfo_t *dip)
    664        1.1       scw {
    665        1.1       scw 	struct acu_softc *sc = arg;
    666        1.1       scw 
    667        1.1       scw 	return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip));
    668        1.1       scw }
    669        1.1       scw 
    670        1.1       scw static void *
    671       1.10  jmcneill acu_malloc(void *arg, int direction, size_t size)
    672        1.1       scw {
    673        1.1       scw 	struct acu_softc *sc = arg;
    674        1.1       scw 	struct acu_dma *ad;
    675        1.1       scw 	int error;
    676        1.1       scw 
    677  1.13.14.1     skrll 	ad = kmem_alloc(sizeof(*ad), KM_SLEEP);
    678        1.1       scw 
    679       1.10  jmcneill 	/* XXX */
    680       1.10  jmcneill 	if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer()) == NULL)
    681        1.1       scw 		goto error;
    682        1.1       scw 
    683        1.1       scw 	ad->ad_size = size;
    684        1.1       scw 
    685        1.1       scw 	error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs,
    686       1.10  jmcneill 	    ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_WAITOK);
    687        1.1       scw 	if (error)
    688        1.1       scw 		goto free_xfer;
    689        1.1       scw 
    690        1.1       scw 	error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size,
    691       1.10  jmcneill 	    &ad->ad_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
    692        1.1       scw 	if (error)
    693        1.1       scw 		goto free_dmamem;
    694        1.1       scw 
    695        1.1       scw 	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
    696       1.10  jmcneill 	    BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ad->ad_map);
    697        1.1       scw 	if (error)
    698        1.1       scw 		goto unmap_dmamem;
    699        1.1       scw 
    700        1.1       scw 	error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size,
    701       1.10  jmcneill 	    NULL, BUS_DMA_WAITOK);
    702        1.1       scw 	if (error) {
    703        1.1       scw 		bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
    704        1.1       scw unmap_dmamem:	bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size);
    705        1.1       scw free_dmamem:	bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
    706        1.1       scw free_xfer:	pxa2x0_dmac_free_xfer(ad->ad_dx);
    707       1.10  jmcneill error:		kmem_free(ad, sizeof(*ad));
    708        1.1       scw 		return (NULL);
    709        1.1       scw 	}
    710        1.1       scw 
    711        1.1       scw 	ad->ad_dx->dx_cookie = sc;
    712        1.1       scw 	ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH;
    713        1.1       scw 	ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4;
    714        1.1       scw 	ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32;
    715        1.1       scw 
    716        1.1       scw 	ad->ad_next = sc->sc_dmas;
    717        1.1       scw 	sc->sc_dmas = ad;
    718        1.1       scw 	return (KERNADDR(ad));
    719        1.1       scw }
    720        1.1       scw 
    721        1.1       scw static void
    722       1.10  jmcneill acu_free(void *arg, void *ptr, size_t size)
    723        1.1       scw {
    724        1.1       scw 	struct acu_softc *sc = arg;
    725        1.1       scw 	struct acu_dma *ad, **adp;
    726        1.1       scw 
    727        1.1       scw 	for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) {
    728        1.1       scw 		if (KERNADDR(ad) == ptr) {
    729        1.1       scw 			pxa2x0_dmac_abort_xfer(ad->ad_dx);
    730        1.1       scw 			pxa2x0_dmac_free_xfer(ad->ad_dx);
    731        1.1       scw 			ad->ad_segs[0].ds_len = ad->ad_size;	/* XXX */
    732        1.1       scw 			bus_dmamap_unload(sc->sc_dmat, ad->ad_map);
    733        1.1       scw 			bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
    734        1.1       scw 			bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size);
    735        1.1       scw 			bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
    736        1.1       scw 			*adp = ad->ad_next;
    737       1.10  jmcneill 			kmem_free(ad, sizeof(*ad));
    738        1.1       scw 			return;
    739        1.1       scw 		}
    740        1.1       scw 	}
    741        1.1       scw }
    742        1.1       scw 
    743        1.1       scw static size_t
    744        1.1       scw acu_round_buffersize(void *arg, int direction, size_t size)
    745        1.1       scw {
    746        1.1       scw 
    747        1.1       scw 	return (size);
    748        1.1       scw }
    749        1.1       scw 
    750        1.1       scw static paddr_t
    751        1.1       scw acu_mappage(void *arg, void *mem, off_t off, int prot)
    752        1.1       scw {
    753        1.1       scw 	struct acu_softc *sc = arg;
    754        1.1       scw 	struct acu_dma *ad;
    755        1.1       scw 
    756        1.1       scw 	if (off < 0)
    757        1.1       scw 		return (-1);
    758        1.1       scw 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != mem; ad = ad->ad_next)
    759        1.1       scw 		;
    760        1.1       scw 	if (ad == NULL)
    761        1.1       scw 		return (-1);
    762        1.1       scw 	return (bus_dmamem_mmap(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs,
    763        1.1       scw 	    off, prot, BUS_DMA_WAITOK));
    764        1.1       scw }
    765        1.1       scw 
    766        1.1       scw static int
    767        1.1       scw acu_get_props(void *arg)
    768        1.1       scw {
    769        1.1       scw 
    770        1.1       scw 	return (AUDIO_PROP_MMAP|AUDIO_PROP_INDEPENDENT|AUDIO_PROP_FULLDUPLEX);
    771        1.1       scw }
    772        1.1       scw 
    773       1.10  jmcneill static void
    774       1.10  jmcneill acu_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread)
    775       1.10  jmcneill {
    776       1.10  jmcneill 	struct acu_softc *sc = opaque;
    777       1.10  jmcneill 
    778       1.10  jmcneill 	*intr = &sc->sc_intr_lock;
    779       1.10  jmcneill 	*thread = &sc->sc_lock;
    780       1.10  jmcneill }
    781       1.10  jmcneill 
    782        1.1       scw static int
    783        1.1       scw acu_halt_output(void *arg)
    784        1.1       scw {
    785        1.1       scw 	struct acu_softc *sc = arg;
    786        1.1       scw 
    787       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    788        1.1       scw 	if (sc->sc_txdma) {
    789        1.1       scw 		acu_reg_write(sc, AC97_POCR, 0);
    790        1.1       scw 		acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
    791        1.1       scw 		pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx);
    792        1.1       scw 		sc->sc_txdma = NULL;
    793        1.1       scw 	}
    794       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    795        1.1       scw 	return (0);
    796        1.1       scw }
    797        1.1       scw 
    798        1.1       scw static int
    799        1.1       scw acu_halt_input(void *arg)
    800        1.1       scw {
    801        1.1       scw 	struct acu_softc *sc = arg;
    802        1.1       scw 
    803       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    804        1.1       scw 	if (sc->sc_rxdma) {
    805        1.1       scw 		acu_reg_write(sc, AC97_PICR, 0);
    806        1.1       scw 		acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
    807        1.1       scw 		pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx);
    808        1.1       scw 		sc->sc_rxdma = NULL;
    809        1.1       scw 	}
    810       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    811        1.1       scw 	return (0);
    812        1.1       scw }
    813        1.1       scw 
    814        1.1       scw static int
    815        1.1       scw acu_trigger_output(void *arg, void *start, void *end, int blksize,
    816        1.1       scw     void (*tx_func)(void *), void *tx_arg, const audio_params_t *param)
    817        1.1       scw {
    818        1.1       scw 	struct acu_softc *sc = arg;
    819        1.1       scw 	struct dmac_xfer *dx;
    820        1.1       scw 	struct acu_dma *ad;
    821        1.1       scw 	int rv;
    822        1.1       scw 
    823        1.1       scw 	if (sc->sc_txdma)
    824        1.1       scw 		return (EBUSY);
    825        1.1       scw 
    826        1.1       scw 	sc->sc_txfunc = tx_func;
    827        1.1       scw 	sc->sc_txarg = tx_arg;
    828        1.1       scw 
    829        1.1       scw 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
    830        1.1       scw 		;
    831        1.1       scw 	if (ad == NULL) {
    832        1.1       scw 		printf("acu_trigger_output: bad addr %p\n", start);
    833        1.1       scw 		return (EINVAL);
    834        1.1       scw 	}
    835        1.1       scw 
    836        1.1       scw 	sc->sc_txdma = ad;
    837        1.1       scw 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
    838        1.1       scw 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
    839        1.1       scw 
    840        1.1       scw 	/*
    841        1.1       scw 	 * Fix up a looping DMA request.
    842        1.1       scw 	 * The 'done' function will be called for every 'blksize' bytes
    843        1.1       scw 	 * transferred by the DMA engine.
    844        1.1       scw 	 */
    845        1.1       scw 	dx = ad->ad_dx;
    846        1.1       scw 	dx->dx_done = acu_tx_loop_segment;
    847        1.1       scw 	dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX;
    848        1.1       scw 	dx->dx_flow = DMAC_FLOW_CTRL_DEST;
    849        1.1       scw 	dx->dx_loop_notify = blksize;
    850        1.4   thorpej 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
    851        1.1       scw 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
    852        1.1       scw 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
    853        1.4   thorpej 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
    854        1.1       scw 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
    855        1.1       scw 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
    856        1.1       scw 
    857        1.1       scw 	rv = pxa2x0_dmac_start_xfer(dx);
    858        1.1       scw 	if (rv == 0) {
    859        1.1       scw 		/*
    860        1.1       scw 		 * XXX: We should only do this once the request has been
    861        1.1       scw 		 * loaded into a DMAC channel.
    862        1.1       scw 		 */
    863        1.1       scw 		acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
    864        1.1       scw 		acu_reg_write(sc, AC97_POCR, AC97_FEFIE);
    865        1.1       scw 	}
    866        1.1       scw 
    867        1.1       scw 	return (rv);
    868        1.1       scw }
    869        1.1       scw 
    870        1.1       scw static int
    871        1.1       scw acu_trigger_input(void *arg, void *start, void *end, int blksize,
    872        1.1       scw     void (*rx_func)(void *), void *rx_arg, const audio_params_t *param)
    873        1.1       scw {
    874        1.1       scw 	struct acu_softc *sc = arg;
    875        1.1       scw 	struct dmac_xfer *dx;
    876        1.1       scw 	struct acu_dma *ad;
    877        1.1       scw 	int rv;
    878        1.1       scw 
    879        1.1       scw 	if (sc->sc_rxdma)
    880        1.1       scw 		return (EBUSY);
    881        1.1       scw 
    882        1.1       scw 	sc->sc_rxfunc = rx_func;
    883        1.1       scw 	sc->sc_rxarg = rx_arg;
    884        1.1       scw 
    885        1.1       scw 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
    886        1.1       scw 		;
    887        1.1       scw 	if (ad == NULL) {
    888        1.1       scw 		printf("acu_trigger_input: bad addr %p\n", start);
    889        1.1       scw 		return (EINVAL);
    890        1.1       scw 	}
    891        1.1       scw 
    892        1.1       scw 	sc->sc_rxdma = ad;
    893        1.1       scw 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
    894        1.1       scw 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
    895        1.1       scw 
    896        1.1       scw 	/*
    897        1.1       scw 	 * Fix up a looping DMA request.
    898        1.1       scw 	 * The 'done' function will be called for every 'blksize' bytes
    899        1.1       scw 	 * transferred by the DMA engine.
    900        1.1       scw 	 */
    901        1.1       scw 	dx = ad->ad_dx;
    902        1.1       scw 	dx->dx_done = acu_rx_loop_segment;
    903        1.1       scw 	dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX;
    904        1.1       scw 	dx->dx_flow = DMAC_FLOW_CTRL_SRC;
    905        1.1       scw 	dx->dx_loop_notify = blksize;
    906        1.4   thorpej 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
    907        1.1       scw 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
    908        1.1       scw 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
    909        1.4   thorpej 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
    910        1.1       scw 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
    911        1.1       scw 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
    912        1.1       scw 
    913        1.1       scw 	rv = pxa2x0_dmac_start_xfer(dx);
    914        1.1       scw 
    915        1.1       scw 	if (rv == 0) {
    916        1.1       scw 		/*
    917        1.1       scw 		 * XXX: We should only do this once the request has been
    918        1.1       scw 		 * loaded into a DMAC channel.
    919        1.1       scw 		 */
    920        1.1       scw 		acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
    921        1.1       scw 		acu_reg_write(sc, AC97_PICR, AC97_FEFIE);
    922        1.1       scw 	}
    923        1.1       scw 
    924        1.1       scw 	return (rv);
    925        1.1       scw }
    926        1.1       scw 
    927        1.1       scw static void
    928        1.1       scw acu_tx_loop_segment(struct dmac_xfer *dx, int status)
    929        1.1       scw {
    930        1.1       scw 	struct acu_softc *sc = dx->dx_cookie;
    931        1.1       scw 	struct acu_dma *ad;
    932        1.1       scw 
    933        1.1       scw 	if ((ad = sc->sc_txdma) == NULL)
    934        1.1       scw 		panic("acu_tx_loop_segment: bad TX dma descriptor!");
    935        1.1       scw 
    936        1.1       scw 	if (ad->ad_dx != dx)
    937        1.1       scw 		panic("acu_tx_loop_segment: xfer mismatch!");
    938        1.1       scw 
    939        1.1       scw 	if (status) {
    940        1.8    nonaka 		aprint_error_dev(sc->sc_dev,
    941        1.8    nonaka 		    "acu_tx_loop_segment: non-zero completion status %d\n",
    942        1.8    nonaka 		    status);
    943        1.1       scw 	}
    944        1.1       scw 
    945       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    946        1.1       scw 	(sc->sc_txfunc)(sc->sc_txarg);
    947       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    948        1.1       scw }
    949        1.1       scw 
    950        1.1       scw static void
    951        1.1       scw acu_rx_loop_segment(struct dmac_xfer *dx, int status)
    952        1.1       scw {
    953        1.1       scw 	struct acu_softc *sc = dx->dx_cookie;
    954        1.1       scw 	struct acu_dma *ad;
    955        1.1       scw 
    956        1.1       scw 	if ((ad = sc->sc_rxdma) == NULL)
    957        1.1       scw 		panic("acu_rx_loop_segment: bad RX dma descriptor!");
    958        1.1       scw 
    959        1.1       scw 	if (ad->ad_dx != dx)
    960        1.1       scw 		panic("acu_rx_loop_segment: xfer mismatch!");
    961        1.1       scw 
    962        1.1       scw 	if (status) {
    963        1.8    nonaka 		aprint_error_dev(sc->sc_dev,
    964        1.8    nonaka 		    "acu_rx_loop_segment: non-zero completion status %d\n",
    965        1.8    nonaka 		    status);
    966        1.1       scw 	}
    967        1.1       scw 
    968       1.10  jmcneill 	mutex_spin_enter(&sc->sc_intr_lock);
    969        1.1       scw 	(sc->sc_rxfunc)(sc->sc_rxarg);
    970       1.10  jmcneill 	mutex_spin_exit(&sc->sc_intr_lock);
    971        1.1       scw }
    972