pxa2x0_ac97.c revision 1.5
1 /* $NetBSD: pxa2x0_ac97.c,v 1.5 2007/03/04 05:59:38 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2005 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/select.h> 44 #include <sys/audioio.h> 45 46 #include <machine/intr.h> 47 #include <machine/bus.h> 48 49 #include <dev/audio_if.h> 50 #include <dev/audiovar.h> 51 #include <dev/mulaw.h> 52 #include <dev/auconv.h> 53 #include <dev/ic/ac97reg.h> 54 #include <dev/ic/ac97var.h> 55 56 #include <arm/xscale/pxa2x0reg.h> 57 #include <arm/xscale/pxa2x0var.h> 58 #include <arm/xscale/pxa2x0_gpio.h> 59 #include <arm/xscale/pxa2x0_dmac.h> 60 61 #include "locators.h" 62 63 struct acu_dma { 64 bus_dmamap_t ad_map; 65 void *ad_addr; 66 #define ACU_N_SEGS 1 /* XXX: We don't support > 1 */ 67 bus_dma_segment_t ad_segs[ACU_N_SEGS]; 68 int ad_nsegs; 69 size_t ad_size; 70 struct dmac_xfer *ad_dx; 71 struct acu_dma *ad_next; 72 }; 73 74 #define KERNADDR(ad) ((void *)((ad)->ad_addr)) 75 76 struct acu_softc { 77 struct device sc_dev; 78 bus_space_tag_t sc_bust; 79 bus_dma_tag_t sc_dmat; 80 bus_space_handle_t sc_bush; 81 void *sc_irqcookie; 82 int sc_in_reset; 83 u_int sc_dac_rate; 84 u_int sc_adc_rate; 85 86 /* List of DMA ring-buffers allocated by acu_malloc() */ 87 struct acu_dma *sc_dmas; 88 89 /* Dummy DMA segment which points to the AC97 PCM Fifo register */ 90 bus_dma_segment_t sc_dr; 91 92 /* PCM Output (Tx) state */ 93 dmac_peripheral_t sc_txp; 94 struct acu_dma *sc_txdma; 95 void (*sc_txfunc)(void *); 96 void *sc_txarg; 97 98 /* PCM Input (Rx) state */ 99 dmac_peripheral_t sc_rxp; 100 struct acu_dma *sc_rxdma; 101 void (*sc_rxfunc)(void *); 102 void *sc_rxarg; 103 104 /* AC97 Codec State */ 105 struct ac97_codec_if *sc_codec_if; 106 struct ac97_host_if sc_host_if; 107 108 /* Child audio(4) device */ 109 struct device *sc_audiodev; 110 111 /* auconv encodings */ 112 struct audio_encoding_set *sc_encodings; 113 }; 114 115 static int pxaacu_match(struct device *, struct cfdata *, void *); 116 static void pxaacu_attach(struct device *, struct device *, void *); 117 118 CFATTACH_DECL(pxaacu, sizeof(struct acu_softc), 119 pxaacu_match, pxaacu_attach, NULL, NULL); 120 121 static int acu_codec_attach(void *, struct ac97_codec_if *); 122 static int acu_codec_read(void *, u_int8_t, u_int16_t *); 123 static int acu_codec_write(void *, u_int8_t, u_int16_t); 124 static int acu_codec_reset(void *); 125 static int acu_intr(void *); 126 127 static int acu_open(void *, int); 128 static void acu_close(void *); 129 static int acu_query_encoding(void *, struct audio_encoding *); 130 static int acu_set_params(void *, int, int, audio_params_t *, audio_params_t *, 131 stream_filter_list_t *, stream_filter_list_t *); 132 static int acu_round_blocksize(void *, int, int, const audio_params_t *); 133 static int acu_halt_output(void *); 134 static int acu_halt_input(void *); 135 static int acu_trigger_output(void *, void *, void *, int, void (*)(void *), 136 void *, const audio_params_t *); 137 static int acu_trigger_input(void *, void *, void *, int, void (*)(void *), 138 void *, const audio_params_t *); 139 static void acu_tx_loop_segment(struct dmac_xfer *, int); 140 static void acu_rx_loop_segment(struct dmac_xfer *, int); 141 static int acu_getdev(void *, struct audio_device *); 142 static int acu_mixer_set_port(void *, mixer_ctrl_t *); 143 static int acu_mixer_get_port(void *, mixer_ctrl_t *); 144 static int acu_query_devinfo(void *, mixer_devinfo_t *); 145 static void *acu_malloc(void *, int, size_t, struct malloc_type *, int); 146 static void acu_free(void *, void *, struct malloc_type *); 147 static size_t acu_round_buffersize(void *, int, size_t); 148 static paddr_t acu_mappage(void *, void *, off_t, int); 149 static int acu_get_props(void *); 150 151 struct audio_hw_if acu_hw_if = { 152 acu_open, 153 acu_close, 154 NULL, 155 acu_query_encoding, 156 acu_set_params, 157 acu_round_blocksize, 158 NULL, 159 NULL, 160 NULL, 161 NULL, 162 NULL, 163 acu_halt_output, 164 acu_halt_input, 165 NULL, 166 acu_getdev, 167 NULL, 168 acu_mixer_set_port, 169 acu_mixer_get_port, 170 acu_query_devinfo, 171 acu_malloc, 172 acu_free, 173 acu_round_buffersize, 174 acu_mappage, 175 acu_get_props, 176 acu_trigger_output, 177 acu_trigger_input, 178 NULL, 179 }; 180 181 struct audio_device acu_device = { 182 "PXA250 AC97", 183 "", 184 "acu" 185 }; 186 187 static const struct audio_format acu_formats[] = { 188 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 189 2, AUFMT_STEREO, 0, {4000, 48000}} 190 }; 191 #define ACU_NFORMATS (sizeof(acu_formats) / sizeof(struct audio_format)) 192 193 static inline u_int32_t 194 acu_reg_read(struct acu_softc *sc, int reg) 195 { 196 197 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 198 } 199 200 static inline void 201 acu_reg_write(struct acu_softc *sc, int reg, u_int32_t val) 202 { 203 204 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 205 } 206 207 static inline int 208 acu_codec_ready(struct acu_softc *sc) 209 { 210 211 return (acu_reg_read(sc, AC97_GSR) & GSR_PCR); 212 } 213 214 static inline int 215 acu_wait_gsr(struct acu_softc *sc, u_int32_t bit) 216 { 217 int timeout; 218 u_int32_t rv; 219 220 for (timeout = 5000; timeout; timeout--) { 221 if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) { 222 acu_reg_write(sc, AC97_GSR, rv | bit); 223 return (0); 224 } 225 delay(1); 226 } 227 228 return (1); 229 } 230 231 static int 232 pxaacu_match(struct device *parent, struct cfdata *cf, void *aux) 233 { 234 struct pxaip_attach_args *pxa = aux; 235 236 if (pxa->pxa_addr != PXA2X0_AC97_BASE || 237 pxa->pxa_intr != PXA2X0_INT_AC97) 238 return (0); 239 240 pxa->pxa_size = PXA2X0_AC97_SIZE; 241 242 return (1); 243 } 244 245 static void 246 pxaacu_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct acu_softc *sc = (struct acu_softc *)self; 249 struct pxaip_attach_args *pxa = aux; 250 251 sc->sc_bust = pxa->pxa_iot; 252 sc->sc_dmat = pxa->pxa_dmat; 253 254 aprint_naive("\n"); 255 aprint_normal(": AC97 Controller\n"); 256 257 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 258 &sc->sc_bush)) { 259 aprint_error("%s: Can't map registers!\n", sc->sc_dev.dv_xname); 260 return; 261 } 262 263 sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO, 264 acu_intr, sc); 265 KASSERT(sc->sc_irqcookie != NULL); 266 267 /* Make sure the AC97 clock is enabled */ 268 pxa2x0_clkman_config(CKEN_AC97, true); 269 delay(100); 270 pxa2x0_gpio_set_function(31, GPIO_CLR | GPIO_ALT_FN_2_OUT); 271 pxa2x0_gpio_set_function(30, GPIO_CLR | GPIO_ALT_FN_2_OUT); 272 pxa2x0_gpio_set_function(28, GPIO_CLR | GPIO_ALT_FN_1_IN); 273 pxa2x0_gpio_set_function(29, GPIO_CLR | GPIO_ALT_FN_1_IN); 274 delay(100); 275 276 /* Do a cold reset */ 277 acu_reg_write(sc, AC97_GCR, 0); 278 delay(100); 279 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 280 delay(100); 281 acu_reg_write(sc, AC97_CAR, 0); 282 283 if (acu_wait_gsr(sc, GSR_PCR)) { 284 acu_reg_write(sc, AC97_GCR, 0); 285 delay(100); 286 pxa2x0_clkman_config(CKEN_AC97, false); 287 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 288 aprint_error("%s: Primary codec not ready\n", 289 sc->sc_dev.dv_xname); 290 return; 291 } 292 293 sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR; 294 sc->sc_dr.ds_len = 4; 295 296 sc->sc_codec_if = NULL; 297 sc->sc_host_if.arg = sc; 298 sc->sc_host_if.attach = acu_codec_attach; 299 sc->sc_host_if.read = acu_codec_read; 300 sc->sc_host_if.write = acu_codec_write; 301 sc->sc_host_if.reset = acu_codec_reset; 302 sc->sc_host_if.flags = NULL; 303 sc->sc_in_reset = 0; 304 sc->sc_dac_rate = sc->sc_adc_rate = 0; 305 306 if (ac97_attach(&sc->sc_host_if, &sc->sc_dev)) { 307 aprint_error("%s: Failed to attach primary codec\n", 308 sc->sc_dev.dv_xname); 309 fail: 310 acu_reg_write(sc, AC97_GCR, 0); 311 delay(100); 312 pxa2x0_clkman_config(CKEN_AC97, false); 313 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 314 return; 315 } 316 317 if (auconv_create_encodings(acu_formats, ACU_NFORMATS, 318 &sc->sc_encodings)) { 319 aprint_error("%s: Failed to create encodings\n", 320 sc->sc_dev.dv_xname); 321 if (sc->sc_codec_if != NULL) 322 (sc->sc_codec_if->vtbl->detach)(sc->sc_codec_if); 323 goto fail; 324 } 325 326 sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, &sc->sc_dev); 327 328 /* 329 * As a work-around for braindamage in the PXA250's AC97 controller 330 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until 331 * acu_open() is called. acu_close() also puts the controller into 332 * Cold Reset. 333 * 334 * While this won't necessarily prevent Rx FIFO overruns, it at least 335 * allows the user to recover by closing then re-opening the audio 336 * device. 337 */ 338 acu_reg_write(sc, AC97_GCR, 0); 339 sc->sc_in_reset = 1; 340 } 341 342 static int 343 acu_codec_attach(void *arg, struct ac97_codec_if *aci) 344 { 345 struct acu_softc *sc = arg; 346 347 sc->sc_codec_if = aci; 348 return (0); 349 } 350 351 static int 352 acu_codec_read(void *arg, u_int8_t codec_reg, u_int16_t *valp) 353 { 354 struct acu_softc *sc = arg; 355 u_int32_t val; 356 int s, reg, rv = 1; 357 358 /* 359 * If we're currently closed, return non-zero. The ac97 frontend 360 * will use its cached copy of the register instead. 361 */ 362 if (sc->sc_in_reset) 363 return (1); 364 365 reg = AC97_CODEC_BASE(0) + codec_reg * 2; 366 367 s = splaudio(); 368 369 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) 370 goto out_nocar; 371 372 val = acu_reg_read(sc, AC97_GSR); 373 val |= GSR_RDCS | GSR_SDONE; 374 acu_reg_write(sc, AC97_GSR, val); 375 376 /* 377 * Dummy read to initiate the real read access 378 */ 379 (void) acu_reg_read(sc, reg); 380 if (acu_wait_gsr(sc, GSR_SDONE)) 381 goto out; 382 383 (void) acu_reg_read(sc, reg); 384 if (acu_wait_gsr(sc, GSR_SDONE)) 385 goto out; 386 387 val = acu_reg_read(sc, AC97_GSR); 388 if (val & GSR_RDCS) 389 goto out; 390 391 *valp = acu_reg_read(sc, reg); 392 if (acu_wait_gsr(sc, GSR_SDONE)) 393 goto out; 394 395 rv = 0; 396 397 out: 398 acu_reg_write(sc, AC97_CAR, 0); 399 out_nocar: 400 splx(s); 401 delay(10); 402 return (rv); 403 } 404 405 static int 406 acu_codec_write(void *arg, u_int8_t codec_reg, u_int16_t val) 407 { 408 struct acu_softc *sc = arg; 409 u_int16_t rv; 410 int s; 411 412 /* 413 * If we're currently closed, chances are the user is just 414 * tweaking mixer settings. Pretend the write succeeded. 415 * The ac97 frontend will cache the value anyway, and it'll 416 * be written correctly when the driver is opened. 417 */ 418 if (sc->sc_in_reset) 419 return (0); 420 421 s = splaudio(); 422 423 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) { 424 splx(s); 425 return (1); 426 } 427 428 rv = acu_reg_read(sc, AC97_GSR); 429 rv |= GSR_RDCS | GSR_CDONE; 430 acu_reg_write(sc, AC97_GSR, rv); 431 432 acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val); 433 434 /* 435 * Wait for the write to complete 436 */ 437 (void) acu_wait_gsr(sc, GSR_CDONE); 438 acu_reg_write(sc, AC97_CAR, 0); 439 440 splx(s); 441 delay(10); 442 return (0); 443 } 444 445 static int 446 acu_codec_reset(void *arg) 447 { 448 struct acu_softc *sc = arg; 449 u_int32_t rv; 450 451 rv = acu_reg_read(sc, AC97_GCR); 452 acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST); 453 delay(100); 454 acu_reg_write(sc, AC97_GCR, rv); 455 delay(100); 456 457 if (acu_wait_gsr(sc, GSR_PCR)) { 458 printf("%s: acu_codec_reset: failed to ready after reset\n", 459 sc->sc_dev.dv_xname); 460 return (ETIMEDOUT); 461 } 462 463 return (0); 464 } 465 466 static int 467 acu_intr(void *arg) 468 { 469 struct acu_softc *sc = arg; 470 u_int32_t gsr, reg; 471 472 gsr = acu_reg_read(sc, AC97_GSR); 473 474 /* 475 * Tx FIFO underruns are no big deal. Just log it and ignore and 476 * subsequent underruns until the next time acu_trigger_output() 477 * is called. 478 */ 479 if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) { 480 acu_reg_write(sc, AC97_POCR, 0); 481 reg = acu_reg_read(sc, AC97_POSR); 482 acu_reg_write(sc, AC97_POSR, reg); 483 printf("%s: Tx PCM Fifo underrun\n", sc->sc_dev.dv_xname); 484 } 485 486 /* 487 * Rx FIFO overruns are a different story. See PAX250 Errata #125 488 * for the gory details. 489 * I don't see any way to gracefully recover from this problem, 490 * other than a issuing a Cold Reset in acu_close(). 491 * The best we can do here is to report the problem on the console. 492 */ 493 if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) { 494 acu_reg_write(sc, AC97_PICR, 0); 495 reg = acu_reg_read(sc, AC97_PISR); 496 acu_reg_write(sc, AC97_PISR, reg); 497 printf("%s: Rx PCM Fifo overrun\n", sc->sc_dev.dv_xname); 498 } 499 500 return (1); 501 } 502 503 static int 504 acu_open(void *arg, int flags) 505 { 506 struct acu_softc *sc = arg; 507 508 /* 509 * Deassert Cold Reset 510 */ 511 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 512 delay(100); 513 acu_reg_write(sc, AC97_CAR, 0); 514 515 /* 516 * Wait for the primary codec to become ready 517 */ 518 if (acu_wait_gsr(sc, GSR_PCR)) 519 return (EIO); 520 sc->sc_in_reset = 0; 521 522 /* 523 * Restore the codec port settings 524 */ 525 sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if); 526 527 /* 528 * Need to reprogram the sample rates, since 'restore_ports' 529 * doesn't do it. 530 * 531 * XXX: These aren't the only two sample rate registers ... 532 */ 533 if (sc->sc_dac_rate) 534 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 535 AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate); 536 if (sc->sc_adc_rate) 537 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 538 AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate); 539 540 return (0); 541 } 542 543 static void 544 acu_close(void *arg) 545 { 546 struct acu_softc *sc = arg; 547 548 /* 549 * Make sure the hardware is quiescent 550 */ 551 acu_halt_output(sc); 552 acu_halt_input(sc); 553 delay(100); 554 555 /* Assert Cold Reset */ 556 acu_reg_write(sc, AC97_GCR, 0); 557 sc->sc_in_reset = 1; 558 } 559 560 static int 561 acu_query_encoding(void *arg, struct audio_encoding *fp) 562 { 563 struct acu_softc *sc = arg; 564 565 return (auconv_query_encoding(sc->sc_encodings, fp)); 566 } 567 568 static int 569 acu_set_params(void *arg, int setmode, int usemode, 570 audio_params_t *play, audio_params_t *rec, 571 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 572 { 573 struct acu_softc *sc = arg; 574 struct audio_params *p; 575 stream_filter_list_t *fil; 576 int mode, err; 577 578 for (mode = AUMODE_RECORD; mode != -1; 579 mode = (mode == AUMODE_RECORD) ? AUMODE_PLAY : -1) { 580 if ((setmode & mode) == 0) 581 continue; 582 583 p = (mode == AUMODE_PLAY) ? play : rec; 584 585 if (p->sample_rate < 4000 || p->sample_rate > 48000 || 586 (p->precision != 8 && p->precision != 16) || 587 (p->channels != 1 && p->channels != 2)) { 588 printf("acu_set_params: precision/channels botch\n"); 589 printf("acu_set_params: rate %d, prec %d, chan %d\n", 590 p->sample_rate, p->precision, p->channels); 591 return (EINVAL); 592 } 593 594 fil = (mode == AUMODE_PLAY) ? pfil : rfil; 595 err = auconv_set_converter(acu_formats, ACU_NFORMATS, 596 mode, p, true, fil); 597 if (err < 0) 598 return (EINVAL); 599 600 if (mode == AUMODE_PLAY) { 601 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 602 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 603 sc->sc_dac_rate = play->sample_rate; 604 } else { 605 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 606 AC97_REG_PCM_LR_ADC_RATE, &rec->sample_rate); 607 sc->sc_adc_rate = rec->sample_rate; 608 } 609 if (err) 610 return (EINVAL); 611 } 612 613 return (0); 614 } 615 616 static int 617 acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param) 618 { 619 620 return (blk & ~0x1f); 621 } 622 623 static int 624 acu_getdev(void *addr, struct audio_device *retp) 625 { 626 627 *retp = acu_device; 628 return (0); 629 } 630 631 static int 632 acu_mixer_set_port(void *arg, mixer_ctrl_t *cp) 633 { 634 struct acu_softc *sc = arg; 635 636 return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp)); 637 } 638 639 static int 640 acu_mixer_get_port(void *arg, mixer_ctrl_t *cp) 641 { 642 struct acu_softc *sc = arg; 643 644 return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp)); 645 } 646 647 static int 648 acu_query_devinfo(void *arg, mixer_devinfo_t *dip) 649 { 650 struct acu_softc *sc = arg; 651 652 return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip)); 653 } 654 655 static void * 656 acu_malloc(void *arg, int direction, size_t size, 657 struct malloc_type *pool, int flags) 658 { 659 struct acu_softc *sc = arg; 660 struct acu_dma *ad; 661 int error; 662 663 if ((ad = malloc(sizeof(*ad), pool, flags)) == NULL) 664 return (NULL); 665 666 if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer(M_NOWAIT)) == NULL) 667 goto error; 668 669 ad->ad_size = size; 670 671 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs, 672 ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_NOWAIT); 673 if (error) 674 goto free_xfer; 675 676 error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size, 677 &ad->ad_addr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 678 if (error) 679 goto free_dmamem; 680 681 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 682 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ad->ad_map); 683 if (error) 684 goto unmap_dmamem; 685 686 error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size, 687 NULL, BUS_DMA_NOWAIT); 688 if (error) { 689 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 690 unmap_dmamem: bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size); 691 free_dmamem: bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 692 free_xfer: pxa2x0_dmac_free_xfer(ad->ad_dx); 693 error: free(ad, pool); 694 return (NULL); 695 } 696 697 ad->ad_dx->dx_cookie = sc; 698 ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH; 699 ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4; 700 ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32; 701 702 ad->ad_next = sc->sc_dmas; 703 sc->sc_dmas = ad; 704 return (KERNADDR(ad)); 705 } 706 707 static void 708 acu_free(void *arg, void *ptr, struct malloc_type *pool) 709 { 710 struct acu_softc *sc = arg; 711 struct acu_dma *ad, **adp; 712 713 for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) { 714 if (KERNADDR(ad) == ptr) { 715 pxa2x0_dmac_abort_xfer(ad->ad_dx); 716 pxa2x0_dmac_free_xfer(ad->ad_dx); 717 ad->ad_segs[0].ds_len = ad->ad_size; /* XXX */ 718 bus_dmamap_unload(sc->sc_dmat, ad->ad_map); 719 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 720 bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size); 721 bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 722 *adp = ad->ad_next; 723 free(ad, pool); 724 return; 725 } 726 } 727 } 728 729 static size_t 730 acu_round_buffersize(void *arg, int direction, size_t size) 731 { 732 733 return (size); 734 } 735 736 static paddr_t 737 acu_mappage(void *arg, void *mem, off_t off, int prot) 738 { 739 struct acu_softc *sc = arg; 740 struct acu_dma *ad; 741 742 if (off < 0) 743 return (-1); 744 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != mem; ad = ad->ad_next) 745 ; 746 if (ad == NULL) 747 return (-1); 748 return (bus_dmamem_mmap(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, 749 off, prot, BUS_DMA_WAITOK)); 750 } 751 752 static int 753 acu_get_props(void *arg) 754 { 755 756 return (AUDIO_PROP_MMAP|AUDIO_PROP_INDEPENDENT|AUDIO_PROP_FULLDUPLEX); 757 } 758 759 static int 760 acu_halt_output(void *arg) 761 { 762 struct acu_softc *sc = arg; 763 int s; 764 765 s = splaudio(); 766 if (sc->sc_txdma) { 767 acu_reg_write(sc, AC97_POCR, 0); 768 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 769 pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx); 770 sc->sc_txdma = NULL; 771 } 772 splx(s); 773 return (0); 774 } 775 776 static int 777 acu_halt_input(void *arg) 778 { 779 struct acu_softc *sc = arg; 780 int s; 781 782 s = splaudio(); 783 if (sc->sc_rxdma) { 784 acu_reg_write(sc, AC97_PICR, 0); 785 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 786 pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx); 787 sc->sc_rxdma = NULL; 788 } 789 splx(s); 790 return (0); 791 } 792 793 static int 794 acu_trigger_output(void *arg, void *start, void *end, int blksize, 795 void (*tx_func)(void *), void *tx_arg, const audio_params_t *param) 796 { 797 struct acu_softc *sc = arg; 798 struct dmac_xfer *dx; 799 struct acu_dma *ad; 800 int rv; 801 802 if (sc->sc_txdma) 803 return (EBUSY); 804 805 sc->sc_txfunc = tx_func; 806 sc->sc_txarg = tx_arg; 807 808 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 809 ; 810 if (ad == NULL) { 811 printf("acu_trigger_output: bad addr %p\n", start); 812 return (EINVAL); 813 } 814 815 sc->sc_txdma = ad; 816 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 817 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 818 819 /* 820 * Fix up a looping DMA request. 821 * The 'done' function will be called for every 'blksize' bytes 822 * transferred by the DMA engine. 823 */ 824 dx = ad->ad_dx; 825 dx->dx_done = acu_tx_loop_segment; 826 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX; 827 dx->dx_flow = DMAC_FLOW_CTRL_DEST; 828 dx->dx_loop_notify = blksize; 829 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 830 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs; 831 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs; 832 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 833 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 834 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 835 836 rv = pxa2x0_dmac_start_xfer(dx); 837 if (rv == 0) { 838 /* 839 * XXX: We should only do this once the request has been 840 * loaded into a DMAC channel. 841 */ 842 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 843 acu_reg_write(sc, AC97_POCR, AC97_FEFIE); 844 } 845 846 return (rv); 847 } 848 849 static int 850 acu_trigger_input(void *arg, void *start, void *end, int blksize, 851 void (*rx_func)(void *), void *rx_arg, const audio_params_t *param) 852 { 853 struct acu_softc *sc = arg; 854 struct dmac_xfer *dx; 855 struct acu_dma *ad; 856 int rv; 857 858 if (sc->sc_rxdma) 859 return (EBUSY); 860 861 sc->sc_rxfunc = rx_func; 862 sc->sc_rxarg = rx_arg; 863 864 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 865 ; 866 if (ad == NULL) { 867 printf("acu_trigger_input: bad addr %p\n", start); 868 return (EINVAL); 869 } 870 871 sc->sc_rxdma = ad; 872 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 873 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 874 875 /* 876 * Fix up a looping DMA request. 877 * The 'done' function will be called for every 'blksize' bytes 878 * transferred by the DMA engine. 879 */ 880 dx = ad->ad_dx; 881 dx->dx_done = acu_rx_loop_segment; 882 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX; 883 dx->dx_flow = DMAC_FLOW_CTRL_SRC; 884 dx->dx_loop_notify = blksize; 885 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 886 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs; 887 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs; 888 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 889 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 890 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 891 892 rv = pxa2x0_dmac_start_xfer(dx); 893 894 if (rv == 0) { 895 /* 896 * XXX: We should only do this once the request has been 897 * loaded into a DMAC channel. 898 */ 899 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 900 acu_reg_write(sc, AC97_PICR, AC97_FEFIE); 901 } 902 903 return (rv); 904 } 905 906 static void 907 acu_tx_loop_segment(struct dmac_xfer *dx, int status) 908 { 909 struct acu_softc *sc = dx->dx_cookie; 910 struct acu_dma *ad; 911 int s; 912 913 if ((ad = sc->sc_txdma) == NULL) 914 panic("acu_tx_loop_segment: bad TX dma descriptor!"); 915 916 if (ad->ad_dx != dx) 917 panic("acu_tx_loop_segment: xfer mismatch!"); 918 919 if (status) { 920 printf( 921 "%s: acu_tx_loop_segment: non-zero completion status %d\n", 922 sc->sc_dev.dv_xname, status); 923 } 924 925 s = splaudio(); 926 (sc->sc_txfunc)(sc->sc_txarg); 927 splx(s); 928 } 929 930 static void 931 acu_rx_loop_segment(struct dmac_xfer *dx, int status) 932 { 933 struct acu_softc *sc = dx->dx_cookie; 934 struct acu_dma *ad; 935 int s; 936 937 if ((ad = sc->sc_rxdma) == NULL) 938 panic("acu_rx_loop_segment: bad RX dma descriptor!"); 939 940 if (ad->ad_dx != dx) 941 panic("acu_rx_loop_segment: xfer mismatch!"); 942 943 if (status) { 944 printf( 945 "%s: acu_rx_loop_segment: non-zero completion status %d\n", 946 sc->sc_dev.dv_xname, status); 947 } 948 949 s = splaudio(); 950 (sc->sc_rxfunc)(sc->sc_rxarg); 951 splx(s); 952 } 953
Indexes created Wed Oct 01 18:09:54 GMT 2025