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pxa2x0_ac97.c revision 1.6
      1 /*	$NetBSD: pxa2x0_ac97.c,v 1.6 2007/08/21 11:39:11 kiyohara Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2003, 2005 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Steve C. Woodford for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/device.h>
     41 #include <sys/kernel.h>
     42 #include <sys/malloc.h>
     43 #include <sys/select.h>
     44 #include <sys/audioio.h>
     45 
     46 #include <machine/intr.h>
     47 #include <machine/bus.h>
     48 
     49 #include <dev/audio_if.h>
     50 #include <dev/audiovar.h>
     51 #include <dev/mulaw.h>
     52 #include <dev/auconv.h>
     53 #include <dev/ic/ac97reg.h>
     54 #include <dev/ic/ac97var.h>
     55 
     56 #include <arm/xscale/pxa2x0cpu.h>
     57 #include <arm/xscale/pxa2x0reg.h>
     58 #include <arm/xscale/pxa2x0var.h>
     59 #include <arm/xscale/pxa2x0_gpio.h>
     60 #include <arm/xscale/pxa2x0_dmac.h>
     61 
     62 #include "locators.h"
     63 
     64 struct acu_dma {
     65 	bus_dmamap_t ad_map;
     66 	void *ad_addr;
     67 #define	ACU_N_SEGS	1	/* XXX: We don't support > 1 */
     68 	bus_dma_segment_t ad_segs[ACU_N_SEGS];
     69 	int ad_nsegs;
     70 	size_t ad_size;
     71 	struct dmac_xfer *ad_dx;
     72 	struct acu_dma *ad_next;
     73 };
     74 
     75 #define KERNADDR(ad) ((void *)((ad)->ad_addr))
     76 
     77 struct acu_softc {
     78 	struct device sc_dev;
     79 	bus_space_tag_t sc_bust;
     80 	bus_dma_tag_t sc_dmat;
     81 	bus_space_handle_t sc_bush;
     82 	void *sc_irqcookie;
     83 	int sc_in_reset;
     84 	u_int sc_dac_rate;
     85 	u_int sc_adc_rate;
     86 
     87 	/* List of DMA ring-buffers allocated by acu_malloc() */
     88 	struct acu_dma *sc_dmas;
     89 
     90 	/* Dummy DMA segment which points to the AC97 PCM Fifo register */
     91 	bus_dma_segment_t sc_dr;
     92 
     93 	/* PCM Output (Tx) state */
     94 	dmac_peripheral_t sc_txp;
     95 	struct acu_dma *sc_txdma;
     96 	void (*sc_txfunc)(void *);
     97 	void *sc_txarg;
     98 
     99 	/* PCM Input (Rx) state */
    100 	dmac_peripheral_t sc_rxp;
    101 	struct acu_dma *sc_rxdma;
    102 	void (*sc_rxfunc)(void *);
    103 	void *sc_rxarg;
    104 
    105 	/* AC97 Codec State */
    106 	struct ac97_codec_if *sc_codec_if;
    107 	struct ac97_host_if sc_host_if;
    108 
    109 	/* Child audio(4) device */
    110 	struct device *sc_audiodev;
    111 
    112 	/* auconv encodings */
    113 	struct audio_encoding_set *sc_encodings;
    114 };
    115 
    116 static int	pxaacu_match(struct device *, struct cfdata *, void *);
    117 static void	pxaacu_attach(struct device *, struct device *, void *);
    118 
    119 CFATTACH_DECL(pxaacu, sizeof(struct acu_softc),
    120     pxaacu_match, pxaacu_attach, NULL, NULL);
    121 
    122 static int acu_codec_attach(void *, struct ac97_codec_if *);
    123 static int acu_codec_read(void *, u_int8_t, u_int16_t *);
    124 static int acu_codec_write(void *, u_int8_t, u_int16_t);
    125 static int acu_codec_reset(void *);
    126 static int acu_intr(void *);
    127 
    128 static int acu_open(void *, int);
    129 static void acu_close(void *);
    130 static int acu_query_encoding(void *, struct audio_encoding *);
    131 static int acu_set_params(void *, int, int, audio_params_t *, audio_params_t *,
    132 	    stream_filter_list_t *, stream_filter_list_t *);
    133 static int acu_round_blocksize(void *, int, int, const audio_params_t *);
    134 static int acu_halt_output(void *);
    135 static int acu_halt_input(void *);
    136 static int acu_trigger_output(void *, void *, void *, int, void (*)(void *),
    137 	    void *, const audio_params_t *);
    138 static int acu_trigger_input(void *, void *, void *, int, void (*)(void *),
    139 	    void *, const audio_params_t *);
    140 static void acu_tx_loop_segment(struct dmac_xfer *, int);
    141 static void acu_rx_loop_segment(struct dmac_xfer *, int);
    142 static int acu_getdev(void *, struct audio_device *);
    143 static int acu_mixer_set_port(void *, mixer_ctrl_t *);
    144 static int acu_mixer_get_port(void *, mixer_ctrl_t *);
    145 static int acu_query_devinfo(void *, mixer_devinfo_t *);
    146 static void *acu_malloc(void *, int, size_t, struct malloc_type *, int);
    147 static void acu_free(void *, void *, struct malloc_type *);
    148 static size_t acu_round_buffersize(void *, int, size_t);
    149 static paddr_t acu_mappage(void *, void *, off_t, int);
    150 static int acu_get_props(void *);
    151 
    152 struct audio_hw_if acu_hw_if = {
    153 	acu_open,
    154 	acu_close,
    155 	NULL,
    156 	acu_query_encoding,
    157 	acu_set_params,
    158 	acu_round_blocksize,
    159 	NULL,
    160 	NULL,
    161 	NULL,
    162 	NULL,
    163 	NULL,
    164 	acu_halt_output,
    165 	acu_halt_input,
    166 	NULL,
    167 	acu_getdev,
    168 	NULL,
    169 	acu_mixer_set_port,
    170 	acu_mixer_get_port,
    171 	acu_query_devinfo,
    172 	acu_malloc,
    173 	acu_free,
    174 	acu_round_buffersize,
    175 	acu_mappage,
    176 	acu_get_props,
    177 	acu_trigger_output,
    178 	acu_trigger_input,
    179 	NULL,
    180 };
    181 
    182 struct audio_device acu_device = {
    183 	"PXA250 AC97",
    184 	"",
    185 	"acu"
    186 };
    187 
    188 static const struct audio_format acu_formats[] = {
    189 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
    190 	 2, AUFMT_STEREO, 0, {4000, 48000}}
    191 };
    192 #define	ACU_NFORMATS	(sizeof(acu_formats) / sizeof(struct audio_format))
    193 
    194 static inline u_int32_t
    195 acu_reg_read(struct acu_softc *sc, int reg)
    196 {
    197 
    198 	return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));
    199 }
    200 
    201 static inline void
    202 acu_reg_write(struct acu_softc *sc, int reg, u_int32_t val)
    203 {
    204 
    205 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
    206 }
    207 
    208 static inline int
    209 acu_codec_ready(struct acu_softc *sc)
    210 {
    211 
    212 	return (acu_reg_read(sc, AC97_GSR) & GSR_PCR);
    213 }
    214 
    215 static inline int
    216 acu_wait_gsr(struct acu_softc *sc, u_int32_t bit)
    217 {
    218 	int timeout;
    219 	u_int32_t rv;
    220 
    221 	for (timeout = 5000; timeout; timeout--) {
    222 		if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) {
    223 			acu_reg_write(sc, AC97_GSR, rv | bit);
    224 			return (0);
    225 		}
    226 		delay(1);
    227 	}
    228 
    229 	return (1);
    230 }
    231 
    232 static int
    233 pxaacu_match(struct device *parent, struct cfdata *cf, void *aux)
    234 {
    235 	struct pxaip_attach_args *pxa = aux;
    236 	struct pxa2x0_gpioconf *gpioconf;
    237 	u_int gpio;
    238 	int i;
    239 
    240 	if (pxa->pxa_addr != PXA2X0_AC97_BASE ||
    241 	    pxa->pxa_intr != PXA2X0_INT_AC97)
    242 		return (0);
    243 
    244 	gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf :
    245 	    pxa27x_pxaacu_gpioconf;
    246 	for (i = 0; gpioconf[i].pin != -1; i++) {
    247 		gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
    248 		if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
    249 		    GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
    250 			return (0);
    251 	}
    252 
    253 	pxa->pxa_size = PXA2X0_AC97_SIZE;
    254 
    255 	return (1);
    256 }
    257 
    258 static void
    259 pxaacu_attach(struct device *parent, struct device *self, void *aux)
    260 {
    261 	struct acu_softc *sc = (struct acu_softc *)self;
    262 	struct pxaip_attach_args *pxa = aux;
    263 
    264 	sc->sc_bust = pxa->pxa_iot;
    265 	sc->sc_dmat = pxa->pxa_dmat;
    266 
    267 	aprint_naive("\n");
    268 	aprint_normal(": AC97 Controller\n");
    269 
    270 	if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0,
    271 	    &sc->sc_bush)) {
    272 		aprint_error("%s: Can't map registers!\n", sc->sc_dev.dv_xname);
    273 		return;
    274 	}
    275 
    276 	sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO,
    277 	    acu_intr, sc);
    278 	KASSERT(sc->sc_irqcookie != NULL);
    279 
    280 	/* Make sure the AC97 clock is enabled */
    281 	pxa2x0_clkman_config(CKEN_AC97, true);
    282 	delay(100);
    283 
    284 	/* Do a cold reset */
    285 	acu_reg_write(sc, AC97_GCR, 0);
    286 	delay(100);
    287 	acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
    288 	delay(100);
    289 	acu_reg_write(sc, AC97_CAR, 0);
    290 
    291 	if (acu_wait_gsr(sc, GSR_PCR)) {
    292 		acu_reg_write(sc, AC97_GCR, 0);
    293 		delay(100);
    294 		pxa2x0_clkman_config(CKEN_AC97, false);
    295 		bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
    296 		aprint_error("%s: Primary codec not ready\n",
    297 		    sc->sc_dev.dv_xname);
    298 		return;
    299 	}
    300 
    301 	sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR;
    302 	sc->sc_dr.ds_len = 4;
    303 
    304 	sc->sc_codec_if = NULL;
    305 	sc->sc_host_if.arg = sc;
    306 	sc->sc_host_if.attach = acu_codec_attach;
    307 	sc->sc_host_if.read = acu_codec_read;
    308 	sc->sc_host_if.write = acu_codec_write;
    309 	sc->sc_host_if.reset = acu_codec_reset;
    310 	sc->sc_host_if.flags = NULL;
    311 	sc->sc_in_reset = 0;
    312 	sc->sc_dac_rate = sc->sc_adc_rate = 0;
    313 
    314 	if (ac97_attach(&sc->sc_host_if, &sc->sc_dev)) {
    315 		aprint_error("%s: Failed to attach primary codec\n",
    316 		    sc->sc_dev.dv_xname);
    317  fail:
    318 		acu_reg_write(sc, AC97_GCR, 0);
    319 		delay(100);
    320 		pxa2x0_clkman_config(CKEN_AC97, false);
    321 		bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
    322 		return;
    323 	}
    324 
    325 	if (auconv_create_encodings(acu_formats, ACU_NFORMATS,
    326 	    &sc->sc_encodings)) {
    327 		aprint_error("%s: Failed to create encodings\n",
    328 		    sc->sc_dev.dv_xname);
    329 		if (sc->sc_codec_if != NULL)
    330 			(sc->sc_codec_if->vtbl->detach)(sc->sc_codec_if);
    331 		goto fail;
    332 	}
    333 
    334 	sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, &sc->sc_dev);
    335 
    336 	/*
    337 	 * As a work-around for braindamage in the PXA250's AC97 controller
    338 	 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until
    339 	 * acu_open() is called. acu_close() also puts the controller into
    340 	 * Cold Reset.
    341 	 *
    342 	 * While this won't necessarily prevent Rx FIFO overruns, it at least
    343 	 * allows the user to recover by closing then re-opening the audio
    344 	 * device.
    345 	 */
    346 	acu_reg_write(sc, AC97_GCR, 0);
    347 	sc->sc_in_reset = 1;
    348 }
    349 
    350 static int
    351 acu_codec_attach(void *arg, struct ac97_codec_if *aci)
    352 {
    353 	struct acu_softc *sc = arg;
    354 
    355 	sc->sc_codec_if = aci;
    356 	return (0);
    357 }
    358 
    359 static int
    360 acu_codec_read(void *arg, u_int8_t codec_reg, u_int16_t *valp)
    361 {
    362 	struct acu_softc *sc = arg;
    363 	u_int32_t val;
    364 	int s, reg, rv = 1;
    365 
    366 	/*
    367 	 * If we're currently closed, return non-zero. The ac97 frontend
    368 	 * will use its cached copy of the register instead.
    369 	 */
    370 	if (sc->sc_in_reset)
    371 		return (1);
    372 
    373 	reg = AC97_CODEC_BASE(0) + codec_reg * 2;
    374 
    375 	s = splaudio();
    376 
    377 	if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP))
    378 		goto out_nocar;
    379 
    380 	val = acu_reg_read(sc, AC97_GSR);
    381 	val |= GSR_RDCS | GSR_SDONE;
    382 	acu_reg_write(sc, AC97_GSR, val);
    383 
    384 	/*
    385 	 * Dummy read to initiate the real read access
    386 	 */
    387 	(void) acu_reg_read(sc, reg);
    388 	if (acu_wait_gsr(sc, GSR_SDONE))
    389 		goto out;
    390 
    391 	(void) acu_reg_read(sc, reg);
    392 	if (acu_wait_gsr(sc, GSR_SDONE))
    393 		goto out;
    394 
    395 	val = acu_reg_read(sc, AC97_GSR);
    396 	if (val & GSR_RDCS)
    397 		goto out;
    398 
    399 	*valp = acu_reg_read(sc, reg);
    400 	if (acu_wait_gsr(sc, GSR_SDONE))
    401 		goto out;
    402 
    403 	rv = 0;
    404 
    405 out:
    406 	acu_reg_write(sc, AC97_CAR, 0);
    407 out_nocar:
    408 	splx(s);
    409 	delay(10);
    410 	return (rv);
    411 }
    412 
    413 static int
    414 acu_codec_write(void *arg, u_int8_t codec_reg, u_int16_t val)
    415 {
    416 	struct acu_softc *sc = arg;
    417 	u_int16_t rv;
    418 	int s;
    419 
    420 	/*
    421 	 * If we're currently closed, chances are the user is just
    422 	 * tweaking mixer settings. Pretend the write succeeded.
    423 	 * The ac97 frontend will cache the value anyway, and it'll
    424 	 * be written correctly when the driver is opened.
    425 	 */
    426 	if (sc->sc_in_reset)
    427 		return (0);
    428 
    429 	s = splaudio();
    430 
    431 	if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) {
    432 		splx(s);
    433 		return (1);
    434 	}
    435 
    436 	rv = acu_reg_read(sc, AC97_GSR);
    437 	rv |= GSR_RDCS | GSR_CDONE;
    438 	acu_reg_write(sc, AC97_GSR, rv);
    439 
    440 	acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val);
    441 
    442 	/*
    443 	 * Wait for the write to complete
    444 	 */
    445 	(void) acu_wait_gsr(sc, GSR_CDONE);
    446 	acu_reg_write(sc, AC97_CAR, 0);
    447 
    448 	splx(s);
    449 	delay(10);
    450 	return (0);
    451 }
    452 
    453 static int
    454 acu_codec_reset(void *arg)
    455 {
    456 	struct acu_softc *sc = arg;
    457 	u_int32_t rv;
    458 
    459 	rv = acu_reg_read(sc, AC97_GCR);
    460 	acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST);
    461 	delay(100);
    462 	acu_reg_write(sc, AC97_GCR, rv);
    463 	delay(100);
    464 
    465 	if (acu_wait_gsr(sc, GSR_PCR)) {
    466 		printf("%s: acu_codec_reset: failed to ready after reset\n",
    467 		    sc->sc_dev.dv_xname);
    468 		return (ETIMEDOUT);
    469 	}
    470 
    471 	return (0);
    472 }
    473 
    474 static int
    475 acu_intr(void *arg)
    476 {
    477 	struct acu_softc *sc = arg;
    478 	u_int32_t gsr, reg;
    479 
    480 	gsr = acu_reg_read(sc, AC97_GSR);
    481 
    482 	/*
    483 	 * Tx FIFO underruns are no big deal. Just log it and ignore and
    484 	 * subsequent underruns until the next time acu_trigger_output()
    485 	 * is called.
    486 	 */
    487 	if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) {
    488 		acu_reg_write(sc, AC97_POCR, 0);
    489 		reg = acu_reg_read(sc, AC97_POSR);
    490 		acu_reg_write(sc, AC97_POSR, reg);
    491 		printf("%s: Tx PCM Fifo underrun\n", sc->sc_dev.dv_xname);
    492 	}
    493 
    494 	/*
    495 	 * Rx FIFO overruns are a different story. See PAX250 Errata #125
    496 	 * for the gory details.
    497 	 * I don't see any way to gracefully recover from this problem,
    498 	 * other than a issuing a Cold Reset in acu_close().
    499 	 * The best we can do here is to report the problem on the console.
    500 	 */
    501 	if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) {
    502 		acu_reg_write(sc, AC97_PICR, 0);
    503 		reg = acu_reg_read(sc, AC97_PISR);
    504 		acu_reg_write(sc, AC97_PISR, reg);
    505 		printf("%s: Rx PCM Fifo overrun\n", sc->sc_dev.dv_xname);
    506 	}
    507 
    508 	return (1);
    509 }
    510 
    511 static int
    512 acu_open(void *arg, int flags)
    513 {
    514 	struct acu_softc *sc = arg;
    515 
    516 	/*
    517 	 * Deassert Cold Reset
    518 	 */
    519 	acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
    520 	delay(100);
    521 	acu_reg_write(sc, AC97_CAR, 0);
    522 
    523 	/*
    524 	 * Wait for the primary codec to become ready
    525 	 */
    526 	if (acu_wait_gsr(sc, GSR_PCR))
    527 		return (EIO);
    528 	sc->sc_in_reset = 0;
    529 
    530 	/*
    531 	 * Restore the codec port settings
    532 	 */
    533 	sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if);
    534 
    535 	/*
    536 	 * Need to reprogram the sample rates, since 'restore_ports'
    537 	 * doesn't do it.
    538 	 *
    539 	 * XXX: These aren't the only two sample rate registers ...
    540 	 */
    541 	if (sc->sc_dac_rate)
    542 		(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    543 		    AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate);
    544 	if (sc->sc_adc_rate)
    545 		(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    546 		    AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate);
    547 
    548 	return (0);
    549 }
    550 
    551 static void
    552 acu_close(void *arg)
    553 {
    554 	struct acu_softc *sc = arg;
    555 
    556 	/*
    557 	 * Make sure the hardware is quiescent
    558 	 */
    559 	acu_halt_output(sc);
    560 	acu_halt_input(sc);
    561 	delay(100);
    562 
    563 	/* Assert Cold Reset */
    564 	acu_reg_write(sc, AC97_GCR, 0);
    565 	sc->sc_in_reset = 1;
    566 }
    567 
    568 static int
    569 acu_query_encoding(void *arg, struct audio_encoding *fp)
    570 {
    571 	struct acu_softc *sc = arg;
    572 
    573 	return (auconv_query_encoding(sc->sc_encodings, fp));
    574 }
    575 
    576 static int
    577 acu_set_params(void *arg, int setmode, int usemode,
    578     audio_params_t *play, audio_params_t *rec,
    579     stream_filter_list_t *pfil, stream_filter_list_t *rfil)
    580 {
    581 	struct acu_softc *sc = arg;
    582 	struct audio_params *p;
    583 	stream_filter_list_t *fil;
    584 	int mode, err;
    585 
    586 	for (mode = AUMODE_RECORD; mode != -1;
    587 	    mode = (mode == AUMODE_RECORD) ? AUMODE_PLAY : -1) {
    588 		if ((setmode & mode) == 0)
    589 			continue;
    590 
    591 		p = (mode == AUMODE_PLAY) ? play : rec;
    592 
    593 		if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
    594 		    (p->precision != 8 && p->precision != 16) ||
    595 		    (p->channels != 1 && p->channels != 2)) {
    596 			printf("acu_set_params: precision/channels botch\n");
    597 			printf("acu_set_params: rate %d, prec %d, chan %d\n",
    598 			    p->sample_rate, p->precision, p->channels);
    599 			return (EINVAL);
    600 		}
    601 
    602 		fil = (mode == AUMODE_PLAY) ? pfil : rfil;
    603 		err = auconv_set_converter(acu_formats, ACU_NFORMATS,
    604 		    mode, p, true, fil);
    605 		if (err < 0)
    606 			return (EINVAL);
    607 
    608 		if (mode == AUMODE_PLAY) {
    609 			err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    610 			    AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate);
    611 			sc->sc_dac_rate = play->sample_rate;
    612 		} else {
    613 			err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
    614 			    AC97_REG_PCM_LR_ADC_RATE, &rec->sample_rate);
    615 			sc->sc_adc_rate = rec->sample_rate;
    616 		}
    617 		if (err)
    618 			return (EINVAL);
    619 	}
    620 
    621 	return (0);
    622 }
    623 
    624 static int
    625 acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param)
    626 {
    627 
    628 	return (blk & ~0x1f);
    629 }
    630 
    631 static int
    632 acu_getdev(void *addr, struct audio_device *retp)
    633 {
    634 
    635 	*retp = acu_device;
    636 	return (0);
    637 }
    638 
    639 static int
    640 acu_mixer_set_port(void *arg, mixer_ctrl_t *cp)
    641 {
    642 	struct acu_softc *sc = arg;
    643 
    644 	return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp));
    645 }
    646 
    647 static int
    648 acu_mixer_get_port(void *arg, mixer_ctrl_t *cp)
    649 {
    650 	struct acu_softc *sc = arg;
    651 
    652 	return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp));
    653 }
    654 
    655 static int
    656 acu_query_devinfo(void *arg, mixer_devinfo_t *dip)
    657 {
    658 	struct acu_softc *sc = arg;
    659 
    660 	return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip));
    661 }
    662 
    663 static void *
    664 acu_malloc(void *arg, int direction, size_t size,
    665     struct malloc_type *pool, int flags)
    666 {
    667 	struct acu_softc *sc = arg;
    668 	struct acu_dma *ad;
    669 	int error;
    670 
    671 	if ((ad = malloc(sizeof(*ad), pool, flags)) == NULL)
    672 		return (NULL);
    673 
    674 	if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer(M_NOWAIT)) == NULL)
    675 		goto error;
    676 
    677 	ad->ad_size = size;
    678 
    679 	error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs,
    680 	    ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_NOWAIT);
    681 	if (error)
    682 		goto free_xfer;
    683 
    684 	error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size,
    685 	    &ad->ad_addr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
    686 	if (error)
    687 		goto free_dmamem;
    688 
    689 	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
    690 	    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ad->ad_map);
    691 	if (error)
    692 		goto unmap_dmamem;
    693 
    694 	error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size,
    695 	    NULL, BUS_DMA_NOWAIT);
    696 	if (error) {
    697 		bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
    698 unmap_dmamem:	bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size);
    699 free_dmamem:	bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
    700 free_xfer:	pxa2x0_dmac_free_xfer(ad->ad_dx);
    701 error:		free(ad, pool);
    702 		return (NULL);
    703 	}
    704 
    705 	ad->ad_dx->dx_cookie = sc;
    706 	ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH;
    707 	ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4;
    708 	ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32;
    709 
    710 	ad->ad_next = sc->sc_dmas;
    711 	sc->sc_dmas = ad;
    712 	return (KERNADDR(ad));
    713 }
    714 
    715 static void
    716 acu_free(void *arg, void *ptr, struct malloc_type *pool)
    717 {
    718 	struct acu_softc *sc = arg;
    719 	struct acu_dma *ad, **adp;
    720 
    721 	for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) {
    722 		if (KERNADDR(ad) == ptr) {
    723 			pxa2x0_dmac_abort_xfer(ad->ad_dx);
    724 			pxa2x0_dmac_free_xfer(ad->ad_dx);
    725 			ad->ad_segs[0].ds_len = ad->ad_size;	/* XXX */
    726 			bus_dmamap_unload(sc->sc_dmat, ad->ad_map);
    727 			bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
    728 			bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size);
    729 			bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
    730 			*adp = ad->ad_next;
    731 			free(ad, pool);
    732 			return;
    733 		}
    734 	}
    735 }
    736 
    737 static size_t
    738 acu_round_buffersize(void *arg, int direction, size_t size)
    739 {
    740 
    741 	return (size);
    742 }
    743 
    744 static paddr_t
    745 acu_mappage(void *arg, void *mem, off_t off, int prot)
    746 {
    747 	struct acu_softc *sc = arg;
    748 	struct acu_dma *ad;
    749 
    750 	if (off < 0)
    751 		return (-1);
    752 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != mem; ad = ad->ad_next)
    753 		;
    754 	if (ad == NULL)
    755 		return (-1);
    756 	return (bus_dmamem_mmap(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs,
    757 	    off, prot, BUS_DMA_WAITOK));
    758 }
    759 
    760 static int
    761 acu_get_props(void *arg)
    762 {
    763 
    764 	return (AUDIO_PROP_MMAP|AUDIO_PROP_INDEPENDENT|AUDIO_PROP_FULLDUPLEX);
    765 }
    766 
    767 static int
    768 acu_halt_output(void *arg)
    769 {
    770 	struct acu_softc *sc = arg;
    771 	int s;
    772 
    773 	s = splaudio();
    774 	if (sc->sc_txdma) {
    775 		acu_reg_write(sc, AC97_POCR, 0);
    776 		acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
    777 		pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx);
    778 		sc->sc_txdma = NULL;
    779 	}
    780 	splx(s);
    781 	return (0);
    782 }
    783 
    784 static int
    785 acu_halt_input(void *arg)
    786 {
    787 	struct acu_softc *sc = arg;
    788 	int s;
    789 
    790 	s = splaudio();
    791 	if (sc->sc_rxdma) {
    792 		acu_reg_write(sc, AC97_PICR, 0);
    793 		acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
    794 		pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx);
    795 		sc->sc_rxdma = NULL;
    796 	}
    797 	splx(s);
    798 	return (0);
    799 }
    800 
    801 static int
    802 acu_trigger_output(void *arg, void *start, void *end, int blksize,
    803     void (*tx_func)(void *), void *tx_arg, const audio_params_t *param)
    804 {
    805 	struct acu_softc *sc = arg;
    806 	struct dmac_xfer *dx;
    807 	struct acu_dma *ad;
    808 	int rv;
    809 
    810 	if (sc->sc_txdma)
    811 		return (EBUSY);
    812 
    813 	sc->sc_txfunc = tx_func;
    814 	sc->sc_txarg = tx_arg;
    815 
    816 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
    817 		;
    818 	if (ad == NULL) {
    819 		printf("acu_trigger_output: bad addr %p\n", start);
    820 		return (EINVAL);
    821 	}
    822 
    823 	sc->sc_txdma = ad;
    824 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
    825 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
    826 
    827 	/*
    828 	 * Fix up a looping DMA request.
    829 	 * The 'done' function will be called for every 'blksize' bytes
    830 	 * transferred by the DMA engine.
    831 	 */
    832 	dx = ad->ad_dx;
    833 	dx->dx_done = acu_tx_loop_segment;
    834 	dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX;
    835 	dx->dx_flow = DMAC_FLOW_CTRL_DEST;
    836 	dx->dx_loop_notify = blksize;
    837 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
    838 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
    839 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
    840 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
    841 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
    842 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
    843 
    844 	rv = pxa2x0_dmac_start_xfer(dx);
    845 	if (rv == 0) {
    846 		/*
    847 		 * XXX: We should only do this once the request has been
    848 		 * loaded into a DMAC channel.
    849 		 */
    850 		acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
    851 		acu_reg_write(sc, AC97_POCR, AC97_FEFIE);
    852 	}
    853 
    854 	return (rv);
    855 }
    856 
    857 static int
    858 acu_trigger_input(void *arg, void *start, void *end, int blksize,
    859     void (*rx_func)(void *), void *rx_arg, const audio_params_t *param)
    860 {
    861 	struct acu_softc *sc = arg;
    862 	struct dmac_xfer *dx;
    863 	struct acu_dma *ad;
    864 	int rv;
    865 
    866 	if (sc->sc_rxdma)
    867 		return (EBUSY);
    868 
    869 	sc->sc_rxfunc = rx_func;
    870 	sc->sc_rxarg = rx_arg;
    871 
    872 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
    873 		;
    874 	if (ad == NULL) {
    875 		printf("acu_trigger_input: bad addr %p\n", start);
    876 		return (EINVAL);
    877 	}
    878 
    879 	sc->sc_rxdma = ad;
    880 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
    881 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
    882 
    883 	/*
    884 	 * Fix up a looping DMA request.
    885 	 * The 'done' function will be called for every 'blksize' bytes
    886 	 * transferred by the DMA engine.
    887 	 */
    888 	dx = ad->ad_dx;
    889 	dx->dx_done = acu_rx_loop_segment;
    890 	dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX;
    891 	dx->dx_flow = DMAC_FLOW_CTRL_SRC;
    892 	dx->dx_loop_notify = blksize;
    893 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
    894 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
    895 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
    896 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
    897 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
    898 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
    899 
    900 	rv = pxa2x0_dmac_start_xfer(dx);
    901 
    902 	if (rv == 0) {
    903 		/*
    904 		 * XXX: We should only do this once the request has been
    905 		 * loaded into a DMAC channel.
    906 		 */
    907 		acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
    908 		acu_reg_write(sc, AC97_PICR, AC97_FEFIE);
    909 	}
    910 
    911 	return (rv);
    912 }
    913 
    914 static void
    915 acu_tx_loop_segment(struct dmac_xfer *dx, int status)
    916 {
    917 	struct acu_softc *sc = dx->dx_cookie;
    918 	struct acu_dma *ad;
    919 	int s;
    920 
    921 	if ((ad = sc->sc_txdma) == NULL)
    922 		panic("acu_tx_loop_segment: bad TX dma descriptor!");
    923 
    924 	if (ad->ad_dx != dx)
    925 		panic("acu_tx_loop_segment: xfer mismatch!");
    926 
    927 	if (status) {
    928 		printf(
    929 		    "%s: acu_tx_loop_segment: non-zero completion status %d\n",
    930 		    sc->sc_dev.dv_xname, status);
    931 	}
    932 
    933 	s = splaudio();
    934 	(sc->sc_txfunc)(sc->sc_txarg);
    935 	splx(s);
    936 }
    937 
    938 static void
    939 acu_rx_loop_segment(struct dmac_xfer *dx, int status)
    940 {
    941 	struct acu_softc *sc = dx->dx_cookie;
    942 	struct acu_dma *ad;
    943 	int s;
    944 
    945 	if ((ad = sc->sc_rxdma) == NULL)
    946 		panic("acu_rx_loop_segment: bad RX dma descriptor!");
    947 
    948 	if (ad->ad_dx != dx)
    949 		panic("acu_rx_loop_segment: xfer mismatch!");
    950 
    951 	if (status) {
    952 		printf(
    953 		    "%s: acu_rx_loop_segment: non-zero completion status %d\n",
    954 		    sc->sc_dev.dv_xname, status);
    955 	}
    956 
    957 	s = splaudio();
    958 	(sc->sc_rxfunc)(sc->sc_rxarg);
    959 	splx(s);
    960 }
    961