pxa2x0_ac97.c revision 1.9
1 /* $NetBSD: pxa2x0_ac97.c,v 1.9 2011/07/01 20:32:51 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2005 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/select.h> 44 #include <sys/audioio.h> 45 46 #include <machine/intr.h> 47 #include <sys/bus.h> 48 49 #include <dev/audio_if.h> 50 #include <dev/audiovar.h> 51 #include <dev/mulaw.h> 52 #include <dev/auconv.h> 53 #include <dev/ic/ac97reg.h> 54 #include <dev/ic/ac97var.h> 55 56 #include <arm/xscale/pxa2x0cpu.h> 57 #include <arm/xscale/pxa2x0reg.h> 58 #include <arm/xscale/pxa2x0var.h> 59 #include <arm/xscale/pxa2x0_gpio.h> 60 #include <arm/xscale/pxa2x0_dmac.h> 61 62 #include "locators.h" 63 64 struct acu_dma { 65 bus_dmamap_t ad_map; 66 void *ad_addr; 67 #define ACU_N_SEGS 1 /* XXX: We don't support > 1 */ 68 bus_dma_segment_t ad_segs[ACU_N_SEGS]; 69 int ad_nsegs; 70 size_t ad_size; 71 struct dmac_xfer *ad_dx; 72 struct acu_dma *ad_next; 73 }; 74 75 #define KERNADDR(ad) ((void *)((ad)->ad_addr)) 76 77 struct acu_softc { 78 device_t sc_dev; 79 bus_space_tag_t sc_bust; 80 bus_dma_tag_t sc_dmat; 81 bus_space_handle_t sc_bush; 82 void *sc_irqcookie; 83 int sc_in_reset; 84 u_int sc_dac_rate; 85 u_int sc_adc_rate; 86 87 /* List of DMA ring-buffers allocated by acu_malloc() */ 88 struct acu_dma *sc_dmas; 89 90 /* Dummy DMA segment which points to the AC97 PCM Fifo register */ 91 bus_dma_segment_t sc_dr; 92 93 /* PCM Output (Tx) state */ 94 dmac_peripheral_t sc_txp; 95 struct acu_dma *sc_txdma; 96 void (*sc_txfunc)(void *); 97 void *sc_txarg; 98 99 /* PCM Input (Rx) state */ 100 dmac_peripheral_t sc_rxp; 101 struct acu_dma *sc_rxdma; 102 void (*sc_rxfunc)(void *); 103 void *sc_rxarg; 104 105 /* AC97 Codec State */ 106 struct ac97_codec_if *sc_codec_if; 107 struct ac97_host_if sc_host_if; 108 109 /* Child audio(4) device */ 110 struct device *sc_audiodev; 111 112 /* auconv encodings */ 113 struct audio_encoding_set *sc_encodings; 114 }; 115 116 static int pxaacu_match(device_t, cfdata_t, void *); 117 static void pxaacu_attach(device_t, device_t, void *); 118 119 CFATTACH_DECL_NEW(pxaacu, sizeof(struct acu_softc), 120 pxaacu_match, pxaacu_attach, NULL, NULL); 121 122 static int acu_codec_attach(void *, struct ac97_codec_if *); 123 static int acu_codec_read(void *, u_int8_t, u_int16_t *); 124 static int acu_codec_write(void *, u_int8_t, u_int16_t); 125 static int acu_codec_reset(void *); 126 static int acu_intr(void *); 127 128 static int acu_open(void *, int); 129 static void acu_close(void *); 130 static int acu_query_encoding(void *, struct audio_encoding *); 131 static int acu_set_params(void *, int, int, audio_params_t *, audio_params_t *, 132 stream_filter_list_t *, stream_filter_list_t *); 133 static int acu_round_blocksize(void *, int, int, const audio_params_t *); 134 static int acu_halt_output(void *); 135 static int acu_halt_input(void *); 136 static int acu_trigger_output(void *, void *, void *, int, void (*)(void *), 137 void *, const audio_params_t *); 138 static int acu_trigger_input(void *, void *, void *, int, void (*)(void *), 139 void *, const audio_params_t *); 140 static void acu_tx_loop_segment(struct dmac_xfer *, int); 141 static void acu_rx_loop_segment(struct dmac_xfer *, int); 142 static int acu_getdev(void *, struct audio_device *); 143 static int acu_mixer_set_port(void *, mixer_ctrl_t *); 144 static int acu_mixer_get_port(void *, mixer_ctrl_t *); 145 static int acu_query_devinfo(void *, mixer_devinfo_t *); 146 static void *acu_malloc(void *, int, size_t, struct malloc_type *, int); 147 static void acu_free(void *, void *, struct malloc_type *); 148 static size_t acu_round_buffersize(void *, int, size_t); 149 static paddr_t acu_mappage(void *, void *, off_t, int); 150 static int acu_get_props(void *); 151 152 struct audio_hw_if acu_hw_if = { 153 acu_open, 154 acu_close, 155 NULL, 156 acu_query_encoding, 157 acu_set_params, 158 acu_round_blocksize, 159 NULL, 160 NULL, 161 NULL, 162 NULL, 163 NULL, 164 acu_halt_output, 165 acu_halt_input, 166 NULL, 167 acu_getdev, 168 NULL, 169 acu_mixer_set_port, 170 acu_mixer_get_port, 171 acu_query_devinfo, 172 acu_malloc, 173 acu_free, 174 acu_round_buffersize, 175 acu_mappage, 176 acu_get_props, 177 acu_trigger_output, 178 acu_trigger_input, 179 NULL, 180 }; 181 182 struct audio_device acu_device = { 183 "PXA250 AC97", 184 "", 185 "acu" 186 }; 187 188 static const struct audio_format acu_formats[] = { 189 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 190 2, AUFMT_STEREO, 0, {4000, 48000}} 191 }; 192 #define ACU_NFORMATS (sizeof(acu_formats) / sizeof(struct audio_format)) 193 194 static inline u_int32_t 195 acu_reg_read(struct acu_softc *sc, int reg) 196 { 197 198 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 199 } 200 201 static inline void 202 acu_reg_write(struct acu_softc *sc, int reg, u_int32_t val) 203 { 204 205 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 206 } 207 208 static inline int 209 acu_codec_ready(struct acu_softc *sc) 210 { 211 212 return (acu_reg_read(sc, AC97_GSR) & GSR_PCR); 213 } 214 215 static inline int 216 acu_wait_gsr(struct acu_softc *sc, u_int32_t bit) 217 { 218 int timeout; 219 u_int32_t rv; 220 221 for (timeout = 5000; timeout; timeout--) { 222 if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) { 223 acu_reg_write(sc, AC97_GSR, rv | bit); 224 return (0); 225 } 226 delay(1); 227 } 228 229 return (1); 230 } 231 232 static int 233 pxaacu_match(device_t parent, cfdata_t cf, void *aux) 234 { 235 struct pxaip_attach_args *pxa = aux; 236 struct pxa2x0_gpioconf *gpioconf; 237 u_int gpio; 238 int i; 239 240 if (pxa->pxa_addr != PXA2X0_AC97_BASE || 241 pxa->pxa_intr != PXA2X0_INT_AC97) 242 return (0); 243 244 gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf : 245 pxa27x_pxaacu_gpioconf; 246 for (i = 0; gpioconf[i].pin != -1; i++) { 247 gpio = pxa2x0_gpio_get_function(gpioconf[i].pin); 248 if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) || 249 GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value)) 250 return (0); 251 } 252 253 pxa->pxa_size = PXA2X0_AC97_SIZE; 254 255 return (1); 256 } 257 258 static void 259 pxaacu_attach(device_t parent, device_t self, void *aux) 260 { 261 struct acu_softc *sc = device_private(self); 262 struct pxaip_attach_args *pxa = aux; 263 264 sc->sc_dev = self; 265 sc->sc_bust = pxa->pxa_iot; 266 sc->sc_dmat = pxa->pxa_dmat; 267 268 aprint_naive("\n"); 269 aprint_normal(": AC97 Controller\n"); 270 271 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 272 &sc->sc_bush)) { 273 aprint_error_dev(self, "Can't map registers!\n"); 274 return; 275 } 276 277 sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO, 278 acu_intr, sc); 279 KASSERT(sc->sc_irqcookie != NULL); 280 281 /* Make sure the AC97 clock is enabled */ 282 pxa2x0_clkman_config(CKEN_AC97, true); 283 delay(100); 284 285 /* Do a cold reset */ 286 acu_reg_write(sc, AC97_GCR, 0); 287 delay(100); 288 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 289 delay(100); 290 acu_reg_write(sc, AC97_CAR, 0); 291 292 if (acu_wait_gsr(sc, GSR_PCR)) { 293 acu_reg_write(sc, AC97_GCR, 0); 294 delay(100); 295 pxa2x0_clkman_config(CKEN_AC97, false); 296 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 297 aprint_error_dev(self, "Primary codec not ready\n"); 298 return; 299 } 300 301 sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR; 302 sc->sc_dr.ds_len = 4; 303 304 sc->sc_codec_if = NULL; 305 sc->sc_host_if.arg = sc; 306 sc->sc_host_if.attach = acu_codec_attach; 307 sc->sc_host_if.read = acu_codec_read; 308 sc->sc_host_if.write = acu_codec_write; 309 sc->sc_host_if.reset = acu_codec_reset; 310 sc->sc_host_if.flags = NULL; 311 sc->sc_in_reset = 0; 312 sc->sc_dac_rate = sc->sc_adc_rate = 0; 313 314 if (ac97_attach(&sc->sc_host_if, sc->sc_dev)) { 315 aprint_error_dev(self, "Failed to attach primary codec\n"); 316 fail: 317 acu_reg_write(sc, AC97_GCR, 0); 318 delay(100); 319 pxa2x0_clkman_config(CKEN_AC97, false); 320 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 321 return; 322 } 323 324 if (auconv_create_encodings(acu_formats, ACU_NFORMATS, 325 &sc->sc_encodings)) { 326 aprint_error_dev(self, "Failed to create encodings\n"); 327 if (sc->sc_codec_if != NULL) 328 (sc->sc_codec_if->vtbl->detach)(sc->sc_codec_if); 329 goto fail; 330 } 331 332 sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, sc->sc_dev); 333 334 /* 335 * As a work-around for braindamage in the PXA250's AC97 controller 336 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until 337 * acu_open() is called. acu_close() also puts the controller into 338 * Cold Reset. 339 * 340 * While this won't necessarily prevent Rx FIFO overruns, it at least 341 * allows the user to recover by closing then re-opening the audio 342 * device. 343 */ 344 acu_reg_write(sc, AC97_GCR, 0); 345 sc->sc_in_reset = 1; 346 } 347 348 static int 349 acu_codec_attach(void *arg, struct ac97_codec_if *aci) 350 { 351 struct acu_softc *sc = arg; 352 353 sc->sc_codec_if = aci; 354 return (0); 355 } 356 357 static int 358 acu_codec_read(void *arg, u_int8_t codec_reg, u_int16_t *valp) 359 { 360 struct acu_softc *sc = arg; 361 u_int32_t val; 362 int s, reg, rv = 1; 363 364 /* 365 * If we're currently closed, return non-zero. The ac97 frontend 366 * will use its cached copy of the register instead. 367 */ 368 if (sc->sc_in_reset) 369 return (1); 370 371 reg = AC97_CODEC_BASE(0) + codec_reg * 2; 372 373 s = splaudio(); 374 375 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) 376 goto out_nocar; 377 378 val = acu_reg_read(sc, AC97_GSR); 379 val |= GSR_RDCS | GSR_SDONE; 380 acu_reg_write(sc, AC97_GSR, val); 381 382 /* 383 * Dummy read to initiate the real read access 384 */ 385 (void) acu_reg_read(sc, reg); 386 if (acu_wait_gsr(sc, GSR_SDONE)) 387 goto out; 388 389 (void) acu_reg_read(sc, reg); 390 if (acu_wait_gsr(sc, GSR_SDONE)) 391 goto out; 392 393 val = acu_reg_read(sc, AC97_GSR); 394 if (val & GSR_RDCS) 395 goto out; 396 397 *valp = acu_reg_read(sc, reg); 398 if (acu_wait_gsr(sc, GSR_SDONE)) 399 goto out; 400 401 rv = 0; 402 403 out: 404 acu_reg_write(sc, AC97_CAR, 0); 405 out_nocar: 406 splx(s); 407 delay(10); 408 return (rv); 409 } 410 411 static int 412 acu_codec_write(void *arg, u_int8_t codec_reg, u_int16_t val) 413 { 414 struct acu_softc *sc = arg; 415 u_int16_t rv; 416 int s; 417 418 /* 419 * If we're currently closed, chances are the user is just 420 * tweaking mixer settings. Pretend the write succeeded. 421 * The ac97 frontend will cache the value anyway, and it'll 422 * be written correctly when the driver is opened. 423 */ 424 if (sc->sc_in_reset) 425 return (0); 426 427 s = splaudio(); 428 429 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) { 430 splx(s); 431 return (1); 432 } 433 434 rv = acu_reg_read(sc, AC97_GSR); 435 rv |= GSR_RDCS | GSR_CDONE; 436 acu_reg_write(sc, AC97_GSR, rv); 437 438 acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val); 439 440 /* 441 * Wait for the write to complete 442 */ 443 (void) acu_wait_gsr(sc, GSR_CDONE); 444 acu_reg_write(sc, AC97_CAR, 0); 445 446 splx(s); 447 delay(10); 448 return (0); 449 } 450 451 static int 452 acu_codec_reset(void *arg) 453 { 454 struct acu_softc *sc = arg; 455 u_int32_t rv; 456 457 rv = acu_reg_read(sc, AC97_GCR); 458 acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST); 459 delay(100); 460 acu_reg_write(sc, AC97_GCR, rv); 461 delay(100); 462 463 if (acu_wait_gsr(sc, GSR_PCR)) { 464 aprint_error_dev(sc->sc_dev, 465 "acu_codec_reset: failed to ready after reset\n"); 466 return (ETIMEDOUT); 467 } 468 469 return (0); 470 } 471 472 static int 473 acu_intr(void *arg) 474 { 475 struct acu_softc *sc = arg; 476 u_int32_t gsr, reg; 477 478 gsr = acu_reg_read(sc, AC97_GSR); 479 480 /* 481 * Tx FIFO underruns are no big deal. Just log it and ignore and 482 * subsequent underruns until the next time acu_trigger_output() 483 * is called. 484 */ 485 if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) { 486 acu_reg_write(sc, AC97_POCR, 0); 487 reg = acu_reg_read(sc, AC97_POSR); 488 acu_reg_write(sc, AC97_POSR, reg); 489 aprint_error_dev(sc->sc_dev, "Tx PCM Fifo underrun\n"); 490 } 491 492 /* 493 * Rx FIFO overruns are a different story. See PAX250 Errata #125 494 * for the gory details. 495 * I don't see any way to gracefully recover from this problem, 496 * other than a issuing a Cold Reset in acu_close(). 497 * The best we can do here is to report the problem on the console. 498 */ 499 if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) { 500 acu_reg_write(sc, AC97_PICR, 0); 501 reg = acu_reg_read(sc, AC97_PISR); 502 acu_reg_write(sc, AC97_PISR, reg); 503 aprint_error_dev(sc->sc_dev, "Rx PCM Fifo overrun\n"); 504 } 505 506 return (1); 507 } 508 509 static int 510 acu_open(void *arg, int flags) 511 { 512 struct acu_softc *sc = arg; 513 514 /* 515 * Deassert Cold Reset 516 */ 517 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 518 delay(100); 519 acu_reg_write(sc, AC97_CAR, 0); 520 521 /* 522 * Wait for the primary codec to become ready 523 */ 524 if (acu_wait_gsr(sc, GSR_PCR)) 525 return (EIO); 526 sc->sc_in_reset = 0; 527 528 /* 529 * Restore the codec port settings 530 */ 531 sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if); 532 533 /* 534 * Need to reprogram the sample rates, since 'restore_ports' 535 * doesn't do it. 536 * 537 * XXX: These aren't the only two sample rate registers ... 538 */ 539 if (sc->sc_dac_rate) 540 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 541 AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate); 542 if (sc->sc_adc_rate) 543 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 544 AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate); 545 546 return (0); 547 } 548 549 static void 550 acu_close(void *arg) 551 { 552 struct acu_softc *sc = arg; 553 554 /* 555 * Make sure the hardware is quiescent 556 */ 557 acu_halt_output(sc); 558 acu_halt_input(sc); 559 delay(100); 560 561 /* Assert Cold Reset */ 562 acu_reg_write(sc, AC97_GCR, 0); 563 sc->sc_in_reset = 1; 564 } 565 566 static int 567 acu_query_encoding(void *arg, struct audio_encoding *fp) 568 { 569 struct acu_softc *sc = arg; 570 571 return (auconv_query_encoding(sc->sc_encodings, fp)); 572 } 573 574 static int 575 acu_set_params(void *arg, int setmode, int usemode, 576 audio_params_t *play, audio_params_t *rec, 577 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 578 { 579 struct acu_softc *sc = arg; 580 struct audio_params *p; 581 stream_filter_list_t *fil; 582 int mode, err; 583 584 for (mode = AUMODE_RECORD; mode != -1; 585 mode = (mode == AUMODE_RECORD) ? AUMODE_PLAY : -1) { 586 if ((setmode & mode) == 0) 587 continue; 588 589 p = (mode == AUMODE_PLAY) ? play : rec; 590 591 if (p->sample_rate < 4000 || p->sample_rate > 48000 || 592 (p->precision != 8 && p->precision != 16) || 593 (p->channels != 1 && p->channels != 2)) { 594 printf("acu_set_params: precision/channels botch\n"); 595 printf("acu_set_params: rate %d, prec %d, chan %d\n", 596 p->sample_rate, p->precision, p->channels); 597 return (EINVAL); 598 } 599 600 fil = (mode == AUMODE_PLAY) ? pfil : rfil; 601 err = auconv_set_converter(acu_formats, ACU_NFORMATS, 602 mode, p, true, fil); 603 if (err < 0) 604 return (EINVAL); 605 606 if (mode == AUMODE_PLAY) { 607 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 608 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 609 sc->sc_dac_rate = play->sample_rate; 610 } else { 611 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 612 AC97_REG_PCM_LR_ADC_RATE, &rec->sample_rate); 613 sc->sc_adc_rate = rec->sample_rate; 614 } 615 if (err) 616 return (EINVAL); 617 } 618 619 return (0); 620 } 621 622 static int 623 acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param) 624 { 625 626 return (blk & ~0x1f); 627 } 628 629 static int 630 acu_getdev(void *addr, struct audio_device *retp) 631 { 632 633 *retp = acu_device; 634 return (0); 635 } 636 637 static int 638 acu_mixer_set_port(void *arg, mixer_ctrl_t *cp) 639 { 640 struct acu_softc *sc = arg; 641 642 return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp)); 643 } 644 645 static int 646 acu_mixer_get_port(void *arg, mixer_ctrl_t *cp) 647 { 648 struct acu_softc *sc = arg; 649 650 return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp)); 651 } 652 653 static int 654 acu_query_devinfo(void *arg, mixer_devinfo_t *dip) 655 { 656 struct acu_softc *sc = arg; 657 658 return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip)); 659 } 660 661 static void * 662 acu_malloc(void *arg, int direction, size_t size, 663 struct malloc_type *pool, int flags) 664 { 665 struct acu_softc *sc = arg; 666 struct acu_dma *ad; 667 int error; 668 669 if ((ad = malloc(sizeof(*ad), pool, flags)) == NULL) 670 return (NULL); 671 672 if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer(M_NOWAIT)) == NULL) 673 goto error; 674 675 ad->ad_size = size; 676 677 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs, 678 ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_NOWAIT); 679 if (error) 680 goto free_xfer; 681 682 error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size, 683 &ad->ad_addr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 684 if (error) 685 goto free_dmamem; 686 687 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 688 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ad->ad_map); 689 if (error) 690 goto unmap_dmamem; 691 692 error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size, 693 NULL, BUS_DMA_NOWAIT); 694 if (error) { 695 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 696 unmap_dmamem: bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size); 697 free_dmamem: bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 698 free_xfer: pxa2x0_dmac_free_xfer(ad->ad_dx); 699 error: free(ad, pool); 700 return (NULL); 701 } 702 703 ad->ad_dx->dx_cookie = sc; 704 ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH; 705 ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4; 706 ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32; 707 708 ad->ad_next = sc->sc_dmas; 709 sc->sc_dmas = ad; 710 return (KERNADDR(ad)); 711 } 712 713 static void 714 acu_free(void *arg, void *ptr, struct malloc_type *pool) 715 { 716 struct acu_softc *sc = arg; 717 struct acu_dma *ad, **adp; 718 719 for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) { 720 if (KERNADDR(ad) == ptr) { 721 pxa2x0_dmac_abort_xfer(ad->ad_dx); 722 pxa2x0_dmac_free_xfer(ad->ad_dx); 723 ad->ad_segs[0].ds_len = ad->ad_size; /* XXX */ 724 bus_dmamap_unload(sc->sc_dmat, ad->ad_map); 725 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 726 bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size); 727 bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 728 *adp = ad->ad_next; 729 free(ad, pool); 730 return; 731 } 732 } 733 } 734 735 static size_t 736 acu_round_buffersize(void *arg, int direction, size_t size) 737 { 738 739 return (size); 740 } 741 742 static paddr_t 743 acu_mappage(void *arg, void *mem, off_t off, int prot) 744 { 745 struct acu_softc *sc = arg; 746 struct acu_dma *ad; 747 748 if (off < 0) 749 return (-1); 750 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != mem; ad = ad->ad_next) 751 ; 752 if (ad == NULL) 753 return (-1); 754 return (bus_dmamem_mmap(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, 755 off, prot, BUS_DMA_WAITOK)); 756 } 757 758 static int 759 acu_get_props(void *arg) 760 { 761 762 return (AUDIO_PROP_MMAP|AUDIO_PROP_INDEPENDENT|AUDIO_PROP_FULLDUPLEX); 763 } 764 765 static int 766 acu_halt_output(void *arg) 767 { 768 struct acu_softc *sc = arg; 769 int s; 770 771 s = splaudio(); 772 if (sc->sc_txdma) { 773 acu_reg_write(sc, AC97_POCR, 0); 774 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 775 pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx); 776 sc->sc_txdma = NULL; 777 } 778 splx(s); 779 return (0); 780 } 781 782 static int 783 acu_halt_input(void *arg) 784 { 785 struct acu_softc *sc = arg; 786 int s; 787 788 s = splaudio(); 789 if (sc->sc_rxdma) { 790 acu_reg_write(sc, AC97_PICR, 0); 791 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 792 pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx); 793 sc->sc_rxdma = NULL; 794 } 795 splx(s); 796 return (0); 797 } 798 799 static int 800 acu_trigger_output(void *arg, void *start, void *end, int blksize, 801 void (*tx_func)(void *), void *tx_arg, const audio_params_t *param) 802 { 803 struct acu_softc *sc = arg; 804 struct dmac_xfer *dx; 805 struct acu_dma *ad; 806 int rv; 807 808 if (sc->sc_txdma) 809 return (EBUSY); 810 811 sc->sc_txfunc = tx_func; 812 sc->sc_txarg = tx_arg; 813 814 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 815 ; 816 if (ad == NULL) { 817 printf("acu_trigger_output: bad addr %p\n", start); 818 return (EINVAL); 819 } 820 821 sc->sc_txdma = ad; 822 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 823 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 824 825 /* 826 * Fix up a looping DMA request. 827 * The 'done' function will be called for every 'blksize' bytes 828 * transferred by the DMA engine. 829 */ 830 dx = ad->ad_dx; 831 dx->dx_done = acu_tx_loop_segment; 832 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX; 833 dx->dx_flow = DMAC_FLOW_CTRL_DEST; 834 dx->dx_loop_notify = blksize; 835 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 836 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs; 837 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs; 838 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 839 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 840 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 841 842 rv = pxa2x0_dmac_start_xfer(dx); 843 if (rv == 0) { 844 /* 845 * XXX: We should only do this once the request has been 846 * loaded into a DMAC channel. 847 */ 848 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 849 acu_reg_write(sc, AC97_POCR, AC97_FEFIE); 850 } 851 852 return (rv); 853 } 854 855 static int 856 acu_trigger_input(void *arg, void *start, void *end, int blksize, 857 void (*rx_func)(void *), void *rx_arg, const audio_params_t *param) 858 { 859 struct acu_softc *sc = arg; 860 struct dmac_xfer *dx; 861 struct acu_dma *ad; 862 int rv; 863 864 if (sc->sc_rxdma) 865 return (EBUSY); 866 867 sc->sc_rxfunc = rx_func; 868 sc->sc_rxarg = rx_arg; 869 870 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 871 ; 872 if (ad == NULL) { 873 printf("acu_trigger_input: bad addr %p\n", start); 874 return (EINVAL); 875 } 876 877 sc->sc_rxdma = ad; 878 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 879 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 880 881 /* 882 * Fix up a looping DMA request. 883 * The 'done' function will be called for every 'blksize' bytes 884 * transferred by the DMA engine. 885 */ 886 dx = ad->ad_dx; 887 dx->dx_done = acu_rx_loop_segment; 888 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX; 889 dx->dx_flow = DMAC_FLOW_CTRL_SRC; 890 dx->dx_loop_notify = blksize; 891 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 892 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs; 893 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs; 894 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 895 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 896 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 897 898 rv = pxa2x0_dmac_start_xfer(dx); 899 900 if (rv == 0) { 901 /* 902 * XXX: We should only do this once the request has been 903 * loaded into a DMAC channel. 904 */ 905 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 906 acu_reg_write(sc, AC97_PICR, AC97_FEFIE); 907 } 908 909 return (rv); 910 } 911 912 static void 913 acu_tx_loop_segment(struct dmac_xfer *dx, int status) 914 { 915 struct acu_softc *sc = dx->dx_cookie; 916 struct acu_dma *ad; 917 int s; 918 919 if ((ad = sc->sc_txdma) == NULL) 920 panic("acu_tx_loop_segment: bad TX dma descriptor!"); 921 922 if (ad->ad_dx != dx) 923 panic("acu_tx_loop_segment: xfer mismatch!"); 924 925 if (status) { 926 aprint_error_dev(sc->sc_dev, 927 "acu_tx_loop_segment: non-zero completion status %d\n", 928 status); 929 } 930 931 s = splaudio(); 932 (sc->sc_txfunc)(sc->sc_txarg); 933 splx(s); 934 } 935 936 static void 937 acu_rx_loop_segment(struct dmac_xfer *dx, int status) 938 { 939 struct acu_softc *sc = dx->dx_cookie; 940 struct acu_dma *ad; 941 int s; 942 943 if ((ad = sc->sc_rxdma) == NULL) 944 panic("acu_rx_loop_segment: bad RX dma descriptor!"); 945 946 if (ad->ad_dx != dx) 947 panic("acu_rx_loop_segment: xfer mismatch!"); 948 949 if (status) { 950 aprint_error_dev(sc->sc_dev, 951 "acu_rx_loop_segment: non-zero completion status %d\n", 952 status); 953 } 954 955 s = splaudio(); 956 (sc->sc_rxfunc)(sc->sc_rxarg); 957 splx(s); 958 } 959
Indexes created Wed Oct 01 18:09:54 GMT 2025