pxa2x0_gpio.c revision 1.1
1 /* $NetBSD: pxa2x0_gpio.c,v 1.1 2003/06/05 13:48:27 scw Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include "opt_pxa2x0_gpio.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <machine/intr.h> 46 #include <machine/bus.h> 47 48 #include <arm/xscale/pxa2x0reg.h> 49 #include <arm/xscale/pxa2x0var.h> 50 #include <arm/xscale/pxa2x0_gpio.h> 51 52 #include "locators.h" 53 54 struct gpio_irq_handler { 55 int (*gh_func)(void *); 56 void *gh_arg; 57 int gh_spl; 58 u_int gh_gpio; 59 }; 60 61 struct pxagpio_softc { 62 struct device sc_dev; 63 bus_space_tag_t sc_bust; 64 bus_space_handle_t sc_bush; 65 void *sc_irqcookie[3]; 66 u_int32_t sc_mask[3]; 67 #ifdef PXAGPIO_HAS_GPION_INTRS 68 struct gpio_irq_handler *sc_handlers[GPIO_NPINS]; 69 #else 70 struct gpio_irq_handler *sc_handlers[2]; 71 #endif 72 }; 73 74 static int pxagpio_match(struct device *, struct cfdata *, void *); 75 static void pxagpio_attach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(pxagpio, sizeof(struct pxagpio_softc), 78 pxagpio_match, pxagpio_attach, NULL, NULL); 79 80 static struct pxagpio_softc *pxagpio_softc; 81 static vaddr_t pxagpio_regs; 82 #define GPIO_BOOTSTRAP_REG(reg) \ 83 (*((volatile u_int32_t *)(pxagpio_regs + (reg)))) 84 85 static int gpio_intr0(void *); 86 static int gpio_intr1(void *); 87 #ifdef PXAGPIO_HAS_GPION_INTRS 88 static int gpio_dispatch(struct pxagpio_softc *, int); 89 static int gpio_intrN(void *); 90 #endif 91 92 static __inline u_int32_t 93 pxagpio_reg_read(struct pxagpio_softc *sc, int reg) 94 { 95 if (__predict_true(sc != NULL)) 96 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 97 else 98 if (pxagpio_regs) 99 return (GPIO_BOOTSTRAP_REG(reg)); 100 panic("pxagpio_reg_read: not bootstrapped"); 101 } 102 103 static __inline void 104 pxagpio_reg_write(struct pxagpio_softc *sc, int reg, u_int32_t val) 105 { 106 if (__predict_true(sc != NULL)) 107 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 108 else 109 if (pxagpio_regs) 110 GPIO_BOOTSTRAP_REG(reg) = val; 111 else 112 panic("pxagpio_reg_write: not bootstrapped"); 113 return; 114 } 115 116 static int 117 pxagpio_match(struct device *parent, struct cfdata *cf, void *aux) 118 { 119 struct pxaip_attach_args *pxa = aux; 120 121 if (pxagpio_softc != NULL || pxa->pxa_addr != PXA2X0_GPIO_BASE) 122 return (0); 123 124 pxa->pxa_size = PXA2X0_GPIO_SIZE; 125 126 return (1); 127 } 128 129 void 130 pxagpio_attach(struct device *parent, struct device *self, void *aux) 131 { 132 struct pxagpio_softc *sc = (struct pxagpio_softc *)self; 133 struct pxaip_attach_args *pxa = aux; 134 135 sc->sc_bust = pxa->pxa_iot; 136 137 aprint_normal(": GPIO Controller\n"); 138 139 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 140 &sc->sc_bush)) { 141 aprint_error("%s: Can't map registers!\n", sc->sc_dev.dv_xname); 142 return; 143 } 144 145 memset(sc->sc_handlers, 0, sizeof(sc->sc_handlers)); 146 147 /* 148 * Disable all GPIO interrupts 149 */ 150 pxagpio_reg_write(sc, GPIO_GRER0, 0); 151 pxagpio_reg_write(sc, GPIO_GRER1, 0); 152 pxagpio_reg_write(sc, GPIO_GRER2, 0); 153 pxagpio_reg_write(sc, GPIO_GFER0, 0); 154 pxagpio_reg_write(sc, GPIO_GFER1, 0); 155 pxagpio_reg_write(sc, GPIO_GFER2, 0); 156 pxagpio_reg_write(sc, GPIO_GEDR0, ~0); 157 pxagpio_reg_write(sc, GPIO_GEDR1, ~0); 158 pxagpio_reg_write(sc, GPIO_GEDR2, ~0); 159 160 #ifdef PXAGPIO_HAS_GPION_INTRS 161 sc->sc_irqcookie[2] = pxa2x0_intr_establish(PXA2X0_INT_GPION, IPL_BIO, 162 gpio_intrN, sc); 163 if (sc->sc_irqcookie[2] == NULL) { 164 aprint_error("%s: failed to hook main GPIO interrupt\n", 165 sc->sc_dev.dv_xname); 166 return; 167 } 168 #endif 169 170 sc->sc_irqcookie[0] = sc->sc_irqcookie[1] = NULL; 171 172 pxagpio_softc = sc; 173 } 174 175 void 176 pxa2x0_gpio_bootstrap(vaddr_t gpio_regs) 177 { 178 179 pxagpio_regs = gpio_regs; 180 } 181 182 void * 183 pxa2x0_gpio_intr_establish(u_int gpio, int level, int spl, int (*func)(void *), 184 void *arg) 185 { 186 struct pxagpio_softc *sc = pxagpio_softc; 187 struct gpio_irq_handler *gh; 188 u_int32_t bit, reg; 189 190 #ifdef DEBUG 191 #ifdef PXAGPIO_HAS_GPION_INTRS 192 if (gpio >= GPIO_NPINS) 193 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 194 #else 195 if (gpio > 1) 196 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 197 #endif 198 #endif 199 200 if (!GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(gpio))) 201 panic("pxa2x0_gpio_intr_establish: Pin %d not GPIO_IN", gpio); 202 203 switch (level) { 204 case IST_EDGE_FALLING: 205 case IST_EDGE_RISING: 206 case IST_EDGE_BOTH: 207 break; 208 209 default: 210 panic("pxa2x0_gpio_intr_establish: bad level: %d", level); 211 break; 212 } 213 214 if (sc->sc_handlers[gpio] != NULL) 215 panic("pxa2x0_gpio_intr_establish: illegal shared interrupt"); 216 217 MALLOC(gh, struct gpio_irq_handler *, sizeof(struct gpio_irq_handler), 218 M_DEVBUF, M_NOWAIT); 219 220 gh->gh_func = func; 221 gh->gh_arg = arg; 222 gh->gh_spl = spl; 223 gh->gh_gpio = gpio; 224 sc->sc_handlers[gpio] = gh; 225 226 if (gpio == 0) { 227 KDASSERT(sc->sc_irqcookie[0] == NULL); 228 sc->sc_irqcookie[0] = pxa2x0_intr_establish(PXA2X0_INT_GPIO0, 229 spl, gpio_intr0, sc); 230 KDASSERT(sc->sc_irqcookie[0]); 231 } else 232 if (gpio == 1) { 233 KDASSERT(sc->sc_irqcookie[1] == NULL); 234 sc->sc_irqcookie[1] = pxa2x0_intr_establish(PXA2X0_INT_GPIO1, 235 spl, gpio_intr1, sc); 236 KDASSERT(sc->sc_irqcookie[1]); 237 } 238 239 bit = GPIO_BIT(gpio); 240 sc->sc_mask[GPIO_BANK(gpio)] |= bit; 241 242 switch (level) { 243 case IST_EDGE_FALLING: 244 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 245 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 246 break; 247 248 case IST_EDGE_RISING: 249 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 250 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 251 break; 252 253 case IST_EDGE_BOTH: 254 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 255 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 256 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 257 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 258 break; 259 } 260 261 return (gh); 262 } 263 264 void 265 pxa2x0_gpio_intr_disestablish(void *cookie) 266 { 267 struct pxagpio_softc *sc = pxagpio_softc; 268 struct gpio_irq_handler *gh = cookie; 269 u_int32_t bit, reg; 270 271 bit = GPIO_BIT(gh->gh_gpio); 272 273 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio)); 274 reg &= ~bit; 275 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg); 276 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio)); 277 reg &= ~bit; 278 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg); 279 280 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gh->gh_gpio), bit); 281 282 sc->sc_mask[GPIO_BANK(gh->gh_gpio)] &= ~bit; 283 sc->sc_handlers[gh->gh_gpio] = NULL; 284 285 if (gh->gh_gpio == 0) { 286 #if 0 287 pxa2x0_intr_disestablish(sc->sc_irqcookie[0]); 288 sc->sc_irqcookie[0] = NULL; 289 #else 290 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0"); 291 #endif 292 } else 293 if (gh->gh_gpio == 1) { 294 #if 0 295 pxa2x0_intr_disestablish(sc->sc_irqcookie[1]); 296 sc->sc_irqcookie[0] = NULL; 297 #else 298 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0"); 299 #endif 300 } 301 302 FREE(gh, M_DEVBUF); 303 } 304 305 static int 306 gpio_intr0(void *arg) 307 { 308 struct pxagpio_softc *sc = arg; 309 310 #ifdef DIAGNOSTIC 311 if (sc->sc_handlers[0] == NULL) { 312 printf("%s: stray GPIO#0 edge interrupt\n", 313 sc->sc_dev.dv_xname); 314 return (0); 315 } 316 #endif 317 318 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 0), 319 GPIO_BIT(0)); 320 321 return ((sc->sc_handlers[0]->gh_func)(sc->sc_handlers[0]->gh_arg)); 322 } 323 324 static int 325 gpio_intr1(void *arg) 326 { 327 struct pxagpio_softc *sc = arg; 328 329 #ifdef DIAGNOSTIC 330 if (sc->sc_handlers[1] == NULL) { 331 printf("%s: stray GPIO#1 edge interrupt\n", 332 sc->sc_dev.dv_xname); 333 return (0); 334 } 335 #endif 336 337 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 1), 338 GPIO_BIT(1)); 339 340 return ((sc->sc_handlers[1]->gh_func)(sc->sc_handlers[1]->gh_arg)); 341 } 342 343 #ifdef PXAGPIO_HAS_GPION_INTRS 344 static int 345 gpio_dispatch(struct pxagpio_softc *sc, int gpio_base) 346 { 347 struct gpio_irq_handler **ghp, *gh; 348 int i, s, handled, pins; 349 u_int32_t gedr, mask; 350 int bank; 351 352 /* Fetch bitmap of pending interrupts on this GPIO bank */ 353 gedr = pxagpio_reg_read(sc, GPIO_REG(GPIO_GEDR0, gpio_base)); 354 355 /* Don't handle GPIO 0/1 here */ 356 if (gpio_base == 0) 357 gedr &= ~(GPIO_BIT(0) | GPIO_BIT(1)); 358 359 /* Bail early if there are no pending interrupts in this bank */ 360 if (gedr == 0) 361 return (0); 362 363 /* Acknowledge pending interrupts. */ 364 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio_base), gedr); 365 366 bank = GPIO_BANK(gpio_base); 367 368 /* 369 * We're only interested in those for which we have a handler 370 * registered 371 */ 372 #ifdef DEBUG 373 if ((gedr & sc->sc_mask[bank]) == 0) { 374 printf("%s: stray GPIO interrupt. Bank %d, GEDR 0x%08x, mask 0x%08x\n", 375 sc->sc_dev.dv_xname, bank, gedr, sc->sc_mask[bank]); 376 return (1); /* XXX: Pretend we dealt with it */ 377 } 378 #endif 379 380 gedr &= sc->sc_mask[bank]; 381 ghp = &sc->sc_handlers[gpio_base]; 382 pins = (gpio_base < 64) ? 32 : 17; 383 handled = 0; 384 385 for (i = 0, mask = 1; i < pins && gedr; i++, ghp++, mask <<= 1) { 386 if ((gedr & mask) == 0) 387 continue; 388 gedr &= ~mask; 389 390 if ((gh = *ghp) == NULL) { 391 printf("%s: unhandled GPIO interrupt. GPIO#%d\n", 392 sc->sc_dev.dv_xname, gpio_base + i); 393 continue; 394 } 395 396 s = _splraise(gh->gh_spl); 397 handled |= (gh->gh_func)(gh->gh_arg); 398 splx(s); 399 } 400 401 return (handled); 402 } 403 404 static int 405 gpio_intrN(void *arg) 406 { 407 struct pxagpio_softc *sc = arg; 408 int handled; 409 410 handled = gpio_dispatch(sc, 0); 411 handled |= gpio_dispatch(sc, 32); 412 handled |= gpio_dispatch(sc, 64); 413 414 return (handled); 415 } 416 #endif /* PXAGPIO_HAS_GPION_INTRS */ 417 418 u_int 419 pxa2x0_gpio_get_function(u_int gpio) 420 { 421 struct pxagpio_softc *sc = pxagpio_softc; 422 u_int32_t rv, io; 423 424 KDASSERT(gpio < GPIO_NPINS); 425 426 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) >> GPIO_FN_SHIFT(gpio); 427 rv = GPIO_FN(rv); 428 429 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)); 430 if (io & GPIO_BIT(gpio)) 431 rv |= GPIO_OUT; 432 433 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio)); 434 if (io & GPIO_BIT(gpio)) 435 rv |= GPIO_SET; 436 437 return (rv); 438 } 439 440 u_int 441 pxa2x0_gpio_set_function(u_int gpio, u_int fn) 442 { 443 struct pxagpio_softc *sc = pxagpio_softc; 444 u_int32_t rv, bit; 445 u_int oldfn; 446 447 KDASSERT(gpio < GPIO_NPINS); 448 449 oldfn = pxa2x0_gpio_get_function(gpio); 450 451 if (GPIO_FN(fn) == GPIO_FN(oldfn) && 452 GPIO_FN_IS_OUT(fn) == GPIO_FN_IS_OUT(oldfn)) { 453 /* 454 * The pin's function is not changing. 455 * For Alternate Functions and GPIO input, we can just 456 * return now. 457 * For GPIO output pins, check the initial state is 458 * the same. 459 * 460 * Return 'fn' instead of 'oldfn' so the caller can 461 * reliably detect that we didn't change anything. 462 * (The initial state might be different for non- 463 * GPIO output pins). 464 */ 465 if (!GPIO_IS_GPIO_OUT(fn) || 466 GPIO_FN_IS_SET(fn) == GPIO_FN_IS_SET(oldfn)) 467 return (fn); 468 } 469 470 /* 471 * See section 4.1.3.7 of the PXA2x0 Developer's Manual for 472 * the correct procedure for changing GPIO pin functions. 473 */ 474 475 bit = GPIO_BIT(gpio); 476 477 /* 478 * 1. Configure the correct set/clear state of the pin 479 */ 480 if (GPIO_FN_IS_SET(fn)) 481 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit); 482 else 483 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit); 484 485 /* 486 * 2. Configure the pin as an input or output as appropriate 487 */ 488 rv = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit; 489 if (GPIO_FN_IS_OUT(fn)) 490 rv |= bit; 491 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), rv); 492 493 /* 494 * 3. Configure the pin's function 495 */ 496 bit = GPIO_FN_MASK << GPIO_FN_SHIFT(gpio); 497 fn = GPIO_FN(fn) << GPIO_FN_SHIFT(gpio); 498 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) & ~bit; 499 pxagpio_reg_write(sc, GPIO_FN_REG(gpio), rv | fn); 500 501 return (oldfn); 502 } 503
Indexes created Mon Sep 29 13:09:55 GMT 2025