pxa2x0_gpio.c revision 1.16.14.1
1 /* $NetBSD: pxa2x0_gpio.c,v 1.16.14.1 2017/08/28 17:51:32 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.16.14.1 2017/08/28 17:51:32 skrll Exp $"); 40 41 #include "gpio.h" 42 #include "opt_pxa2x0_gpio.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <machine/intr.h> 50 #include <sys/bus.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_gpio.h> 56 57 #include "locators.h" 58 59 #include <sys/gpio.h> 60 #include <dev/gpio/gpiovar.h> 61 62 struct gpio_irq_handler { 63 struct gpio_irq_handler *gh_next; 64 int (*gh_func)(void *); 65 void *gh_arg; 66 int gh_spl; 67 u_int gh_gpio; 68 int gh_level; 69 }; 70 71 struct pxagpio_softc { 72 device_t sc_dev; 73 bus_space_tag_t sc_bust; 74 bus_space_handle_t sc_bush; 75 void *sc_irqcookie[4]; 76 uint32_t sc_mask[4]; 77 #ifdef PXAGPIO_HAS_GPION_INTRS 78 struct gpio_irq_handler *sc_handlers[GPIO_NPINS]; 79 #else 80 struct gpio_irq_handler *sc_handlers[2]; 81 #endif 82 struct gpio_chipset_tag sc_gpio_gc; 83 gpio_pin_t sc_gpio_pins[GPIO_NPINS]; 84 }; 85 86 static int pxagpio_match(device_t, cfdata_t, void *); 87 static void pxagpio_attach(device_t, device_t, void *); 88 89 #if NGPIO > 0 90 static int pxa2x0_gpio_pin_read(void *, int); 91 static void pxa2x0_gpio_pin_write(void *, int, int); 92 static void pxa2x0_gpio_pin_ctl(void *, int, int); 93 #endif 94 95 CFATTACH_DECL_NEW(pxagpio, sizeof(struct pxagpio_softc), 96 pxagpio_match, pxagpio_attach, NULL, NULL); 97 98 static struct pxagpio_softc *pxagpio_softc; 99 static vaddr_t pxagpio_regs; 100 #define GPIO_BOOTSTRAP_REG(reg) \ 101 (*((volatile uint32_t *)(pxagpio_regs + (reg)))) 102 103 static int gpio_intr0(void *); 104 static int gpio_intr1(void *); 105 #ifdef PXAGPIO_HAS_GPION_INTRS 106 static int gpio_dispatch(struct pxagpio_softc *, int); 107 static int gpio_intrN(void *); 108 #endif 109 110 static inline uint32_t 111 pxagpio_reg_read(struct pxagpio_softc *sc, int reg) 112 { 113 if (__predict_true(sc != NULL)) 114 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 115 else 116 if (pxagpio_regs) 117 return (GPIO_BOOTSTRAP_REG(reg)); 118 panic("pxagpio_reg_read: not bootstrapped"); 119 } 120 121 static inline void 122 pxagpio_reg_write(struct pxagpio_softc *sc, int reg, uint32_t val) 123 { 124 if (__predict_true(sc != NULL)) 125 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 126 else 127 if (pxagpio_regs) 128 GPIO_BOOTSTRAP_REG(reg) = val; 129 else 130 panic("pxagpio_reg_write: not bootstrapped"); 131 return; 132 } 133 134 static int 135 pxagpio_match(device_t parent, cfdata_t cf, void *aux) 136 { 137 struct pxaip_attach_args *pxa = aux; 138 139 if (pxagpio_softc != NULL || pxa->pxa_addr != PXA2X0_GPIO_BASE) 140 return (0); 141 142 pxa->pxa_size = PXA2X0_GPIO_SIZE; 143 144 return (1); 145 } 146 147 static void 148 pxagpio_attach(device_t parent, device_t self, void *aux) 149 { 150 struct pxagpio_softc *sc = device_private(self); 151 struct pxaip_attach_args *pxa = aux; 152 #if NGPIO > 0 153 struct gpiobus_attach_args gba; 154 int pin, maxpin; 155 u_int func; 156 #endif 157 158 sc->sc_dev = self; 159 sc->sc_bust = pxa->pxa_iot; 160 161 aprint_normal(": GPIO Controller\n"); 162 163 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 164 &sc->sc_bush)) { 165 aprint_error_dev(self, "Can't map registers!\n"); 166 return; 167 } 168 169 pxagpio_regs = (vaddr_t)bus_space_vaddr(sc->sc_bust, sc->sc_bush); 170 171 memset(sc->sc_handlers, 0, sizeof(sc->sc_handlers)); 172 173 /* 174 * Disable all GPIO interrupts 175 */ 176 pxagpio_reg_write(sc, GPIO_GRER0, 0); 177 pxagpio_reg_write(sc, GPIO_GRER1, 0); 178 pxagpio_reg_write(sc, GPIO_GRER2, 0); 179 pxagpio_reg_write(sc, GPIO_GFER0, 0); 180 pxagpio_reg_write(sc, GPIO_GFER1, 0); 181 pxagpio_reg_write(sc, GPIO_GFER2, 0); 182 pxagpio_reg_write(sc, GPIO_GEDR0, ~0); 183 pxagpio_reg_write(sc, GPIO_GEDR1, ~0); 184 pxagpio_reg_write(sc, GPIO_GEDR2, ~0); 185 #ifdef CPU_XSCALE_PXA270 186 if (CPU_IS_PXA270) { 187 pxagpio_reg_write(sc, GPIO_GRER3, 0); 188 pxagpio_reg_write(sc, GPIO_GFER3, 0); 189 pxagpio_reg_write(sc, GPIO_GEDR3, ~0); 190 } 191 #endif 192 193 #ifdef PXAGPIO_HAS_GPION_INTRS 194 sc->sc_irqcookie[2] = pxa2x0_intr_establish(PXA2X0_INT_GPION, IPL_BIO, 195 gpio_intrN, sc); 196 if (sc->sc_irqcookie[2] == NULL) { 197 aprint_error_dev(self, "failed to hook main GPIO interrupt\n"); 198 return; 199 } 200 #endif 201 202 sc->sc_irqcookie[0] = sc->sc_irqcookie[1] = NULL; 203 204 pxagpio_softc = sc; 205 #if NGPIO > 0 206 #if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270) 207 maxpin = CPU_IS_PXA270 ? PXA270_GPIO_NPINS : PXA250_GPIO_NPINS; 208 #else 209 maxpin = GPIO_NPINS; 210 #endif 211 for (pin = 0; pin < maxpin; ++pin) { 212 213 sc->sc_gpio_pins[pin].pin_num = pin; 214 func = pxa2x0_gpio_get_function(pin); 215 216 if (GPIO_IS_GPIO(func)) { 217 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 218 GPIO_PIN_OUTPUT; 219 sc->sc_gpio_pins[pin].pin_state = 220 pxa2x0_gpio_pin_read(sc, pin); 221 } else { 222 sc->sc_gpio_pins[pin].pin_caps = 0; 223 sc->sc_gpio_pins[pin].pin_state = 0; 224 } 225 } 226 227 /* create controller tag */ 228 sc->sc_gpio_gc.gp_cookie = sc; 229 sc->sc_gpio_gc.gp_pin_read = pxa2x0_gpio_pin_read; 230 sc->sc_gpio_gc.gp_pin_write = pxa2x0_gpio_pin_write; 231 sc->sc_gpio_gc.gp_pin_ctl = pxa2x0_gpio_pin_ctl; 232 233 gba.gba_gc = &sc->sc_gpio_gc; 234 gba.gba_pins = sc->sc_gpio_pins; 235 gba.gba_npins = maxpin; 236 237 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 238 #else 239 aprint_normal_dev(sc->sc_dev, "no GPIO configured in kernel\n"); 240 #endif 241 } 242 243 void 244 pxa2x0_gpio_bootstrap(vaddr_t gpio_regs) 245 { 246 247 pxagpio_regs = gpio_regs; 248 } 249 250 void * 251 pxa2x0_gpio_intr_establish(u_int gpio, int level, int spl, int (*func)(void *), 252 void *arg) 253 { 254 struct pxagpio_softc *sc = pxagpio_softc; 255 struct gpio_irq_handler *gh; 256 uint32_t bit, reg; 257 258 #ifdef PXAGPIO_HAS_GPION_INTRS 259 if (gpio >= GPIO_NPINS) 260 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 261 #else 262 if (gpio > 1) 263 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 264 #endif 265 266 if (!GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(gpio))) 267 panic("pxa2x0_gpio_intr_establish: Pin %d not GPIO_IN", gpio); 268 269 switch (level) { 270 case IST_EDGE_FALLING: 271 case IST_EDGE_RISING: 272 case IST_EDGE_BOTH: 273 break; 274 275 default: 276 panic("pxa2x0_gpio_intr_establish: bad level: %d", level); 277 break; 278 } 279 280 if (sc->sc_handlers[gpio] != NULL) 281 panic("pxa2x0_gpio_intr_establish: illegal shared interrupt"); 282 283 gh = malloc(sizeof(struct gpio_irq_handler), M_DEVBUF, M_NOWAIT); 284 285 gh->gh_func = func; 286 gh->gh_arg = arg; 287 gh->gh_spl = spl; 288 gh->gh_gpio = gpio; 289 gh->gh_level = level; 290 gh->gh_next = sc->sc_handlers[gpio]; 291 sc->sc_handlers[gpio] = gh; 292 293 if (gpio == 0) { 294 KDASSERT(sc->sc_irqcookie[0] == NULL); 295 sc->sc_irqcookie[0] = pxa2x0_intr_establish(PXA2X0_INT_GPIO0, 296 spl, gpio_intr0, sc); 297 KDASSERT(sc->sc_irqcookie[0]); 298 } else 299 if (gpio == 1) { 300 KDASSERT(sc->sc_irqcookie[1] == NULL); 301 sc->sc_irqcookie[1] = pxa2x0_intr_establish(PXA2X0_INT_GPIO1, 302 spl, gpio_intr1, sc); 303 KDASSERT(sc->sc_irqcookie[1]); 304 } 305 306 bit = GPIO_BIT(gpio); 307 sc->sc_mask[GPIO_BANK(gpio)] |= bit; 308 309 switch (level) { 310 case IST_EDGE_FALLING: 311 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 312 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 313 break; 314 315 case IST_EDGE_RISING: 316 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 317 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 318 break; 319 320 case IST_EDGE_BOTH: 321 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 322 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 323 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 324 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 325 break; 326 } 327 328 return (gh); 329 } 330 331 void 332 pxa2x0_gpio_intr_disestablish(void *cookie) 333 { 334 struct pxagpio_softc *sc = pxagpio_softc; 335 struct gpio_irq_handler *gh = cookie; 336 uint32_t bit, reg; 337 338 bit = GPIO_BIT(gh->gh_gpio); 339 340 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio)); 341 reg &= ~bit; 342 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg); 343 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio)); 344 reg &= ~bit; 345 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg); 346 347 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gh->gh_gpio), bit); 348 349 sc->sc_mask[GPIO_BANK(gh->gh_gpio)] &= ~bit; 350 sc->sc_handlers[gh->gh_gpio] = NULL; 351 352 if (gh->gh_gpio == 0) { 353 #if 0 354 pxa2x0_intr_disestablish(sc->sc_irqcookie[0]); 355 sc->sc_irqcookie[0] = NULL; 356 #else 357 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0"); 358 #endif 359 } else 360 if (gh->gh_gpio == 1) { 361 #if 0 362 pxa2x0_intr_disestablish(sc->sc_irqcookie[1]); 363 sc->sc_irqcookie[1] = NULL; 364 #else 365 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#1"); 366 #endif 367 } 368 369 free(gh, M_DEVBUF); 370 } 371 372 static int 373 gpio_intr0(void *arg) 374 { 375 struct pxagpio_softc *sc = arg; 376 377 #ifdef DIAGNOSTIC 378 if (sc->sc_handlers[0] == NULL) { 379 aprint_error_dev(sc->sc_dev, "stray GPIO#0 edge interrupt\n"); 380 return (0); 381 } 382 #endif 383 384 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 0), 385 GPIO_BIT(0)); 386 387 return ((sc->sc_handlers[0]->gh_func)(sc->sc_handlers[0]->gh_arg)); 388 } 389 390 static int 391 gpio_intr1(void *arg) 392 { 393 struct pxagpio_softc *sc = arg; 394 395 #ifdef DIAGNOSTIC 396 if (sc->sc_handlers[1] == NULL) { 397 aprint_error_dev(sc->sc_dev, "stray GPIO#1 edge interrupt\n"); 398 return (0); 399 } 400 #endif 401 402 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 1), 403 GPIO_BIT(1)); 404 405 return ((sc->sc_handlers[1]->gh_func)(sc->sc_handlers[1]->gh_arg)); 406 } 407 408 #ifdef PXAGPIO_HAS_GPION_INTRS 409 static int 410 gpio_dispatch(struct pxagpio_softc *sc, int gpio_base) 411 { 412 struct gpio_irq_handler **ghp, *gh; 413 int i, s, nhandled, handled, pins; 414 uint32_t gedr, mask; 415 int bank; 416 417 /* Fetch bitmap of pending interrupts on this GPIO bank */ 418 gedr = pxagpio_reg_read(sc, GPIO_REG(GPIO_GEDR0, gpio_base)); 419 420 /* Don't handle GPIO 0/1 here */ 421 if (gpio_base == 0) 422 gedr &= ~(GPIO_BIT(0) | GPIO_BIT(1)); 423 424 /* Bail early if there are no pending interrupts in this bank */ 425 if (gedr == 0) 426 return (0); 427 428 /* Acknowledge pending interrupts. */ 429 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio_base), gedr); 430 431 bank = GPIO_BANK(gpio_base); 432 433 /* 434 * We're only interested in those for which we have a handler 435 * registered 436 */ 437 #ifdef DEBUG 438 if ((gedr & sc->sc_mask[bank]) == 0) { 439 aprint_error_dev(sc->sc_dev, 440 "stray GPIO interrupt. Bank %d, GEDR 0x%08x, mask 0x%08x\n", 441 bank, gedr, sc->sc_mask[bank]); 442 return (1); /* XXX: Pretend we dealt with it */ 443 } 444 #endif 445 446 gedr &= sc->sc_mask[bank]; 447 ghp = &sc->sc_handlers[gpio_base]; 448 if (CPU_IS_PXA270) 449 pins = (gpio_base < 96) ? 32 : 25; 450 else 451 pins = (gpio_base < 64) ? 32 : 17; 452 handled = 0; 453 454 for (i = 0, mask = 1; i < pins && gedr; i++, ghp++, mask <<= 1) { 455 if ((gedr & mask) == 0) 456 continue; 457 gedr &= ~mask; 458 459 if ((gh = *ghp) == NULL) { 460 aprint_error_dev(sc->sc_dev, 461 "unhandled GPIO interrupt. GPIO#%d\n", 462 gpio_base + i); 463 continue; 464 } 465 466 s = _splraise(gh->gh_spl); 467 do { 468 nhandled = (gh->gh_func)(gh->gh_arg); 469 handled |= nhandled; 470 gh = gh->gh_next; 471 } while (gh != NULL); 472 splx(s); 473 } 474 475 return (handled); 476 } 477 478 static int 479 gpio_intrN(void *arg) 480 { 481 struct pxagpio_softc *sc = arg; 482 int handled; 483 484 handled = gpio_dispatch(sc, 0); 485 handled |= gpio_dispatch(sc, 32); 486 handled |= gpio_dispatch(sc, 64); 487 if (CPU_IS_PXA270) 488 handled |= gpio_dispatch(sc, 96); 489 return (handled); 490 } 491 #endif /* PXAGPIO_HAS_GPION_INTRS */ 492 493 u_int 494 pxa2x0_gpio_get_function(u_int gpio) 495 { 496 struct pxagpio_softc *sc = pxagpio_softc; 497 uint32_t rv, io; 498 499 KDASSERT(gpio < GPIO_NPINS); 500 501 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) >> GPIO_FN_SHIFT(gpio); 502 rv = GPIO_FN(rv); 503 504 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)); 505 if (io & GPIO_BIT(gpio)) 506 rv |= GPIO_OUT; 507 508 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio)); 509 if (io & GPIO_BIT(gpio)) 510 rv |= GPIO_SET; 511 512 return (rv); 513 } 514 515 u_int 516 pxa2x0_gpio_set_function(u_int gpio, u_int fn) 517 { 518 struct pxagpio_softc *sc = pxagpio_softc; 519 uint32_t rv, bit; 520 u_int oldfn; 521 522 KDASSERT(gpio < GPIO_NPINS); 523 524 oldfn = pxa2x0_gpio_get_function(gpio); 525 526 if (GPIO_FN(fn) == GPIO_FN(oldfn) && 527 GPIO_FN_IS_OUT(fn) == GPIO_FN_IS_OUT(oldfn)) { 528 /* 529 * The pin's function is not changing. 530 * For Alternate Functions and GPIO input, we can just 531 * return now. 532 * For GPIO output pins, check the initial state is 533 * the same. 534 * 535 * Return 'fn' instead of 'oldfn' so the caller can 536 * reliably detect that we didn't change anything. 537 * (The initial state might be different for non- 538 * GPIO output pins). 539 */ 540 if (!GPIO_IS_GPIO_OUT(fn) || 541 GPIO_FN_IS_SET(fn) == GPIO_FN_IS_SET(oldfn)) 542 return (fn); 543 } 544 545 /* 546 * See section 4.1.3.7 of the PXA2x0 Developer's Manual for 547 * the correct procedure for changing GPIO pin functions. 548 */ 549 550 bit = GPIO_BIT(gpio); 551 552 /* 553 * 1. Configure the correct set/clear state of the pin 554 */ 555 if (GPIO_FN_IS_SET(fn)) 556 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit); 557 else 558 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit); 559 560 /* 561 * 2. Configure the pin as an input or output as appropriate 562 */ 563 rv = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit; 564 if (GPIO_FN_IS_OUT(fn)) 565 rv |= bit; 566 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), rv); 567 568 /* 569 * 3. Configure the pin's function 570 */ 571 bit = GPIO_FN_MASK << GPIO_FN_SHIFT(gpio); 572 fn = GPIO_FN(fn) << GPIO_FN_SHIFT(gpio); 573 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) & ~bit; 574 pxagpio_reg_write(sc, GPIO_FN_REG(gpio), rv | fn); 575 576 return (oldfn); 577 } 578 579 /* 580 * Quick function to read pin value 581 */ 582 int 583 pxa2x0_gpio_get_bit(u_int gpio) 584 { 585 struct pxagpio_softc *sc = pxagpio_softc; 586 int bit; 587 588 bit = GPIO_BIT(gpio); 589 if (pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio)) & bit) 590 return 1; 591 else 592 return 0; 593 } 594 595 /* 596 * Quick function to set pin to 1 597 */ 598 void 599 pxa2x0_gpio_set_bit(u_int gpio) 600 { 601 struct pxagpio_softc *sc = pxagpio_softc; 602 int bit; 603 604 bit = GPIO_BIT(gpio); 605 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit); 606 } 607 608 /* 609 * Quick function to set pin to 0 610 */ 611 void 612 pxa2x0_gpio_clear_bit(u_int gpio) 613 { 614 struct pxagpio_softc *sc = pxagpio_softc; 615 int bit; 616 617 bit = GPIO_BIT(gpio); 618 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit); 619 } 620 621 /* 622 * Quick function to change pin direction 623 */ 624 void 625 pxa2x0_gpio_set_dir(u_int gpio, int dir) 626 { 627 struct pxagpio_softc *sc = pxagpio_softc; 628 int bit; 629 uint32_t reg; 630 631 bit = GPIO_BIT(gpio); 632 633 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit; 634 if (GPIO_FN_IS_OUT(dir)) 635 reg |= bit; 636 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), reg); 637 } 638 639 /* 640 * Quick function to clear interrupt status on a pin 641 * GPIO pins may be toggle in an interrupt and we dont want 642 * extra spurious interrupts to occur. 643 * Suppose this causes a slight race if a key is pressed while 644 * the interrupt handler is running. (yes this is for the keyboard driver) 645 */ 646 void 647 pxa2x0_gpio_clear_intr(u_int gpio) 648 { 649 struct pxagpio_softc *sc = pxagpio_softc; 650 int bit; 651 652 bit = GPIO_BIT(gpio); 653 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio), bit); 654 } 655 656 /* 657 * Quick function to mask (disable) a GPIO interrupt 658 */ 659 void 660 pxa2x0_gpio_intr_mask(void *v) 661 { 662 struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v; 663 664 pxa2x0_gpio_set_intr_level(gh->gh_gpio, IPL_NONE); 665 } 666 667 /* 668 * Quick function to unmask (enable) a GPIO interrupt 669 */ 670 void 671 pxa2x0_gpio_intr_unmask(void *v) 672 { 673 struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v; 674 675 pxa2x0_gpio_set_intr_level(gh->gh_gpio, gh->gh_level); 676 } 677 678 /* 679 * Configure the edge sensitivity of interrupt pins 680 */ 681 void 682 pxa2x0_gpio_set_intr_level(u_int gpio, int level) 683 { 684 struct pxagpio_softc *sc = pxagpio_softc; 685 uint32_t bit; 686 uint32_t gfer; 687 uint32_t grer; 688 int s; 689 690 s = splhigh(); 691 692 bit = GPIO_BIT(gpio); 693 gfer = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 694 grer = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 695 696 switch (level) { 697 case IST_NONE: 698 gfer &= ~bit; 699 grer &= ~bit; 700 break; 701 case IST_EDGE_FALLING: 702 gfer |= bit; 703 grer &= ~bit; 704 break; 705 case IST_EDGE_RISING: 706 gfer &= ~bit; 707 grer |= bit; 708 break; 709 case IST_EDGE_BOTH: 710 gfer |= bit; 711 grer |= bit; 712 break; 713 default: 714 panic("pxa2x0_gpio_set_intr_level: bad level: %d", level); 715 break; 716 } 717 718 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), gfer); 719 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), grer); 720 721 splx(s); 722 } 723 724 #if NGPIO > 0 725 /* GPIO support functions */ 726 static int 727 pxa2x0_gpio_pin_read(void *arg, int pin) 728 { 729 return pxa2x0_gpio_get_bit(pin); 730 } 731 732 static void 733 pxa2x0_gpio_pin_write(void *arg, int pin, int value) 734 { 735 if (value == GPIO_PIN_HIGH) { 736 pxa2x0_gpio_set_bit(pin); 737 } else { 738 pxa2x0_gpio_clear_bit(pin); 739 } 740 } 741 742 static void 743 pxa2x0_gpio_pin_ctl(void *arg, int pin, int flags) 744 { 745 if (flags & GPIO_PIN_OUTPUT) { 746 pxa2x0_gpio_set_function(pin, GPIO_OUT); 747 } else if (flags & GPIO_PIN_INPUT) { 748 pxa2x0_gpio_set_function(pin, GPIO_IN); 749 } 750 } 751 #endif 752 753 #if defined(CPU_XSCALE_PXA250) 754 /* 755 * Configurations of GPIO for PXA25x 756 */ 757 struct pxa2x0_gpioconf pxa25x_com_btuart_gpioconf[] = { 758 { 42, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTRXD */ 759 { 43, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTTXD */ 760 761 #if 0 /* optional */ 762 { 44, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTCTS */ 763 { 45, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTRTS */ 764 #endif 765 766 { -1 } 767 }; 768 769 struct pxa2x0_gpioconf pxa25x_com_ffuart_gpioconf[] = { 770 { 34, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 771 772 #if 0 /* optional */ 773 { 35, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* CTS */ 774 { 36, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* DCD */ 775 { 37, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* DSR */ 776 { 38, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* RI */ 777 #endif 778 779 { 39, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */ 780 781 #if 0 /* optional */ 782 { 40, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* DTR */ 783 { 41, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* RTS */ 784 #endif 785 786 { -1 } 787 }; 788 789 struct pxa2x0_gpioconf pxa25x_com_hwuart_gpioconf[] = { 790 #if 0 /* We can select and/or. */ 791 { 42, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWRXD */ 792 { 49, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* HWRXD */ 793 794 { 43, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWTXD */ 795 { 48, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* HWTXD */ 796 797 #if 0 /* optional */ 798 { 44, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWCST */ 799 { 51, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWCST */ 800 801 { 45, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWRST */ 802 { 52, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWRST */ 803 #endif 804 #endif 805 806 { -1 } 807 }; 808 809 struct pxa2x0_gpioconf pxa25x_com_stuart_gpioconf[] = { 810 { 46, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* RXD */ 811 { 47, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* TXD */ 812 { -1 } 813 }; 814 815 struct pxa2x0_gpioconf pxa25x_i2c_gpioconf[] = { 816 { -1 } 817 }; 818 819 struct pxa2x0_gpioconf pxa25x_i2s_gpioconf[] = { 820 { 28, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* BITCLK */ 821 { 29, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN */ 822 { 30, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SDATA_OUT */ 823 { 31, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYNC */ 824 { 32, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYSCLK */ 825 { -1 } 826 }; 827 828 struct pxa2x0_gpioconf pxa25x_pcic_gpioconf[] = { 829 { 48, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPOE */ 830 { 49, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPWE */ 831 { 50, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOR */ 832 { 51, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOW */ 833 834 #if 0 /* We can select and/or. */ 835 { 52, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE1 */ 836 { 53, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE2 */ 837 #endif 838 839 { 54, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* pSKTSEL */ 840 { 55, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPREG */ 841 { 56, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nPWAIT */ 842 { 57, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nIOIS16 */ 843 { -1 } 844 }; 845 846 struct pxa2x0_gpioconf pxa25x_pxaacu_gpioconf[] = { 847 { 28, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BITCLK */ 848 { 30, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SDATA_OUT */ 849 { 31, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SYNC */ 850 851 #if 0 /* We can select and/or. */ 852 { 29, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 853 { 32, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN1 */ 854 #endif 855 856 { -1 } 857 }; 858 859 struct pxa2x0_gpioconf pxa25x_pxamci_gpioconf[] = { 860 #if 0 /* We can select and/or. */ 861 { 6, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */ 862 { 53, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */ 863 { 54, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */ 864 865 { 8, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS0 */ 866 { 34, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* MMCCS0 */ 867 { 67, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS0 */ 868 869 { 9, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */ 870 { 39, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */ 871 { 68, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */ 872 #endif 873 874 { -1 } 875 }; 876 #endif 877 878 #if defined(CPU_XSCALE_PXA270) 879 /* 880 * Configurations of GPIO for PXA27x 881 */ 882 struct pxa2x0_gpioconf pxa27x_com_btuart_gpioconf[] = { 883 { 42, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTRXD */ 884 { 43, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTTXD */ 885 886 #if 0 /* optional */ 887 { 44, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTCTS */ 888 { 45, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTRTS */ 889 #endif 890 891 { -1 } 892 }; 893 894 struct pxa2x0_gpioconf pxa27x_com_ffuart_gpioconf[] = { 895 #if 0 /* We can select and/or. */ 896 { 16, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */ 897 { 37, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */ 898 { 39, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */ 899 { 83, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */ 900 { 99, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */ 901 902 { 19, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */ 903 { 33, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 904 { 34, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 905 { 41, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 906 { 53, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 907 { 85, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */ 908 { 96, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */ 909 { 102, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */ 910 911 { 9, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */ 912 { 26, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */ 913 { 35, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFCTS */ 914 { 100, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */ 915 916 { 27, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */ 917 { 41, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFRTS */ 918 { 83, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */ 919 { 98, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */ 920 921 { 40, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFDTR */ 922 { 82, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFDTR */ 923 924 { 36, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFDCD */ 925 926 { 33, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* FFDSR */ 927 { 37, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFDSR */ 928 929 { 38, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRI */ 930 #endif 931 { -1 } 932 }; 933 934 struct pxa2x0_gpioconf pxa27x_com_stuart_gpioconf[] = { 935 { 46, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* STD_RXD */ 936 { 47, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* STD_TXD */ 937 { -1 } 938 }; 939 940 struct pxa2x0_gpioconf pxa27x_i2c_gpioconf[] = { 941 { 117, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SCL */ 942 { 118, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDA */ 943 { -1 } 944 }; 945 946 struct pxa2x0_gpioconf pxa27x_i2s_gpioconf[] = { 947 { 28, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_BITCLK */ 948 { 29, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* I2S_SDATA_IN */ 949 { 30, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SDATA_OUT */ 950 { 31, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SYNC */ 951 { 113, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SYSCLK */ 952 { -1 } 953 }; 954 955 struct pxa2x0_gpioconf pxa27x_ohci_gpioconf[] = { 956 #if 0 /* We can select and/or. */ 957 { 88, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* USBHPWR1 */ 958 { 89, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* USBHPEN1 */ 959 { 119, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* USBHPWR2 */ 960 { 120, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* USBHPEN2 */ 961 #endif 962 { -1 } 963 }; 964 965 struct pxa2x0_gpioconf pxa27x_pcic_gpioconf[] = { 966 { 48, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPOE */ 967 { 49, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPWE */ 968 { 50, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOR */ 969 { 51, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOW */ 970 { 55, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPREG */ 971 { 56, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nPWAIT */ 972 { 57, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nIOIS16 */ 973 974 #if 0 /* We can select and/or. */ 975 { 85, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */ 976 { 86, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */ 977 { 102, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */ 978 979 { 54, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE2 */ 980 { 78, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE2 */ 981 { 105, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE2 */ 982 983 { 79, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* pSKTSEL */ 984 { 104, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* pSKTSEL */ 985 #endif 986 987 { -1 } 988 }; 989 990 struct pxa2x0_gpioconf pxa27x_pxaacu_gpioconf[] = { 991 { 28, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BITCLK */ 992 { 30, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SDATA_OUT */ 993 994 #if 0 /* We can select and/or. */ 995 { 31, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SYNC */ 996 { 94, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYNC */ 997 998 { 29, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 999 { 116, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN0 */ 1000 1001 { 32, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN1 */ 1002 { 99, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN1 */ 1003 1004 { 95, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* RESET_n */ 1005 { 113, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* RESET_n */ 1006 #endif 1007 1008 { -1 } 1009 }; 1010 1011 struct pxa2x0_gpioconf pxa27x_pxamci_gpioconf[] = { 1012 { 32, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* MMCLK */ 1013 { 92, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<0> */ 1014 { 109, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<1> */ 1015 { 110, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<2>/MMCCS<0> */ 1016 { 111, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<3>/MMCCS<1> */ 1017 { 112, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMCMD */ 1018 1019 { -1 } 1020 }; 1021 #endif 1022 1023 void 1024 pxa2x0_gpio_config(struct pxa2x0_gpioconf **conflist) 1025 { 1026 int i, j; 1027 1028 for (i = 0; conflist[i] != NULL; i++) 1029 for (j = 0; conflist[i][j].pin != -1; j++) 1030 pxa2x0_gpio_set_function(conflist[i][j].pin, 1031 conflist[i][j].value); 1032 } 1033
Indexes created Wed Oct 15 16:09:53 GMT 2025