pxa2x0_gpio.c revision 1.3
1 /* $NetBSD: pxa2x0_gpio.c,v 1.3 2005/07/04 00:42:37 bsh Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.3 2005/07/04 00:42:37 bsh Exp $"); 40 41 #include "opt_pxa2x0_gpio.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 48 #include <machine/intr.h> 49 #include <machine/bus.h> 50 51 #include <arm/xscale/pxa2x0cpu.h> 52 #include <arm/xscale/pxa2x0reg.h> 53 #include <arm/xscale/pxa2x0var.h> 54 #include <arm/xscale/pxa2x0_gpio.h> 55 56 #include "locators.h" 57 58 struct gpio_irq_handler { 59 int (*gh_func)(void *); 60 void *gh_arg; 61 int gh_spl; 62 u_int gh_gpio; 63 }; 64 65 struct pxagpio_softc { 66 struct device sc_dev; 67 bus_space_tag_t sc_bust; 68 bus_space_handle_t sc_bush; 69 void *sc_irqcookie[4]; 70 u_int32_t sc_mask[4]; 71 #ifdef PXAGPIO_HAS_GPION_INTRS 72 struct gpio_irq_handler *sc_handlers[GPIO_NPINS]; 73 #else 74 struct gpio_irq_handler *sc_handlers[2]; 75 #endif 76 }; 77 78 static int pxagpio_match(struct device *, struct cfdata *, void *); 79 static void pxagpio_attach(struct device *, struct device *, void *); 80 81 CFATTACH_DECL(pxagpio, sizeof(struct pxagpio_softc), 82 pxagpio_match, pxagpio_attach, NULL, NULL); 83 84 static struct pxagpio_softc *pxagpio_softc; 85 static vaddr_t pxagpio_regs; 86 #define GPIO_BOOTSTRAP_REG(reg) \ 87 (*((volatile u_int32_t *)(pxagpio_regs + (reg)))) 88 89 static int gpio_intr0(void *); 90 static int gpio_intr1(void *); 91 #ifdef PXAGPIO_HAS_GPION_INTRS 92 static int gpio_dispatch(struct pxagpio_softc *, int); 93 static int gpio_intrN(void *); 94 #endif 95 96 static __inline u_int32_t 97 pxagpio_reg_read(struct pxagpio_softc *sc, int reg) 98 { 99 if (__predict_true(sc != NULL)) 100 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 101 else 102 if (pxagpio_regs) 103 return (GPIO_BOOTSTRAP_REG(reg)); 104 panic("pxagpio_reg_read: not bootstrapped"); 105 } 106 107 static __inline void 108 pxagpio_reg_write(struct pxagpio_softc *sc, int reg, u_int32_t val) 109 { 110 if (__predict_true(sc != NULL)) 111 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 112 else 113 if (pxagpio_regs) 114 GPIO_BOOTSTRAP_REG(reg) = val; 115 else 116 panic("pxagpio_reg_write: not bootstrapped"); 117 return; 118 } 119 120 static int 121 pxagpio_match(struct device *parent, struct cfdata *cf, void *aux) 122 { 123 struct pxaip_attach_args *pxa = aux; 124 125 if (pxagpio_softc != NULL || pxa->pxa_addr != PXA2X0_GPIO_BASE) 126 return (0); 127 128 pxa->pxa_size = PXA2X0_GPIO_SIZE; 129 130 return (1); 131 } 132 133 void 134 pxagpio_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct pxagpio_softc *sc = (struct pxagpio_softc *)self; 137 struct pxaip_attach_args *pxa = aux; 138 139 sc->sc_bust = pxa->pxa_iot; 140 141 aprint_normal(": GPIO Controller\n"); 142 143 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 144 &sc->sc_bush)) { 145 aprint_error("%s: Can't map registers!\n", sc->sc_dev.dv_xname); 146 return; 147 } 148 149 pxagpio_regs = (vaddr_t)bus_space_vaddr(sc->sc_bust, sc->sc_bush); 150 151 memset(sc->sc_handlers, 0, sizeof(sc->sc_handlers)); 152 153 /* 154 * Disable all GPIO interrupts 155 */ 156 pxagpio_reg_write(sc, GPIO_GRER0, 0); 157 pxagpio_reg_write(sc, GPIO_GRER1, 0); 158 pxagpio_reg_write(sc, GPIO_GRER2, 0); 159 pxagpio_reg_write(sc, GPIO_GFER0, 0); 160 pxagpio_reg_write(sc, GPIO_GFER1, 0); 161 pxagpio_reg_write(sc, GPIO_GFER2, 0); 162 pxagpio_reg_write(sc, GPIO_GEDR0, ~0); 163 pxagpio_reg_write(sc, GPIO_GEDR1, ~0); 164 pxagpio_reg_write(sc, GPIO_GEDR2, ~0); 165 #ifdef CPU_XSCALE_PXA270 166 if (CPU_IS_PXA270) { 167 pxagpio_reg_write(sc, GPIO_GRER3, 0); 168 pxagpio_reg_write(sc, GPIO_GFER3, 0); 169 pxagpio_reg_write(sc, GPIO_GEDR3, ~0); 170 } 171 #endif 172 173 #ifdef PXAGPIO_HAS_GPION_INTRS 174 sc->sc_irqcookie[2] = pxa2x0_intr_establish(PXA2X0_INT_GPION, IPL_BIO, 175 gpio_intrN, sc); 176 if (sc->sc_irqcookie[2] == NULL) { 177 aprint_error("%s: failed to hook main GPIO interrupt\n", 178 sc->sc_dev.dv_xname); 179 return; 180 } 181 #endif 182 183 sc->sc_irqcookie[0] = sc->sc_irqcookie[1] = NULL; 184 185 pxagpio_softc = sc; 186 } 187 188 void 189 pxa2x0_gpio_bootstrap(vaddr_t gpio_regs) 190 { 191 192 pxagpio_regs = gpio_regs; 193 } 194 195 void * 196 pxa2x0_gpio_intr_establish(u_int gpio, int level, int spl, int (*func)(void *), 197 void *arg) 198 { 199 struct pxagpio_softc *sc = pxagpio_softc; 200 struct gpio_irq_handler *gh; 201 u_int32_t bit, reg; 202 203 #ifdef DEBUG 204 #ifdef PXAGPIO_HAS_GPION_INTRS 205 if (gpio >= GPIO_NPINS) 206 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 207 #else 208 if (gpio > 1) 209 panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio); 210 #endif 211 #endif 212 213 if (!GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(gpio))) 214 panic("pxa2x0_gpio_intr_establish: Pin %d not GPIO_IN", gpio); 215 216 switch (level) { 217 case IST_EDGE_FALLING: 218 case IST_EDGE_RISING: 219 case IST_EDGE_BOTH: 220 break; 221 222 default: 223 panic("pxa2x0_gpio_intr_establish: bad level: %d", level); 224 break; 225 } 226 227 if (sc->sc_handlers[gpio] != NULL) 228 panic("pxa2x0_gpio_intr_establish: illegal shared interrupt"); 229 230 MALLOC(gh, struct gpio_irq_handler *, sizeof(struct gpio_irq_handler), 231 M_DEVBUF, M_NOWAIT); 232 233 gh->gh_func = func; 234 gh->gh_arg = arg; 235 gh->gh_spl = spl; 236 gh->gh_gpio = gpio; 237 sc->sc_handlers[gpio] = gh; 238 239 if (gpio == 0) { 240 KDASSERT(sc->sc_irqcookie[0] == NULL); 241 sc->sc_irqcookie[0] = pxa2x0_intr_establish(PXA2X0_INT_GPIO0, 242 spl, gpio_intr0, sc); 243 KDASSERT(sc->sc_irqcookie[0]); 244 } else 245 if (gpio == 1) { 246 KDASSERT(sc->sc_irqcookie[1] == NULL); 247 sc->sc_irqcookie[1] = pxa2x0_intr_establish(PXA2X0_INT_GPIO1, 248 spl, gpio_intr1, sc); 249 KDASSERT(sc->sc_irqcookie[1]); 250 } 251 252 bit = GPIO_BIT(gpio); 253 sc->sc_mask[GPIO_BANK(gpio)] |= bit; 254 255 switch (level) { 256 case IST_EDGE_FALLING: 257 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 258 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 259 break; 260 261 case IST_EDGE_RISING: 262 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 263 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 264 break; 265 266 case IST_EDGE_BOTH: 267 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio)); 268 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit); 269 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio)); 270 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit); 271 break; 272 } 273 274 return (gh); 275 } 276 277 void 278 pxa2x0_gpio_intr_disestablish(void *cookie) 279 { 280 struct pxagpio_softc *sc = pxagpio_softc; 281 struct gpio_irq_handler *gh = cookie; 282 u_int32_t bit, reg; 283 284 bit = GPIO_BIT(gh->gh_gpio); 285 286 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio)); 287 reg &= ~bit; 288 pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg); 289 reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio)); 290 reg &= ~bit; 291 pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg); 292 293 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gh->gh_gpio), bit); 294 295 sc->sc_mask[GPIO_BANK(gh->gh_gpio)] &= ~bit; 296 sc->sc_handlers[gh->gh_gpio] = NULL; 297 298 if (gh->gh_gpio == 0) { 299 #if 0 300 pxa2x0_intr_disestablish(sc->sc_irqcookie[0]); 301 sc->sc_irqcookie[0] = NULL; 302 #else 303 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0"); 304 #endif 305 } else 306 if (gh->gh_gpio == 1) { 307 #if 0 308 pxa2x0_intr_disestablish(sc->sc_irqcookie[1]); 309 sc->sc_irqcookie[0] = NULL; 310 #else 311 panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0"); 312 #endif 313 } 314 315 FREE(gh, M_DEVBUF); 316 } 317 318 static int 319 gpio_intr0(void *arg) 320 { 321 struct pxagpio_softc *sc = arg; 322 323 #ifdef DIAGNOSTIC 324 if (sc->sc_handlers[0] == NULL) { 325 printf("%s: stray GPIO#0 edge interrupt\n", 326 sc->sc_dev.dv_xname); 327 return (0); 328 } 329 #endif 330 331 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 0), 332 GPIO_BIT(0)); 333 334 return ((sc->sc_handlers[0]->gh_func)(sc->sc_handlers[0]->gh_arg)); 335 } 336 337 static int 338 gpio_intr1(void *arg) 339 { 340 struct pxagpio_softc *sc = arg; 341 342 #ifdef DIAGNOSTIC 343 if (sc->sc_handlers[1] == NULL) { 344 printf("%s: stray GPIO#1 edge interrupt\n", 345 sc->sc_dev.dv_xname); 346 return (0); 347 } 348 #endif 349 350 bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 1), 351 GPIO_BIT(1)); 352 353 return ((sc->sc_handlers[1]->gh_func)(sc->sc_handlers[1]->gh_arg)); 354 } 355 356 #ifdef PXAGPIO_HAS_GPION_INTRS 357 static int 358 gpio_dispatch(struct pxagpio_softc *sc, int gpio_base) 359 { 360 struct gpio_irq_handler **ghp, *gh; 361 int i, s, handled, pins; 362 u_int32_t gedr, mask; 363 int bank; 364 365 /* Fetch bitmap of pending interrupts on this GPIO bank */ 366 gedr = pxagpio_reg_read(sc, GPIO_REG(GPIO_GEDR0, gpio_base)); 367 368 /* Don't handle GPIO 0/1 here */ 369 if (gpio_base == 0) 370 gedr &= ~(GPIO_BIT(0) | GPIO_BIT(1)); 371 372 /* Bail early if there are no pending interrupts in this bank */ 373 if (gedr == 0) 374 return (0); 375 376 /* Acknowledge pending interrupts. */ 377 pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio_base), gedr); 378 379 bank = GPIO_BANK(gpio_base); 380 381 /* 382 * We're only interested in those for which we have a handler 383 * registered 384 */ 385 #ifdef DEBUG 386 if ((gedr & sc->sc_mask[bank]) == 0) { 387 printf("%s: stray GPIO interrupt. Bank %d, GEDR 0x%08x, mask 0x%08x\n", 388 sc->sc_dev.dv_xname, bank, gedr, sc->sc_mask[bank]); 389 return (1); /* XXX: Pretend we dealt with it */ 390 } 391 #endif 392 393 gedr &= sc->sc_mask[bank]; 394 ghp = &sc->sc_handlers[gpio_base]; 395 if (CPU_IS_PXA270) 396 pins = (gpio_base < 96) ? 32 : 25; 397 else 398 pins = (gpio_base < 64) ? 32 : 17; 399 handled = 0; 400 401 for (i = 0, mask = 1; i < pins && gedr; i++, ghp++, mask <<= 1) { 402 if ((gedr & mask) == 0) 403 continue; 404 gedr &= ~mask; 405 406 if ((gh = *ghp) == NULL) { 407 printf("%s: unhandled GPIO interrupt. GPIO#%d\n", 408 sc->sc_dev.dv_xname, gpio_base + i); 409 continue; 410 } 411 412 s = _splraise(gh->gh_spl); 413 handled |= (gh->gh_func)(gh->gh_arg); 414 splx(s); 415 } 416 417 return (handled); 418 } 419 420 static int 421 gpio_intrN(void *arg) 422 { 423 struct pxagpio_softc *sc = arg; 424 int handled; 425 426 handled = gpio_dispatch(sc, 0); 427 handled |= gpio_dispatch(sc, 32); 428 handled |= gpio_dispatch(sc, 64); 429 if (CPU_IS_PXA270) 430 handled |= gpio_dispatch(sc, 96); 431 return (handled); 432 } 433 #endif /* PXAGPIO_HAS_GPION_INTRS */ 434 435 u_int 436 pxa2x0_gpio_get_function(u_int gpio) 437 { 438 struct pxagpio_softc *sc = pxagpio_softc; 439 u_int32_t rv, io; 440 441 KDASSERT(gpio < GPIO_NPINS); 442 443 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) >> GPIO_FN_SHIFT(gpio); 444 rv = GPIO_FN(rv); 445 446 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)); 447 if (io & GPIO_BIT(gpio)) 448 rv |= GPIO_OUT; 449 450 io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio)); 451 if (io & GPIO_BIT(gpio)) 452 rv |= GPIO_SET; 453 454 return (rv); 455 } 456 457 u_int 458 pxa2x0_gpio_set_function(u_int gpio, u_int fn) 459 { 460 struct pxagpio_softc *sc = pxagpio_softc; 461 u_int32_t rv, bit; 462 u_int oldfn; 463 464 KDASSERT(gpio < GPIO_NPINS); 465 466 oldfn = pxa2x0_gpio_get_function(gpio); 467 468 if (GPIO_FN(fn) == GPIO_FN(oldfn) && 469 GPIO_FN_IS_OUT(fn) == GPIO_FN_IS_OUT(oldfn)) { 470 /* 471 * The pin's function is not changing. 472 * For Alternate Functions and GPIO input, we can just 473 * return now. 474 * For GPIO output pins, check the initial state is 475 * the same. 476 * 477 * Return 'fn' instead of 'oldfn' so the caller can 478 * reliably detect that we didn't change anything. 479 * (The initial state might be different for non- 480 * GPIO output pins). 481 */ 482 if (!GPIO_IS_GPIO_OUT(fn) || 483 GPIO_FN_IS_SET(fn) == GPIO_FN_IS_SET(oldfn)) 484 return (fn); 485 } 486 487 /* 488 * See section 4.1.3.7 of the PXA2x0 Developer's Manual for 489 * the correct procedure for changing GPIO pin functions. 490 */ 491 492 bit = GPIO_BIT(gpio); 493 494 /* 495 * 1. Configure the correct set/clear state of the pin 496 */ 497 if (GPIO_FN_IS_SET(fn)) 498 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit); 499 else 500 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit); 501 502 /* 503 * 2. Configure the pin as an input or output as appropriate 504 */ 505 rv = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit; 506 if (GPIO_FN_IS_OUT(fn)) 507 rv |= bit; 508 pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), rv); 509 510 /* 511 * 3. Configure the pin's function 512 */ 513 bit = GPIO_FN_MASK << GPIO_FN_SHIFT(gpio); 514 fn = GPIO_FN(fn) << GPIO_FN_SHIFT(gpio); 515 rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) & ~bit; 516 pxagpio_reg_write(sc, GPIO_FN_REG(gpio), rv | fn); 517 518 return (oldfn); 519 } 520
Indexes created Sun Sep 28 07:09:56 GMT 2025