pxa2x0_i2s.c revision 1.3
1 /* $NetBSD: pxa2x0_i2s.c,v 1.3 2007/03/04 05:59:38 christos Exp $ */ 2 /* $OpenBSD: pxa2x0_i2s.c,v 1.7 2006/04/04 11:45:40 pascoe Exp $ */ 3 4 /* 5 * Copyright (c) 2005 Christopher Pascoe <pascoe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_i2s.c,v 1.3 2007/03/04 05:59:38 christos Exp $"); 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/malloc.h> 27 28 #include <machine/bus.h> 29 30 #include <arm/xscale/pxa2x0reg.h> 31 #include <arm/xscale/pxa2x0var.h> 32 #include <arm/xscale/pxa2x0_gpio.h> 33 #include <arm/xscale/pxa2x0_i2s.h> 34 #include <arm/xscale/pxa2x0_dmac.h> 35 36 struct pxa2x0_i2s_dma { 37 struct pxa2x0_i2s_dma *next; 38 void *addr; 39 size_t size; 40 bus_dmamap_t map; 41 #define I2S_N_SEGS 1 42 bus_dma_segment_t segs[I2S_N_SEGS]; 43 int nsegs; 44 struct dmac_xfer *dx; 45 }; 46 47 static void pxa2x0_i2s_dmac_ointr(struct dmac_xfer *, int); 48 static void pxa2x0_i2s_dmac_iintr(struct dmac_xfer *, int); 49 50 void 51 pxa2x0_i2s_init(struct pxa2x0_i2s_softc *sc) 52 { 53 54 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SACR0, SACR0_RST); 55 delay(100); 56 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SACR0, 57 SACR0_BCKD | SACR0_SET_TFTH(7) | SACR0_SET_RFTH(7)); 58 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SACR1, 0); 59 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SADR, 0); 60 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SADIV, sc->sc_sadiv); 61 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SACR0, 62 SACR0_BCKD | SACR0_SET_TFTH(7) | SACR0_SET_RFTH(7) | SACR0_ENB); 63 } 64 65 int 66 pxa2x0_i2s_attach_sub(struct pxa2x0_i2s_softc *sc) 67 { 68 int rv; 69 70 rv = bus_space_map(sc->sc_iot, PXA2X0_I2S_BASE, PXA2X0_I2S_SIZE, 0, 71 &sc->sc_ioh); 72 if (rv) { 73 sc->sc_size = 0; 74 return 1; 75 } 76 77 sc->sc_dr.ds_addr = PXA2X0_I2S_BASE + I2S_SADR; 78 sc->sc_dr.ds_len = 4; 79 80 sc->sc_sadiv = SADIV_3_058MHz; 81 82 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size, 83 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 84 85 pxa2x0_gpio_set_function(28, GPIO_ALT_FN_1_OUT); /* I2S_BITCLK */ 86 pxa2x0_gpio_set_function(113, GPIO_ALT_FN_1_OUT); /* I2S_SYSCLK */ 87 pxa2x0_gpio_set_function(31, GPIO_ALT_FN_1_OUT); /* I2S_SYNC */ 88 pxa2x0_gpio_set_function(30, GPIO_ALT_FN_1_OUT); /* I2S_SDATA_OUT */ 89 pxa2x0_gpio_set_function(29, GPIO_ALT_FN_2_IN); /* I2S_SDATA_IN */ 90 91 pxa2x0_i2s_init(sc); 92 93 return 0; 94 } 95 96 void 97 pxa2x0_i2s_open(struct pxa2x0_i2s_softc *sc) 98 { 99 100 if (sc->sc_open++ == 0) { 101 pxa2x0_clkman_config(CKEN_I2S, 1); 102 } 103 } 104 105 void 106 pxa2x0_i2s_close(struct pxa2x0_i2s_softc *sc) 107 { 108 109 if (--sc->sc_open == 0) { 110 pxa2x0_clkman_config(CKEN_I2S, 0); 111 } 112 } 113 114 int 115 pxa2x0_i2s_detach_sub(struct pxa2x0_i2s_softc *sc) 116 { 117 118 if (sc->sc_size > 0) { 119 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 120 sc->sc_size = 0; 121 } 122 pxa2x0_clkman_config(CKEN_I2S, 0); 123 124 return 0; 125 } 126 127 void 128 pxa2x0_i2s_write(struct pxa2x0_i2s_softc *sc, uint32_t data) 129 { 130 131 if (sc->sc_open == 0) 132 return; 133 134 /* Clear intr and underrun bit if set. */ 135 if (bus_space_read_4(sc->sc_iot, sc->sc_ioh, I2S_SASR0) & SASR0_TUR) 136 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SAICR, SAICR_TUR); 137 138 /* Wait for transmit fifo to have space. */ 139 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, I2S_SASR0) & SASR0_TNF) 140 == 0) 141 continue; /* nothing */ 142 143 /* Queue data */ 144 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SADR, data); 145 } 146 147 void 148 pxa2x0_i2s_setspeed(struct pxa2x0_i2s_softc *sc, u_int *argp) 149 { 150 /* 151 * The available speeds are in the following table. 152 * Keep the speeds in increasing order. 153 */ 154 static const struct speed_struct { 155 int speed; 156 int div; 157 } speed_table[] = { 158 {8000, SADIV_513_25kHz}, 159 {11025, SADIV_702_75kHz}, 160 {16000, SADIV_1_026MHz}, 161 {22050, SADIV_1_405MHz}, 162 {44100, SADIV_2_836MHz}, 163 {48000, SADIV_3_058MHz}, 164 }; 165 const const int n = (int)__arraycount(speed_table); 166 u_int arg = (u_int)*argp; 167 int selected = -1; 168 int i; 169 170 if (arg < speed_table[0].speed) 171 selected = 0; 172 if (arg > speed_table[n - 1].speed) 173 selected = n - 1; 174 175 for (i = 1; selected == -1 && i < n; i++) { 176 if (speed_table[i].speed == arg) 177 selected = i; 178 else if (speed_table[i].speed > arg) { 179 int diff1, diff2; 180 181 diff1 = arg - speed_table[i - 1].speed; 182 diff2 = speed_table[i].speed - arg; 183 if (diff1 < diff2) 184 selected = i - 1; 185 else 186 selected = i; 187 } 188 } 189 190 if (selected == -1) 191 selected = 0; 192 193 *argp = speed_table[selected].speed; 194 195 sc->sc_sadiv = speed_table[selected].div; 196 bus_space_write_4(sc->sc_iot, sc->sc_ioh, I2S_SADIV, sc->sc_sadiv); 197 } 198 199 void * 200 pxa2x0_i2s_allocm(void *hdl, int direction, size_t size, 201 struct malloc_type *type, int flags) 202 { 203 struct pxa2x0_i2s_softc *sc = hdl; 204 struct pxa2x0_i2s_dma *p; 205 struct dmac_xfer *dx; 206 int error; 207 208 p = malloc(sizeof(*p), type, flags); 209 if (p == NULL) 210 return NULL; 211 212 dx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 213 if (dx == NULL) { 214 goto fail_alloc; 215 } 216 p->dx = dx; 217 218 p->size = size; 219 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, 0, p->segs, 220 I2S_N_SEGS, &p->nsegs, BUS_DMA_NOWAIT)) != 0) { 221 goto fail_xfer; 222 } 223 224 if ((error = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, size, 225 &p->addr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 226 goto fail_map; 227 } 228 229 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 230 BUS_DMA_NOWAIT, &p->map)) != 0) { 231 goto fail_create; 232 } 233 234 if ((error = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, size, NULL, 235 BUS_DMA_NOWAIT)) != 0) { 236 goto fail_load; 237 } 238 239 dx->dx_cookie = sc; 240 dx->dx_priority = DMAC_PRIORITY_NORMAL; 241 dx->dx_dev_width = DCMD_WIDTH_4; 242 dx->dx_burst_size = DCMD_SIZE_32; 243 244 p->next = sc->sc_dmas; 245 sc->sc_dmas = p; 246 247 return p->addr; 248 249 fail_load: 250 bus_dmamap_destroy(sc->sc_dmat, p->map); 251 fail_create: 252 bus_dmamem_unmap(sc->sc_dmat, p->addr, size); 253 fail_map: 254 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 255 fail_xfer: 256 pxa2x0_dmac_free_xfer(dx); 257 fail_alloc: 258 free(p, type); 259 return NULL; 260 } 261 262 void 263 pxa2x0_i2s_freem(void *hdl, void *ptr, struct malloc_type *type) 264 { 265 struct pxa2x0_i2s_softc *sc = hdl; 266 struct pxa2x0_i2s_dma **pp, *p; 267 268 for (pp = &(sc->sc_dmas); (p = *pp) != NULL; pp = &p->next) { 269 if (p->addr == ptr) { 270 pxa2x0_dmac_abort_xfer(p->dx); 271 pxa2x0_dmac_free_xfer(p->dx); 272 p->segs[0].ds_len = p->size; /* XXX */ 273 bus_dmamap_unload(sc->sc_dmat, p->map); 274 bus_dmamap_destroy(sc->sc_dmat, p->map); 275 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 276 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 277 278 *pp = p->next; 279 free(p, type); 280 return; 281 } 282 } 283 panic("pxa2x0_i2s_freem: trying to free unallocated memory"); 284 } 285 286 paddr_t 287 pxa2x0_i2s_mappage(void *hdl, void *mem, off_t off, int prot) 288 { 289 struct pxa2x0_i2s_softc *sc = hdl; 290 struct pxa2x0_i2s_dma *p; 291 292 if (off < 0) 293 return -1; 294 295 for (p = sc->sc_dmas; p && p->addr != mem; p = p->next) 296 continue; 297 if (p == NULL) 298 return -1; 299 300 if (off > p->size) 301 return -1; 302 303 return bus_dmamem_mmap(sc->sc_dmat, p->segs, p->nsegs, off, prot, 304 BUS_DMA_WAITOK); 305 } 306 307 int 308 pxa2x0_i2s_round_blocksize(void *hdl, int bs, int mode, 309 const struct audio_params *param) 310 { 311 312 /* Enforce individual DMA block size limit */ 313 if (bs > DCMD_LENGTH_MASK) 314 return (DCMD_LENGTH_MASK & ~0x03); 315 316 return (bs + 0x03) & ~0x03; /* 32-bit multiples */ 317 } 318 319 size_t 320 pxa2x0_i2s_round_buffersize(void *hdl, int direction, size_t bufsize) 321 { 322 323 return bufsize; 324 } 325 326 int 327 pxa2x0_i2s_halt_output(void *hdl) 328 { 329 struct pxa2x0_i2s_softc *sc = hdl; 330 int s; 331 332 s = splaudio(); 333 if (sc->sc_txdma) { 334 pxa2x0_dmac_abort_xfer(sc->sc_txdma->dx); 335 sc->sc_txdma = NULL; 336 } 337 splx(s); 338 339 return 0; 340 } 341 342 int 343 pxa2x0_i2s_halt_input(void *hdl) 344 { 345 struct pxa2x0_i2s_softc *sc = hdl; 346 int s; 347 348 s = splaudio(); 349 if (sc->sc_rxdma) { 350 pxa2x0_dmac_abort_xfer(sc->sc_rxdma->dx); 351 sc->sc_rxdma = NULL; 352 } 353 splx(s); 354 355 return 0; 356 } 357 358 int 359 pxa2x0_i2s_start_output(void *hdl, void *block, int bsize, 360 void (*tx_func)(void *), void *tx_arg) 361 { 362 struct pxa2x0_i2s_softc *sc = hdl; 363 struct pxa2x0_i2s_dma *p; 364 struct dmac_xfer *dx; 365 int rv; 366 367 if (sc->sc_txdma) 368 return EBUSY; 369 370 sc->sc_txfunc = tx_func; 371 sc->sc_txarg = tx_arg; 372 373 /* Find mapping which contains block completely */ 374 for (p = sc->sc_dmas; p && (((void *)block < p->addr) || 375 ((void *)block + bsize > p->addr + p->size)); p = p->next) 376 continue; /* Nothing */ 377 378 if (p == NULL) { 379 printf("pxa2x0_i2s_start_output: request with bad start " 380 "address: %p, size: %d)\n", block, bsize); 381 return ENXIO; 382 } 383 sc->sc_txdma = p; 384 385 p->segs[0].ds_addr = p->map->dm_segs[0].ds_addr 386 + ((void *)block - p->addr); 387 p->segs[0].ds_len = bsize; 388 389 dx = p->dx; 390 dx->dx_done = pxa2x0_i2s_dmac_ointr; 391 dx->dx_peripheral = DMAC_PERIPH_I2STX; 392 dx->dx_flow = DMAC_FLOW_CTRL_DEST; 393 dx->dx_loop_notify = DMAC_DONT_LOOP; 394 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 395 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = p->nsegs; 396 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = p->segs; 397 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 398 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 399 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 400 401 /* Start DMA */ 402 rv = pxa2x0_dmac_start_xfer(dx); 403 404 return rv; 405 } 406 407 int 408 pxa2x0_i2s_start_input(void *hdl, void *block, int bsize, 409 void (*rx_func)(void *), void *rx_arg) 410 { 411 struct pxa2x0_i2s_softc *sc = hdl; 412 struct pxa2x0_i2s_dma *p; 413 struct dmac_xfer *dx; 414 int rv; 415 416 if (sc->sc_rxdma) 417 return EBUSY; 418 419 sc->sc_rxfunc = rx_func; 420 sc->sc_rxarg = rx_arg; 421 422 /* Find mapping which contains block completely */ 423 for (p = sc->sc_dmas; p != NULL && (((void *)block < p->addr) || 424 ((void *)block + bsize > p->addr + p->size)); p = p->next) 425 continue; /* Nothing */ 426 427 if (p == NULL) { 428 printf("pxa2x0_i2s_start_input: request with bad start " 429 "address: %p, size: %d)\n", block, bsize); 430 return ENXIO; 431 } 432 433 sc->sc_rxdma = p; 434 p->segs[0].ds_addr = p->map->dm_segs[0].ds_addr 435 + ((void *)block - p->addr); 436 p->segs[0].ds_len = bsize; 437 438 dx = p->dx; 439 dx->dx_done = pxa2x0_i2s_dmac_iintr; 440 dx->dx_peripheral = DMAC_PERIPH_I2SRX; 441 dx->dx_flow = DMAC_FLOW_CTRL_SRC; 442 dx->dx_loop_notify = DMAC_DONT_LOOP; 443 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 444 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 445 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 446 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 447 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = p->nsegs; 448 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = p->segs; 449 450 /* Start DMA */ 451 rv = pxa2x0_dmac_start_xfer(dx); 452 453 return rv; 454 } 455 456 static void 457 pxa2x0_i2s_dmac_ointr(struct dmac_xfer *dx, int status) 458 { 459 struct pxa2x0_i2s_softc *sc = dx->dx_cookie; 460 struct pxa2x0_i2s_dma *p = sc->sc_txdma; 461 int s; 462 463 if (p == NULL) { 464 panic("pxa2x_i2s_dmac_ointr: bad TX DMA descriptor!"); 465 } 466 467 if (p->dx != dx) { 468 panic("pxa2x_i2s_dmac_ointr: xfer mismatch!"); 469 } 470 471 if (status) { 472 printf("%s: pxa2x0_i2s_dmac_ointr: " 473 "non-zero completion status %d\n", 474 sc->sc_dev.dv_xname, status); 475 } 476 477 s = splaudio(); 478 (sc->sc_txfunc)(sc->sc_txarg); 479 splx(s); 480 } 481 482 static void 483 pxa2x0_i2s_dmac_iintr(struct dmac_xfer *dx, int status) 484 { 485 struct pxa2x0_i2s_softc *sc = dx->dx_cookie; 486 struct pxa2x0_i2s_dma *p = sc->sc_rxdma; 487 int s; 488 489 if (p == NULL) { 490 panic("pxa2x_i2s_dmac_iintr: bad RX DMA descriptor!"); 491 } 492 493 if (p->dx != dx) { 494 panic("pxa2x_i2s_dmac_iintr: xfer mismatch!"); 495 } 496 497 if (status) { 498 printf("%s: pxa2x0_i2s_dmac_iintr: " 499 "non-zero completion status %d\n", 500 sc->sc_dev.dv_xname, status); 501 } 502 503 s = splaudio(); 504 (sc->sc_rxfunc)(sc->sc_rxarg); 505 splx(s); 506 } 507
Indexes created Wed Sep 24 15:09:51 GMT 2025