Home | History | Annotate | Line # | Download | only in xscale
pxa2x0_intr.c revision 1.13.12.2
      1  1.13.12.2   yamt /*	$NetBSD: pxa2x0_intr.c,v 1.13.12.2 2009/05/04 08:10:45 yamt Exp $	*/
      2        1.1    bsh 
      3        1.1    bsh /*
      4        1.1    bsh  * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
      5        1.1    bsh  * Written by Hiroyuki Bessho for Genetec Corporation.
      6        1.1    bsh  *
      7        1.1    bsh  * Redistribution and use in source and binary forms, with or without
      8        1.1    bsh  * modification, are permitted provided that the following conditions
      9        1.1    bsh  * are met:
     10        1.1    bsh  * 1. Redistributions of source code must retain the above copyright
     11        1.1    bsh  *    notice, this list of conditions and the following disclaimer.
     12        1.1    bsh  * 2. Redistributions in binary form must reproduce the above copyright
     13        1.1    bsh  *    notice, this list of conditions and the following disclaimer in the
     14        1.1    bsh  *    documentation and/or other materials provided with the distribution.
     15        1.1    bsh  * 3. All advertising materials mentioning features or use of this software
     16        1.1    bsh  *    must display the following acknowledgement:
     17        1.1    bsh  *	This product includes software developed for the NetBSD Project by
     18        1.1    bsh  *	Genetec Corporation.
     19        1.1    bsh  * 4. The name of Genetec Corporation may not be used to endorse or
     20        1.1    bsh  *    promote products derived from this software without specific prior
     21        1.1    bsh  *    written permission.
     22        1.1    bsh  *
     23        1.1    bsh  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
     24        1.1    bsh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     25        1.1    bsh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     26        1.1    bsh  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
     27        1.1    bsh  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     28        1.1    bsh  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     29        1.1    bsh  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     30        1.1    bsh  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     31        1.1    bsh  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     32        1.1    bsh  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     33        1.1    bsh  * POSSIBILITY OF SUCH DAMAGE.
     34        1.1    bsh  */
     35        1.1    bsh 
     36        1.1    bsh /*
     37        1.1    bsh  * IRQ handler for the Intel PXA2X0 processor.
     38        1.1    bsh  * It has integrated interrupt controller.
     39        1.1    bsh  */
     40        1.5  lukem 
     41        1.5  lukem #include <sys/cdefs.h>
     42  1.13.12.2   yamt __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.13.12.2 2009/05/04 08:10:45 yamt Exp $");
     43        1.5  lukem 
     44        1.1    bsh #include <sys/param.h>
     45        1.1    bsh #include <sys/systm.h>
     46        1.1    bsh #include <sys/malloc.h>
     47        1.3    scw 
     48        1.1    bsh #include <machine/bus.h>
     49        1.1    bsh #include <machine/intr.h>
     50        1.3    scw #include <machine/lock.h>
     51        1.1    bsh 
     52        1.6    bsh #include <arm/xscale/pxa2x0cpu.h>
     53        1.1    bsh #include <arm/xscale/pxa2x0reg.h>
     54        1.1    bsh #include <arm/xscale/pxa2x0var.h>
     55        1.3    scw #include <arm/xscale/pxa2x0_intr.h>
     56        1.1    bsh #include <arm/sa11x0/sa11x0_var.h>
     57        1.3    scw 
     58        1.3    scw /*
     59        1.3    scw  * INTC autoconf glue
     60        1.3    scw  */
     61        1.3    scw static int	pxaintc_match(struct device *, struct cfdata *, void *);
     62        1.3    scw static void	pxaintc_attach(struct device *, struct device *, void *);
     63        1.3    scw 
     64        1.3    scw CFATTACH_DECL(pxaintc, sizeof(struct device),
     65        1.3    scw     pxaintc_match, pxaintc_attach, NULL, NULL);
     66        1.3    scw 
     67        1.3    scw static int pxaintc_attached;
     68        1.3    scw 
     69        1.3    scw static int stray_interrupt(void *);
     70        1.3    scw static void init_interrupt_masks(void);
     71        1.1    bsh 
     72        1.1    bsh /*
     73        1.1    bsh  * interrupt dispatch table.
     74        1.1    bsh  */
     75        1.1    bsh #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
     76        1.1    bsh struct intrhand {
     77        1.1    bsh 	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
     78        1.1    bsh 	int (*ih_func)(void *);		/* handler */
     79        1.1    bsh 	void *ih_arg;			/* arg for handler */
     80        1.1    bsh };
     81        1.1    bsh #endif
     82        1.1    bsh 
     83       1.11  peter static struct intrhandler {
     84        1.1    bsh #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
     85        1.1    bsh 	TAILQ_HEAD(,intrhand) list;
     86        1.1    bsh #else
     87        1.1    bsh 	pxa2x0_irq_handler_t func;
     88        1.1    bsh #endif
     89        1.1    bsh 	void *cookie;		/* NULL for stackframe */
     90        1.1    bsh 	/* struct evbnt ev; */
     91        1.1    bsh } handler[ICU_LEN];
     92        1.1    bsh 
     93        1.8  perry volatile int softint_pending;
     94        1.8  perry volatile int intr_mask;
     95        1.1    bsh /* interrupt masks for each level */
     96        1.1    bsh int pxa2x0_imask[NIPL];
     97        1.1    bsh static int extirq_level[ICU_LEN];
     98        1.1    bsh 
     99        1.3    scw 
    100        1.3    scw static int
    101        1.3    scw pxaintc_match(struct device *parent, struct cfdata *cf, void *aux)
    102        1.3    scw {
    103        1.3    scw 	struct pxaip_attach_args *pxa = aux;
    104        1.3    scw 
    105        1.3    scw 	if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE)
    106        1.3    scw 		return (0);
    107        1.3    scw 
    108        1.3    scw 	return (1);
    109        1.3    scw }
    110        1.3    scw 
    111        1.3    scw void
    112        1.3    scw pxaintc_attach(struct device *parent, struct device *self, void *args)
    113        1.3    scw {
    114        1.3    scw 	int i;
    115        1.3    scw 
    116        1.3    scw 	pxaintc_attached = 1;
    117        1.3    scw 
    118        1.3    scw 	aprint_normal(": Interrupt Controller\n");
    119        1.3    scw 
    120        1.3    scw #define	SAIPIC_ICCR	0x14
    121        1.3    scw 
    122        1.3    scw 	write_icu(SAIPIC_ICCR, 1);
    123        1.3    scw 	write_icu(SAIPIC_MR, 0);
    124        1.3    scw 
    125        1.3    scw 	for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){
    126        1.3    scw 		handler[i].func = stray_interrupt;
    127        1.3    scw 		handler[i].cookie = (void *)(intptr_t) i;
    128        1.3    scw 		extirq_level[i] = IPL_SERIAL;
    129        1.3    scw 	}
    130        1.3    scw 
    131        1.3    scw 	init_interrupt_masks();
    132        1.3    scw 
    133        1.3    scw 	_splraise(IPL_SERIAL);
    134        1.3    scw 	enable_interrupts(I32_bit);
    135        1.3    scw }
    136        1.3    scw 
    137        1.3    scw /*
    138        1.3    scw  * Invoked very early on from the board-specific initarm(), in order to
    139        1.3    scw  * inform us the virtual address of the interrupt controller's registers.
    140        1.3    scw  */
    141        1.3    scw void
    142        1.3    scw pxa2x0_intr_bootstrap(vaddr_t addr)
    143        1.3    scw {
    144        1.3    scw 
    145        1.3    scw 	pxaic_base = addr;
    146        1.3    scw }
    147        1.3    scw 
    148        1.8  perry static inline void
    149        1.1    bsh __raise(int ipl)
    150        1.1    bsh {
    151        1.3    scw 
    152  1.13.12.1   yamt 	if (curcpu()->ci_cpl < ipl)
    153        1.1    bsh 		pxa2x0_setipl(ipl);
    154        1.1    bsh }
    155        1.1    bsh 
    156        1.1    bsh /*
    157        1.1    bsh  * called from irq_entry.
    158        1.1    bsh  */
    159        1.1    bsh void
    160        1.3    scw pxa2x0_irq_handler(void *arg)
    161        1.1    bsh {
    162        1.3    scw 	struct clockframe *frame = arg;
    163        1.1    bsh 	uint32_t irqbits;
    164        1.1    bsh 	int irqno;
    165        1.1    bsh 	int saved_spl_level;
    166        1.1    bsh 
    167  1.13.12.1   yamt 	saved_spl_level = curcpu()->ci_cpl;
    168        1.1    bsh 
    169        1.1    bsh 	/* get pending IRQs */
    170        1.1    bsh 	irqbits = read_icu(SAIPIC_IP);
    171        1.1    bsh 
    172        1.3    scw 	while ((irqno = find_first_bit(irqbits)) >= 0) {
    173        1.1    bsh 		/* XXX: Shuould we handle IRQs in priority order? */
    174        1.1    bsh 
    175        1.1    bsh 		/* raise spl to stop interrupts of lower priorities */
    176        1.3    scw 		if (saved_spl_level < extirq_level[irqno])
    177        1.1    bsh 			pxa2x0_setipl(extirq_level[irqno]);
    178        1.1    bsh 
    179        1.1    bsh #ifdef notyet
    180        1.1    bsh 		/* Enable interrupt */
    181        1.1    bsh #endif
    182        1.1    bsh #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
    183        1.1    bsh 		(* handler[irqno].func)(
    184        1.1    bsh 			handler[irqno].cookie == 0
    185        1.1    bsh 			? frame : handler[irqno].cookie );
    186        1.1    bsh #else
    187        1.1    bsh 		/* process all handlers for this interrupt.
    188        1.1    bsh 		   XXX not yet */
    189        1.1    bsh #endif
    190        1.1    bsh 
    191        1.1    bsh #ifdef notyet
    192        1.1    bsh 		/* Disable interrupt */
    193        1.1    bsh #endif
    194        1.1    bsh 
    195        1.1    bsh 		irqbits &= ~(1<<irqno);
    196        1.1    bsh 	}
    197        1.1    bsh 
    198        1.1    bsh 	/* restore spl to that was when this interrupt happen */
    199        1.1    bsh 	pxa2x0_setipl(saved_spl_level);
    200       1.13     ad 
    201  1.13.12.1   yamt #ifdef __HAVE_FAST_SOFTINTS
    202  1.13.12.1   yamt 	cpu_dosoftints();
    203  1.13.12.1   yamt #endif
    204        1.1    bsh }
    205        1.1    bsh 
    206        1.1    bsh static int
    207        1.3    scw stray_interrupt(void *cookie)
    208        1.1    bsh {
    209        1.1    bsh 	int irqno = (int)cookie;
    210  1.13.12.2   yamt 	int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
    211  1.13.12.2   yamt 
    212        1.3    scw 	printf("stray interrupt %d\n", irqno);
    213        1.1    bsh 
    214  1.13.12.2   yamt 	if (irqmin <= irqno && irqno < ICU_LEN){
    215        1.1    bsh 		int save = disable_interrupts(I32_bit);
    216        1.3    scw 		write_icu(SAIPIC_MR,
    217        1.3    scw 		    read_icu(SAIPIC_MR) & ~(1U<<irqno));
    218        1.1    bsh 		restore_interrupts(save);
    219        1.1    bsh 	}
    220        1.1    bsh 
    221        1.1    bsh 	return 0;
    222        1.1    bsh }
    223        1.1    bsh 
    224        1.1    bsh 
    225        1.1    bsh 
    226        1.1    bsh /*
    227        1.1    bsh  * Interrupt Mask Handling
    228        1.1    bsh  */
    229        1.1    bsh 
    230        1.1    bsh void
    231        1.3    scw pxa2x0_update_intr_masks(int irqno, int level)
    232        1.1    bsh {
    233        1.1    bsh 	int mask = 1U<<irqno;
    234        1.1    bsh 	int psw = disable_interrupts(I32_bit);
    235        1.1    bsh 	int i;
    236        1.1    bsh 
    237        1.3    scw 	for(i = 0; i < level; ++i)
    238        1.3    scw 		pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
    239        1.1    bsh 
    240        1.3    scw 	for( ; i < NIPL-1; ++i)
    241        1.1    bsh 		pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */
    242        1.1    bsh 
    243        1.1    bsh 	/*
    244       1.10    wiz 	 * Enforce a hierarchy that gives "slow" device (or devices with
    245        1.1    bsh 	 * limited input buffer space/"real-time" requirements) a better
    246        1.1    bsh 	 * chance at not dropping data.
    247        1.1    bsh 	 */
    248       1.12     ad 	pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK];
    249       1.12     ad 	pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO];
    250       1.12     ad 	pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET];
    251       1.12     ad 	pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL];
    252       1.12     ad 	pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM];
    253       1.12     ad 	pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED];
    254        1.1    bsh 
    255  1.13.12.1   yamt 	write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]);
    256        1.1    bsh 
    257        1.1    bsh 	restore_interrupts(psw);
    258        1.1    bsh }
    259        1.1    bsh 
    260        1.1    bsh 
    261        1.1    bsh static void
    262        1.1    bsh init_interrupt_masks(void)
    263        1.1    bsh {
    264        1.1    bsh 
    265        1.3    scw 	memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask));
    266        1.3    scw 
    267        1.3    scw 	/*
    268        1.3    scw 	 * IPL_NONE has soft interrupts enabled only, at least until
    269        1.3    scw 	 * hardware handlers are installed.
    270        1.3    scw 	 */
    271  1.13.12.1   yamt 	pxa2x0_imask[IPL_NONE] = ~0;
    272        1.1    bsh 	/*
    273        1.1    bsh 	 * Initialize the soft interrupt masks to block themselves.
    274        1.1    bsh 	 */
    275  1.13.12.1   yamt 	pxa2x0_imask[IPL_SOFTCLOCK] = ~0;
    276  1.13.12.1   yamt 	pxa2x0_imask[IPL_SOFTBIO] = ~0;
    277  1.13.12.1   yamt 	pxa2x0_imask[IPL_SOFTNET] = ~0;
    278  1.13.12.1   yamt 	pxa2x0_imask[IPL_SOFTSERIAL] = ~0;
    279        1.1    bsh 
    280       1.12     ad 	pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_NONE];
    281       1.12     ad 	pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK];
    282       1.12     ad 	pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO];
    283       1.12     ad 	pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET];
    284        1.1    bsh }
    285        1.1    bsh 
    286        1.1    bsh #undef splx
    287        1.1    bsh void
    288        1.1    bsh splx(int ipl)
    289        1.1    bsh {
    290        1.1    bsh 	pxa2x0_splx(ipl);
    291        1.1    bsh }
    292        1.1    bsh 
    293        1.1    bsh #undef _splraise
    294        1.1    bsh int
    295        1.1    bsh _splraise(int ipl)
    296        1.1    bsh {
    297        1.1    bsh 	return pxa2x0_splraise(ipl);
    298        1.1    bsh }
    299        1.1    bsh 
    300        1.1    bsh #undef _spllower
    301        1.1    bsh int
    302        1.1    bsh _spllower(int ipl)
    303        1.1    bsh {
    304        1.1    bsh 	return pxa2x0_spllower(ipl);
    305        1.1    bsh }
    306        1.1    bsh 
    307        1.1    bsh void *
    308        1.1    bsh pxa2x0_intr_establish(int irqno, int level,
    309        1.3    scw     int (*func)(void *), void *cookie)
    310        1.1    bsh {
    311        1.1    bsh 	int psw;
    312        1.6    bsh 	int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
    313        1.1    bsh 
    314        1.6    bsh 	if (irqno < irqmin || irqno >= ICU_LEN)
    315        1.1    bsh 		panic("intr_establish: bogus irq number %d", irqno);
    316        1.1    bsh 
    317        1.1    bsh 	psw = disable_interrupts(I32_bit);
    318        1.1    bsh 
    319        1.1    bsh 	handler[irqno].cookie = cookie;
    320        1.1    bsh 	handler[irqno].func = func;
    321        1.1    bsh 	extirq_level[irqno] = level;
    322        1.3    scw 	pxa2x0_update_intr_masks(irqno, level);
    323        1.1    bsh 
    324  1.13.12.1   yamt 	intr_mask = pxa2x0_imask[curcpu()->ci_cpl];
    325       1.11  peter 
    326        1.1    bsh 	restore_interrupts(psw);
    327        1.1    bsh 
    328        1.3    scw 	return (&handler[irqno]);
    329        1.1    bsh }
    330        1.1    bsh 
    331       1.11  peter void
    332       1.11  peter pxa2x0_intr_disestablish(void *cookie)
    333       1.11  peter {
    334       1.11  peter 	struct intrhandler *lhandler = cookie, *ih;
    335       1.11  peter 	int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
    336       1.11  peter 	int irqno = lhandler - handler;
    337       1.11  peter 	int psw;
    338       1.11  peter 
    339       1.11  peter 	if (irqno < irqmin || irqno >= ICU_LEN)
    340       1.11  peter 		panic("intr_disestablish: bogus irq number %d", irqno);
    341       1.11  peter 
    342       1.11  peter 	psw = disable_interrupts(I32_bit);
    343       1.11  peter 
    344       1.11  peter 	ih = &handler[irqno];
    345       1.11  peter 	ih->func = stray_interrupt;
    346       1.11  peter 	ih->cookie = (void *)(intptr_t)irqno;
    347       1.11  peter 	extirq_level[irqno] = IPL_SERIAL;
    348       1.11  peter 	pxa2x0_update_intr_masks(irqno, IPL_SERIAL);
    349       1.11  peter 
    350       1.11  peter 	restore_interrupts(psw);
    351       1.11  peter }
    352       1.11  peter 
    353        1.1    bsh /*
    354        1.1    bsh  * Glue for drivers of sa11x0 compatible integrated logics.
    355        1.1    bsh  */
    356        1.1    bsh void *
    357        1.1    bsh sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
    358        1.3    scw     int (*ih_fun)(void *), void *ih_arg)
    359        1.1    bsh {
    360        1.3    scw 
    361        1.3    scw 	return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg);
    362        1.1    bsh }
    363