pxa2x0_intr.c revision 1.11.26.2
1 /* $NetBSD: pxa2x0_intr.c,v 1.11.26.2 2008/01/09 01:45:28 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.11.26.2 2008/01/09 01:45:28 matt Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(struct device *, struct cfdata *, void *); 62 static void pxaintc_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(pxaintc, sizeof(struct device), 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct intrhandler { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 volatile int softint_pending; 94 volatile int intr_mask; 95 /* interrupt masks for each level */ 96 int pxa2x0_imask[NIPL]; 97 static int extirq_level[ICU_LEN]; 98 99 100 static int 101 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux) 102 { 103 struct pxaip_attach_args *pxa = aux; 104 105 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 106 return (0); 107 108 return (1); 109 } 110 111 void 112 pxaintc_attach(struct device *parent, struct device *self, void *args) 113 { 114 int i; 115 116 pxaintc_attached = 1; 117 118 aprint_normal(": Interrupt Controller\n"); 119 120 #define SAIPIC_ICCR 0x14 121 122 write_icu(SAIPIC_ICCR, 1); 123 write_icu(SAIPIC_MR, 0); 124 125 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 126 handler[i].func = stray_interrupt; 127 handler[i].cookie = (void *)(intptr_t) i; 128 extirq_level[i] = IPL_SERIAL; 129 } 130 131 init_interrupt_masks(); 132 133 _splraise(IPL_SERIAL); 134 enable_interrupts(I32_bit); 135 } 136 137 /* 138 * Invoked very early on from the board-specific initarm(), in order to 139 * inform us the virtual address of the interrupt controller's registers. 140 */ 141 void 142 pxa2x0_intr_bootstrap(vaddr_t addr) 143 { 144 145 pxaic_base = addr; 146 } 147 148 static inline void 149 __raise(int ipl) 150 { 151 152 if (curcpu()->ci_cpl < ipl) 153 pxa2x0_setipl(ipl); 154 } 155 156 #ifdef __HAVE_FAST_SOFTINTS 157 /* 158 * Map a software interrupt queue to an interrupt priority level. 159 */ 160 static const int si_to_ipl[] = { 161 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 162 [SI_SOFTBIO] = IPL_SOFTBIO, 163 [SI_SOFTNET] = IPL_SOFTNET, 164 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 165 }; 166 #endif 167 168 /* 169 * called from irq_entry. 170 */ 171 void 172 pxa2x0_irq_handler(void *arg) 173 { 174 struct clockframe *frame = arg; 175 uint32_t irqbits; 176 int irqno; 177 int saved_spl_level; 178 179 saved_spl_level = curcpu()->ci_cpl; 180 181 /* get pending IRQs */ 182 irqbits = read_icu(SAIPIC_IP); 183 184 while ((irqno = find_first_bit(irqbits)) >= 0) { 185 /* XXX: Shuould we handle IRQs in priority order? */ 186 187 /* raise spl to stop interrupts of lower priorities */ 188 if (saved_spl_level < extirq_level[irqno]) 189 pxa2x0_setipl(extirq_level[irqno]); 190 191 #ifdef notyet 192 /* Enable interrupt */ 193 #endif 194 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 195 (* handler[irqno].func)( 196 handler[irqno].cookie == 0 197 ? frame : handler[irqno].cookie ); 198 #else 199 /* process all handlers for this interrupt. 200 XXX not yet */ 201 #endif 202 203 #ifdef notyet 204 /* Disable interrupt */ 205 #endif 206 207 irqbits &= ~(1<<irqno); 208 } 209 210 /* restore spl to that was when this interrupt happen */ 211 pxa2x0_setipl(saved_spl_level); 212 213 #ifdef __HAVE_FAST_SOFTINTS 214 if(softint_pending & intr_mask) 215 pxa2x0_do_pending(); 216 #endif 217 } 218 219 static int 220 stray_interrupt(void *cookie) 221 { 222 int irqno = (int)cookie; 223 printf("stray interrupt %d\n", irqno); 224 225 if (PXA270_IRQ_MIN <= irqno && irqno < ICU_LEN){ 226 int save = disable_interrupts(I32_bit); 227 write_icu(SAIPIC_MR, 228 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 229 restore_interrupts(save); 230 } 231 232 return 0; 233 } 234 235 236 237 /* 238 * Interrupt Mask Handling 239 */ 240 241 void 242 pxa2x0_update_intr_masks(int irqno, int level) 243 { 244 int mask = 1U<<irqno; 245 int psw = disable_interrupts(I32_bit); 246 int i; 247 248 for(i = 0; i < level; ++i) 249 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 250 251 for( ; i < NIPL-1; ++i) 252 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */ 253 254 /* 255 * Enforce a hierarchy that gives "slow" device (or devices with 256 * limited input buffer space/"real-time" requirements) a better 257 * chance at not dropping data. 258 */ 259 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 260 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 261 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 262 pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL]; 263 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 264 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 265 266 write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]); 267 268 restore_interrupts(psw); 269 } 270 271 272 static void 273 init_interrupt_masks(void) 274 { 275 276 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 277 278 /* 279 * IPL_NONE has soft interrupts enabled only, at least until 280 * hardware handlers are installed. 281 */ 282 pxa2x0_imask[IPL_NONE] = 283 SI_TO_IRQBIT(SI_SOFTCLOCK) | 284 SI_TO_IRQBIT(SI_SOFTBIO) | 285 SI_TO_IRQBIT(SI_SOFTNET) | 286 SI_TO_IRQBIT(SI_SOFTSERIAL); 287 288 /* 289 * Initialize the soft interrupt masks to block themselves. 290 */ 291 pxa2x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 292 pxa2x0_imask[IPL_SOFTBIO] = ~SI_TO_IRQBIT(SI_SOFTBIO); 293 pxa2x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 294 pxa2x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL); 295 296 pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_NONE]; 297 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 298 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 299 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 300 } 301 302 #ifdef __HAVE_FAST_SOFTINTS 303 void 304 pxa2x0_do_pending(void) 305 { 306 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 307 int oldirqstate, spl_save; 308 309 if (__cpu_simple_lock_try(&processing) == 0) 310 return; 311 312 spl_save = curcpu()->ci_cpl; 313 314 oldirqstate = disable_interrupts(I32_bit); 315 316 #if 1 317 #define DO_SOFTINT(si,ipl) \ 318 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 319 softint_pending &= ~SI_TO_IRQBIT(si); \ 320 __raise(ipl); \ 321 restore_interrupts(oldirqstate); \ 322 softintr_dispatch(si); \ 323 oldirqstate = disable_interrupts(I32_bit); \ 324 pxa2x0_setipl(spl_save); \ 325 } 326 327 do { 328 DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL); 329 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 330 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 331 DO_SOFTINT(SI_SOFT, IPL_SOFT); 332 } while( softint_pending & intr_mask ); 333 #else 334 while( (si = find_first_bit(softint_pending & intr_mask)) >= 0 ){ 335 softint_pending &= ~SI_TO_IRQBIT(si); 336 __raise(si_to_ipl(si)); 337 restore_interrupts(oldirqstate); 338 softintr_dispatch(si); 339 oldirqstate = disable_interrupts(I32_bit); 340 pxa2x0_setipl(spl_save); 341 } 342 #endif 343 344 __cpu_simple_unlock(&processing); 345 346 restore_interrupts(oldirqstate); 347 } 348 #endif 349 350 351 #undef splx 352 void 353 splx(int ipl) 354 { 355 356 pxa2x0_splx(ipl); 357 } 358 359 #undef _splraise 360 int 361 _splraise(int ipl) 362 { 363 364 return pxa2x0_splraise(ipl); 365 } 366 367 #undef _spllower 368 int 369 _spllower(int ipl) 370 { 371 372 return pxa2x0_spllower(ipl); 373 } 374 375 #undef _setsoftintr 376 #ifdef __HAVE_FAST_SOFTINTS 377 void 378 _setsoftintr(int si) 379 { 380 pxa2x0_setsoftintr(si); 381 } 382 #endif 383 384 void * 385 pxa2x0_intr_establish(int irqno, int level, 386 int (*func)(void *), void *cookie) 387 { 388 int psw; 389 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 390 391 if (irqno < irqmin || irqno >= ICU_LEN) 392 panic("intr_establish: bogus irq number %d", irqno); 393 394 psw = disable_interrupts(I32_bit); 395 396 handler[irqno].cookie = cookie; 397 handler[irqno].func = func; 398 extirq_level[irqno] = level; 399 pxa2x0_update_intr_masks(irqno, level); 400 401 intr_mask = pxa2x0_imask[curcpu()->ci_cpl]; 402 403 restore_interrupts(psw); 404 405 return (&handler[irqno]); 406 } 407 408 void 409 pxa2x0_intr_disestablish(void *cookie) 410 { 411 struct intrhandler *lhandler = cookie, *ih; 412 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 413 int irqno = lhandler - handler; 414 int psw; 415 416 if (irqno < irqmin || irqno >= ICU_LEN) 417 panic("intr_disestablish: bogus irq number %d", irqno); 418 419 psw = disable_interrupts(I32_bit); 420 421 ih = &handler[irqno]; 422 ih->func = stray_interrupt; 423 ih->cookie = (void *)(intptr_t)irqno; 424 extirq_level[irqno] = IPL_SERIAL; 425 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 426 427 restore_interrupts(psw); 428 } 429 430 /* 431 * Glue for drivers of sa11x0 compatible integrated logics. 432 */ 433 void * 434 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 435 int (*ih_fun)(void *), void *ih_arg) 436 { 437 438 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 439 } 440
Indexes created Wed Oct 22 13:09:56 GMT 2025