pxa2x0_intr.c revision 1.11.26.3
1 /* $NetBSD: pxa2x0_intr.c,v 1.11.26.3 2008/01/28 18:29:10 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.11.26.3 2008/01/28 18:29:10 matt Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(struct device *, struct cfdata *, void *); 62 static void pxaintc_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(pxaintc, sizeof(struct device), 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct intrhandler { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 volatile int softint_pending; 94 volatile int intr_mask; 95 /* interrupt masks for each level */ 96 int pxa2x0_imask[NIPL]; 97 static int extirq_level[ICU_LEN]; 98 99 100 static int 101 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux) 102 { 103 struct pxaip_attach_args *pxa = aux; 104 105 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 106 return (0); 107 108 return (1); 109 } 110 111 void 112 pxaintc_attach(struct device *parent, struct device *self, void *args) 113 { 114 int i; 115 116 pxaintc_attached = 1; 117 118 aprint_normal(": Interrupt Controller\n"); 119 120 #define SAIPIC_ICCR 0x14 121 122 write_icu(SAIPIC_ICCR, 1); 123 write_icu(SAIPIC_MR, 0); 124 125 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 126 handler[i].func = stray_interrupt; 127 handler[i].cookie = (void *)(intptr_t) i; 128 extirq_level[i] = IPL_SERIAL; 129 } 130 131 init_interrupt_masks(); 132 133 _splraise(IPL_SERIAL); 134 enable_interrupts(I32_bit); 135 } 136 137 /* 138 * Invoked very early on from the board-specific initarm(), in order to 139 * inform us the virtual address of the interrupt controller's registers. 140 */ 141 void 142 pxa2x0_intr_bootstrap(vaddr_t addr) 143 { 144 145 pxaic_base = addr; 146 } 147 148 static inline void 149 __raise(int ipl) 150 { 151 152 if (curcpu()->ci_cpl < ipl) 153 pxa2x0_setipl(ipl); 154 } 155 156 /* 157 * called from irq_entry. 158 */ 159 void 160 pxa2x0_irq_handler(void *arg) 161 { 162 struct clockframe *frame = arg; 163 uint32_t irqbits; 164 int irqno; 165 int saved_spl_level; 166 167 saved_spl_level = curcpu()->ci_cpl; 168 169 /* get pending IRQs */ 170 irqbits = read_icu(SAIPIC_IP); 171 172 while ((irqno = find_first_bit(irqbits)) >= 0) { 173 /* XXX: Shuould we handle IRQs in priority order? */ 174 175 /* raise spl to stop interrupts of lower priorities */ 176 if (saved_spl_level < extirq_level[irqno]) 177 pxa2x0_setipl(extirq_level[irqno]); 178 179 #ifdef notyet 180 /* Enable interrupt */ 181 #endif 182 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 183 (* handler[irqno].func)( 184 handler[irqno].cookie == 0 185 ? frame : handler[irqno].cookie ); 186 #else 187 /* process all handlers for this interrupt. 188 XXX not yet */ 189 #endif 190 191 #ifdef notyet 192 /* Disable interrupt */ 193 #endif 194 195 irqbits &= ~(1<<irqno); 196 } 197 198 /* restore spl to that was when this interrupt happen */ 199 pxa2x0_setipl(saved_spl_level); 200 201 #ifdef __HAVE_FAST_SOFTINTS 202 cpu_dosoftints(); 203 #endif 204 } 205 206 static int 207 stray_interrupt(void *cookie) 208 { 209 int irqno = (int)cookie; 210 printf("stray interrupt %d\n", irqno); 211 212 if (PXA270_IRQ_MIN <= irqno && irqno < ICU_LEN){ 213 int save = disable_interrupts(I32_bit); 214 write_icu(SAIPIC_MR, 215 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 216 restore_interrupts(save); 217 } 218 219 return 0; 220 } 221 222 223 224 /* 225 * Interrupt Mask Handling 226 */ 227 228 void 229 pxa2x0_update_intr_masks(int irqno, int level) 230 { 231 int mask = 1U<<irqno; 232 int psw = disable_interrupts(I32_bit); 233 int i; 234 235 for(i = 0; i < level; ++i) 236 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 237 238 for( ; i < NIPL-1; ++i) 239 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */ 240 241 /* 242 * Enforce a hierarchy that gives "slow" device (or devices with 243 * limited input buffer space/"real-time" requirements) a better 244 * chance at not dropping data. 245 */ 246 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 247 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 248 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 249 pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL]; 250 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 251 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 252 253 write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]); 254 255 restore_interrupts(psw); 256 } 257 258 259 static void 260 init_interrupt_masks(void) 261 { 262 263 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 264 265 /* 266 * IPL_NONE has soft interrupts enabled only, at least until 267 * hardware handlers are installed. 268 */ 269 pxa2x0_imask[IPL_NONE] = ~0; 270 /* 271 * Initialize the soft interrupt masks to block themselves. 272 */ 273 pxa2x0_imask[IPL_SOFTCLOCK] = ~0; 274 pxa2x0_imask[IPL_SOFTBIO] = ~0; 275 pxa2x0_imask[IPL_SOFTNET] = ~0; 276 pxa2x0_imask[IPL_SOFTSERIAL] = ~0; 277 278 pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_NONE]; 279 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 280 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 281 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 282 } 283 284 #undef splx 285 void 286 splx(int ipl) 287 { 288 pxa2x0_splx(ipl); 289 } 290 291 #undef _splraise 292 int 293 _splraise(int ipl) 294 { 295 return pxa2x0_splraise(ipl); 296 } 297 298 #undef _spllower 299 int 300 _spllower(int ipl) 301 { 302 return pxa2x0_spllower(ipl); 303 } 304 305 void * 306 pxa2x0_intr_establish(int irqno, int level, 307 int (*func)(void *), void *cookie) 308 { 309 int psw; 310 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 311 312 if (irqno < irqmin || irqno >= ICU_LEN) 313 panic("intr_establish: bogus irq number %d", irqno); 314 315 psw = disable_interrupts(I32_bit); 316 317 handler[irqno].cookie = cookie; 318 handler[irqno].func = func; 319 extirq_level[irqno] = level; 320 pxa2x0_update_intr_masks(irqno, level); 321 322 intr_mask = pxa2x0_imask[curcpu()->ci_cpl]; 323 324 restore_interrupts(psw); 325 326 return (&handler[irqno]); 327 } 328 329 void 330 pxa2x0_intr_disestablish(void *cookie) 331 { 332 struct intrhandler *lhandler = cookie, *ih; 333 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 334 int irqno = lhandler - handler; 335 int psw; 336 337 if (irqno < irqmin || irqno >= ICU_LEN) 338 panic("intr_disestablish: bogus irq number %d", irqno); 339 340 psw = disable_interrupts(I32_bit); 341 342 ih = &handler[irqno]; 343 ih->func = stray_interrupt; 344 ih->cookie = (void *)(intptr_t)irqno; 345 extirq_level[irqno] = IPL_SERIAL; 346 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 347 348 restore_interrupts(psw); 349 } 350 351 /* 352 * Glue for drivers of sa11x0 compatible integrated logics. 353 */ 354 void * 355 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 356 int (*ih_fun)(void *), void *ih_arg) 357 { 358 359 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 360 } 361
Indexes created Tue Oct 21 16:10:11 GMT 2025