pxa2x0_intr.h revision 1.1.2.2
1 1.1.2.2 nathanw /* $NetBSD: pxa2x0_intr.h,v 1.1.2.2 2002/11/11 21:56:58 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* Derived from i80321_intr.h */ 4 1.1.2.2 nathanw 5 1.1.2.2 nathanw /* 6 1.1.2.2 nathanw * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 7 1.1.2.2 nathanw * All rights reserved. 8 1.1.2.2 nathanw * 9 1.1.2.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 10 1.1.2.2 nathanw * 11 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 12 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 13 1.1.2.2 nathanw * are met: 14 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 15 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 16 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 17 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 18 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 19 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 20 1.1.2.2 nathanw * must display the following acknowledgement: 21 1.1.2.2 nathanw * This product includes software developed for the NetBSD Project by 22 1.1.2.2 nathanw * Wasabi Systems, Inc. 23 1.1.2.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 1.1.2.2 nathanw * or promote products derived from this software without specific prior 25 1.1.2.2 nathanw * written permission. 26 1.1.2.2 nathanw * 27 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 1.1.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 1.1.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 1.1.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 1.1.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 1.1.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 1.1.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 1.1.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 1.1.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 1.1.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 1.1.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 38 1.1.2.2 nathanw */ 39 1.1.2.2 nathanw 40 1.1.2.2 nathanw #ifndef _PXA2X0_INTR_H_ 41 1.1.2.2 nathanw #define _PXA2X0_INTR_H_ 42 1.1.2.2 nathanw 43 1.1.2.2 nathanw #include <arm/cpu.h> 44 1.1.2.2 nathanw #include <arm/armreg.h> 45 1.1.2.2 nathanw #include <arm/cpufunc.h> 46 1.1.2.2 nathanw #include <machine/atomic.h> 47 1.1.2.2 nathanw #include <machine/intr.h> 48 1.1.2.2 nathanw #include <arm/softintr.h> 49 1.1.2.2 nathanw 50 1.1.2.2 nathanw #include <arm/xscale/pxa2x0reg.h> 51 1.1.2.2 nathanw 52 1.1.2.2 nathanw vaddr_t pxaic_base; /* Shared with pxa2x0_irq.S */ 53 1.1.2.2 nathanw #define read_icu(offset) (*(volatile uint32_t *)(pxaic_base+(offset))) 54 1.1.2.2 nathanw #define write_icu(offset,value) \ 55 1.1.2.2 nathanw (*(volatile uint32_t *)(pxaic_base+(offset))=(value)) 56 1.1.2.2 nathanw 57 1.1.2.2 nathanw extern __volatile int current_spl_level; 58 1.1.2.2 nathanw extern __volatile int intr_mask; 59 1.1.2.2 nathanw extern __volatile int softint_pending; 60 1.1.2.2 nathanw extern int pxa2x0_imask[]; 61 1.1.2.2 nathanw void pxa2x0_do_pending(void); 62 1.1.2.2 nathanw 63 1.1.2.2 nathanw /* 64 1.1.2.2 nathanw * Cotulla's integrated ICU doesn't have IRQ0..7, so 65 1.1.2.2 nathanw * we map software interrupts to bit 0..3 66 1.1.2.2 nathanw */ 67 1.1.2.2 nathanw #define SI_TO_IRQBIT(si) (1U<<(si)) 68 1.1.2.2 nathanw 69 1.1.2.2 nathanw 70 1.1.2.2 nathanw static __inline void 71 1.1.2.2 nathanw pxa2x0_setipl(int new) 72 1.1.2.2 nathanw { 73 1.1.2.2 nathanw current_spl_level = new; 74 1.1.2.2 nathanw intr_mask = pxa2x0_imask[current_spl_level]; 75 1.1.2.2 nathanw write_icu( SAIPIC_MR, intr_mask ); 76 1.1.2.2 nathanw } 77 1.1.2.2 nathanw 78 1.1.2.2 nathanw 79 1.1.2.2 nathanw static __inline void 80 1.1.2.2 nathanw pxa2x0_splx(int new) 81 1.1.2.2 nathanw { 82 1.1.2.2 nathanw int psw; 83 1.1.2.2 nathanw 84 1.1.2.2 nathanw psw = disable_interrupts(I32_bit); 85 1.1.2.2 nathanw pxa2x0_setipl(new); 86 1.1.2.2 nathanw restore_interrupts(psw); 87 1.1.2.2 nathanw 88 1.1.2.2 nathanw /* If there are software interrupts to process, do it. */ 89 1.1.2.2 nathanw if (softint_pending & intr_mask) 90 1.1.2.2 nathanw pxa2x0_do_pending(); 91 1.1.2.2 nathanw } 92 1.1.2.2 nathanw 93 1.1.2.2 nathanw 94 1.1.2.2 nathanw static __inline int 95 1.1.2.2 nathanw pxa2x0_splraise(int ipl) 96 1.1.2.2 nathanw { 97 1.1.2.2 nathanw int old, psw; 98 1.1.2.2 nathanw 99 1.1.2.2 nathanw old = current_spl_level; 100 1.1.2.2 nathanw if( ipl > current_spl_level ){ 101 1.1.2.2 nathanw psw = disable_interrupts(I32_bit); 102 1.1.2.2 nathanw pxa2x0_setipl(ipl); 103 1.1.2.2 nathanw restore_interrupts(psw); 104 1.1.2.2 nathanw } 105 1.1.2.2 nathanw 106 1.1.2.2 nathanw return (old); 107 1.1.2.2 nathanw } 108 1.1.2.2 nathanw 109 1.1.2.2 nathanw static __inline int 110 1.1.2.2 nathanw pxa2x0_spllower(int ipl) 111 1.1.2.2 nathanw { 112 1.1.2.2 nathanw int old = current_spl_level; 113 1.1.2.2 nathanw int psw = disable_interrupts(I32_bit); 114 1.1.2.2 nathanw pxa2x0_splx(ipl); 115 1.1.2.2 nathanw restore_interrupts(psw); 116 1.1.2.2 nathanw return(old); 117 1.1.2.2 nathanw } 118 1.1.2.2 nathanw 119 1.1.2.2 nathanw static __inline void 120 1.1.2.2 nathanw pxa2x0_setsoftintr(int si) 121 1.1.2.2 nathanw { 122 1.1.2.2 nathanw atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) ); 123 1.1.2.2 nathanw 124 1.1.2.2 nathanw /* Process unmasked pending soft interrupts. */ 125 1.1.2.2 nathanw if ( softint_pending & intr_mask ) 126 1.1.2.2 nathanw pxa2x0_do_pending(); 127 1.1.2.2 nathanw } 128 1.1.2.2 nathanw 129 1.1.2.2 nathanw 130 1.1.2.2 nathanw /* 131 1.1.2.2 nathanw * An useful function for interrupt handlers. 132 1.1.2.2 nathanw * XXX: This shouldn't be here. 133 1.1.2.2 nathanw */ 134 1.1.2.2 nathanw static __inline int 135 1.1.2.2 nathanw find_first_bit( uint32_t bits ) 136 1.1.2.2 nathanw { 137 1.1.2.2 nathanw int count; 138 1.1.2.2 nathanw 139 1.1.2.2 nathanw /* since CLZ is available only on ARMv5, this isn't portable 140 1.1.2.2 nathanw * to all ARM CPUs. This file is for PXA2[15]0 processor. 141 1.1.2.2 nathanw */ 142 1.1.2.2 nathanw asm( "clz %0, %1" : "=r" (count) : "r" (bits) ); 143 1.1.2.2 nathanw return 31-count; 144 1.1.2.2 nathanw } 145 1.1.2.2 nathanw 146 1.1.2.2 nathanw 147 1.1.2.2 nathanw int _splraise(int); 148 1.1.2.2 nathanw int _spllower(int); 149 1.1.2.2 nathanw void splx(int); 150 1.1.2.2 nathanw void _setsoftintr(int); 151 1.1.2.2 nathanw 152 1.1.2.2 nathanw #if !defined(EVBARM_SPL_NOINLINE) 153 1.1.2.2 nathanw 154 1.1.2.2 nathanw #define splx(new) pxa2x0_splx(new) 155 1.1.2.2 nathanw #define _spllower(ipl) pxa2x0_spllower(ipl) 156 1.1.2.2 nathanw #define _splraise(ipl) pxa2x0_splraise(ipl) 157 1.1.2.2 nathanw #define _setsoftintr(si) pxa2x0_setsoftintr(si) 158 1.1.2.2 nathanw 159 1.1.2.2 nathanw #endif /* !EVBARM_SPL_NOINTR */ 160 1.1.2.2 nathanw 161 1.1.2.2 nathanw #endif _PXA2X0_INTR_H_ 162
Indexes created Tue Oct 21 16:10:11 GMT 2025