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pxa2x0_intr.h revision 1.1 
      1 /*	$NetBSD: pxa2x0_intr.h,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
      2 
      3 /* Derived from i80321_intr.h */
      4 
      5 /*
      6  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
      7  * All rights reserved.
      8  *
      9  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  * 3. All advertising materials mentioning features or use of this software
     20  *    must display the following acknowledgement:
     21  *	This product includes software developed for the NetBSD Project by
     22  *	Wasabi Systems, Inc.
     23  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     24  *    or promote products derived from this software without specific prior
     25  *    written permission.
     26  *
     27  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  * POSSIBILITY OF SUCH DAMAGE.
     38  */
     39 
     40 #ifndef _PXA2X0_INTR_H_
     41 #define _PXA2X0_INTR_H_
     42 
     43 #include <arm/cpu.h>
     44 #include <arm/armreg.h>
     45 #include <arm/cpufunc.h>
     46 #include <machine/atomic.h>
     47 #include <machine/intr.h>
     48 #include <arm/softintr.h>
     49 
     50 #include <arm/xscale/pxa2x0reg.h>
     51 
     52 vaddr_t pxaic_base;		/* Shared with pxa2x0_irq.S */
     53 #define read_icu(offset) (*(volatile uint32_t *)(pxaic_base+(offset)))
     54 #define write_icu(offset,value) \
     55  (*(volatile uint32_t *)(pxaic_base+(offset))=(value))
     56 
     57 extern __volatile int current_spl_level;
     58 extern __volatile int intr_mask;
     59 extern __volatile int softint_pending;
     60 extern int pxa2x0_imask[];
     61 void pxa2x0_do_pending(void);
     62 
     63 /*
     64  * Cotulla's integrated ICU doesn't have IRQ0..7, so
     65  * we map software interrupts to bit 0..3
     66  */
     67 #define SI_TO_IRQBIT(si)  (1U<<(si))
     68 
     69 
     70 static __inline void
     71 pxa2x0_setipl(int new)
     72 {
     73 	current_spl_level = new;
     74 	intr_mask = pxa2x0_imask[current_spl_level];
     75 	write_icu( SAIPIC_MR, intr_mask );
     76 }
     77 
     78 
     79 static __inline void
     80 pxa2x0_splx(int new)
     81 {
     82 	int psw;
     83 
     84 	psw = disable_interrupts(I32_bit);
     85 	pxa2x0_setipl(new);
     86 	restore_interrupts(psw);
     87 
     88 	/* If there are software interrupts to process, do it. */
     89 	if (softint_pending & intr_mask)
     90 		pxa2x0_do_pending();
     91 }
     92 
     93 
     94 static __inline int
     95 pxa2x0_splraise(int ipl)
     96 {
     97 	int	old, psw;
     98 
     99 	old = current_spl_level;
    100 	if( ipl > current_spl_level ){
    101 		psw = disable_interrupts(I32_bit);
    102 		pxa2x0_setipl(ipl);
    103 		restore_interrupts(psw);
    104 	}
    105 
    106 	return (old);
    107 }
    108 
    109 static __inline int
    110 pxa2x0_spllower(int ipl)
    111 {
    112 	int old = current_spl_level;
    113 	int psw = disable_interrupts(I32_bit);
    114 	pxa2x0_splx(ipl);
    115 	restore_interrupts(psw);
    116 	return(old);
    117 }
    118 
    119 static __inline void
    120 pxa2x0_setsoftintr(int si)
    121 {
    122 	atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) );
    123 
    124 	/* Process unmasked pending soft interrupts. */
    125 	if ( softint_pending & intr_mask )
    126 		pxa2x0_do_pending();
    127 }
    128 
    129 
    130 /*
    131  * An useful function for interrupt handlers.
    132  * XXX: This shouldn't be here.
    133  */
    134 static __inline int
    135 find_first_bit( uint32_t bits )
    136 {
    137 	int count;
    138 
    139 	/* since CLZ is available only on ARMv5, this isn't portable
    140 	 * to all ARM CPUs.  This file is for PXA2[15]0 processor.
    141 	 */
    142 	asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
    143 	return 31-count;
    144 }
    145 
    146 
    147 int	_splraise(int);
    148 int	_spllower(int);
    149 void	splx(int);
    150 void	_setsoftintr(int);
    151 
    152 #if !defined(EVBARM_SPL_NOINLINE)
    153 
    154 #define splx(new)		pxa2x0_splx(new)
    155 #define	_spllower(ipl)		pxa2x0_spllower(ipl)
    156 #define	_splraise(ipl)		pxa2x0_splraise(ipl)
    157 #define	_setsoftintr(si)	pxa2x0_setsoftintr(si)
    158 
    159 #endif	/* !EVBARM_SPL_NOINTR */
    160 
    161 #endif _PXA2X0_INTR_H_
    162