pxa2x0_intr.h revision 1.10
1 /* $NetBSD: pxa2x0_intr.h,v 1.10 2007/02/28 23:26:10 bjh21 Exp $ */ 2 3 /* Derived from i80321_intr.h */ 4 5 /* 6 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _PXA2X0_INTR_H_ 41 #define _PXA2X0_INTR_H_ 42 43 #define ARM_IRQ_HANDLER _C_LABEL(pxa2x0_irq_handler) 44 45 #ifndef _LOCORE 46 47 #include <arm/cpu.h> 48 #include <arm/armreg.h> 49 #include <arm/cpufunc.h> 50 #include <machine/atomic.h> 51 #include <machine/intr.h> 52 #include <arm/softintr.h> 53 54 #include <arm/xscale/pxa2x0reg.h> 55 56 vaddr_t pxaic_base; /* Shared with pxa2x0_irq.S */ 57 #define read_icu(offset) (*(volatile uint32_t *)(pxaic_base + (offset))) 58 #define write_icu(offset,value) \ 59 (*(volatile uint32_t *)(pxaic_base + (offset)) = (value)) 60 61 extern volatile int current_spl_level; 62 extern volatile int intr_mask; 63 extern volatile int softint_pending; 64 extern int pxa2x0_imask[]; 65 void pxa2x0_do_pending(void); 66 67 /* 68 * Cotulla's integrated ICU doesn't have IRQ0..7, so 69 * we map software interrupts to bit 0..3 70 */ 71 #define SI_TO_IRQBIT(si) (1U<<(si)) 72 73 static inline void 74 pxa2x0_setipl(int new) 75 { 76 77 current_spl_level = new; 78 intr_mask = pxa2x0_imask[current_spl_level]; 79 write_icu(SAIPIC_MR, intr_mask); 80 } 81 82 83 static inline void 84 pxa2x0_splx(int new) 85 { 86 int psw; 87 88 psw = disable_interrupts(I32_bit); 89 pxa2x0_setipl(new); 90 restore_interrupts(psw); 91 92 /* If there are software interrupts to process, do it. */ 93 if (softint_pending & intr_mask) 94 pxa2x0_do_pending(); 95 } 96 97 98 static inline int 99 pxa2x0_splraise(int ipl) 100 { 101 int old, psw; 102 103 old = current_spl_level; 104 if (ipl > current_spl_level) { 105 psw = disable_interrupts(I32_bit); 106 pxa2x0_setipl(ipl); 107 restore_interrupts(psw); 108 } 109 110 return old; 111 } 112 113 static inline int 114 pxa2x0_spllower(int ipl) 115 { 116 int old = current_spl_level; 117 int psw = disable_interrupts(I32_bit); 118 119 pxa2x0_splx(ipl); 120 restore_interrupts(psw); 121 return old; 122 } 123 124 static inline void 125 pxa2x0_setsoftintr(int si) 126 { 127 128 atomic_set_bit((u_int *)__UNVOLATILE(&softint_pending), 129 SI_TO_IRQBIT(si)); 130 131 /* Process unmasked pending soft interrupts. */ 132 if (softint_pending & intr_mask) 133 pxa2x0_do_pending(); 134 } 135 136 137 /* 138 * An useful function for interrupt handlers. 139 * XXX: This shouldn't be here. 140 */ 141 static inline int 142 find_first_bit(uint32_t bits) 143 { 144 int count; 145 146 /* 147 * Since CLZ is available only on ARMv5, this isn't portable 148 * to all ARM CPUs. This file is for PXA2[15]0 processor. 149 */ 150 __asm( "clz %0, %1" : "=r" (count) : "r" (bits) ); 151 return 31 - count; 152 } 153 154 155 int _splraise(int); 156 int _spllower(int); 157 void splx(int); 158 void _setsoftintr(int); 159 160 #if !defined(EVBARM_SPL_NOINLINE) 161 162 #define splx(new) pxa2x0_splx(new) 163 #define _spllower(ipl) pxa2x0_spllower(ipl) 164 #define _splraise(ipl) pxa2x0_splraise(ipl) 165 #define _setsoftintr(si) pxa2x0_setsoftintr(si) 166 167 #endif /* !EVBARM_SPL_NOINTR */ 168 169 /* 170 * This function *MUST* be called very early on in a port's 171 * initarm() function, before ANY spl*() functions are called. 172 * 173 * The parameter is the virtual address of the PXA2x0's Interrupt 174 * Controller registers. 175 */ 176 void pxa2x0_intr_bootstrap(vaddr_t); 177 178 void pxa2x0_irq_handler(void *); 179 void *pxa2x0_intr_establish(int irqno, int level, 180 int (*func)(void *), void *cookie); 181 void pxa2x0_intr_disestablish(void *cookie); 182 void pxa2x0_update_intr_masks(int irqno, int level); 183 extern volatile int current_spl_level; 184 185 #endif /* ! _LOCORE */ 186 187 #endif /* _PXA2X0_INTR_H_ */ 188
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