pxa2x0_mci.c revision 1.2.2.2
1 1.2.2.2 jym /* $NetBSD: pxa2x0_mci.c,v 1.2.2.2 2009/05/13 17:16:18 jym Exp $ */ 2 1.2.2.2 jym /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 1.2.2.2 jym 4 1.2.2.2 jym /* 5 1.2.2.2 jym * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 1.2.2.2 jym * 7 1.2.2.2 jym * Permission to use, copy, modify, and distribute this software for any 8 1.2.2.2 jym * purpose with or without fee is hereby granted, provided that the above 9 1.2.2.2 jym * copyright notice and this permission notice appear in all copies. 10 1.2.2.2 jym * 11 1.2.2.2 jym * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 1.2.2.2 jym * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 1.2.2.2 jym * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 1.2.2.2 jym * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 1.2.2.2 jym * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 1.2.2.2 jym * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 1.2.2.2 jym * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 1.2.2.2 jym */ 19 1.2.2.2 jym 20 1.2.2.2 jym /*- 21 1.2.2.2 jym * Copyright (c) 2007-2009 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 1.2.2.2 jym * All rights reserved. 23 1.2.2.2 jym * 24 1.2.2.2 jym * Redistribution and use in source and binary forms, with or without 25 1.2.2.2 jym * modification, are permitted provided that the following conditions 26 1.2.2.2 jym * are met: 27 1.2.2.2 jym * 1. Redistributions of source code must retain the above copyright 28 1.2.2.2 jym * notice, this list of conditions and the following disclaimer. 29 1.2.2.2 jym * 2. Redistributions in binary form must reproduce the above copyright 30 1.2.2.2 jym * notice, this list of conditions and the following disclaimer in the 31 1.2.2.2 jym * documentation and/or other materials provided with the distribution. 32 1.2.2.2 jym * 33 1.2.2.2 jym * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 1.2.2.2 jym * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 1.2.2.2 jym * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 1.2.2.2 jym * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 1.2.2.2 jym * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 1.2.2.2 jym * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 1.2.2.2 jym * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 1.2.2.2 jym * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 1.2.2.2 jym * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 1.2.2.2 jym * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 1.2.2.2 jym * SUCH DAMAGE. 44 1.2.2.2 jym */ 45 1.2.2.2 jym 46 1.2.2.2 jym /* 47 1.2.2.2 jym * MMC/SD/SDIO controller driver for Intel PXA2xx processors 48 1.2.2.2 jym * 49 1.2.2.2 jym * Power management is beyond control of the processor's SD/SDIO/MMC 50 1.2.2.2 jym * block, so this driver depends on the attachment driver to provide 51 1.2.2.2 jym * us with some callback functions via the "tag" member in our softc. 52 1.2.2.2 jym * Bus power management calls are then dispatched to the attachment 53 1.2.2.2 jym * driver. 54 1.2.2.2 jym */ 55 1.2.2.2 jym 56 1.2.2.2 jym #include <sys/cdefs.h> 57 1.2.2.2 jym __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.2.2.2 2009/05/13 17:16:18 jym Exp $"); 58 1.2.2.2 jym 59 1.2.2.2 jym #include <sys/param.h> 60 1.2.2.2 jym #include <sys/device.h> 61 1.2.2.2 jym #include <sys/systm.h> 62 1.2.2.2 jym #include <sys/malloc.h> 63 1.2.2.2 jym #include <sys/kernel.h> 64 1.2.2.2 jym #include <sys/proc.h> 65 1.2.2.2 jym #include <sys/bus.h> 66 1.2.2.2 jym #include <sys/mutex.h> 67 1.2.2.2 jym #include <sys/condvar.h> 68 1.2.2.2 jym 69 1.2.2.2 jym #include <machine/intr.h> 70 1.2.2.2 jym 71 1.2.2.2 jym #include <dev/sdmmc/sdmmcvar.h> 72 1.2.2.2 jym #include <dev/sdmmc/sdmmcchip.h> 73 1.2.2.2 jym 74 1.2.2.2 jym #include <arm/xscale/pxa2x0cpu.h> 75 1.2.2.2 jym #include <arm/xscale/pxa2x0reg.h> 76 1.2.2.2 jym #include <arm/xscale/pxa2x0var.h> 77 1.2.2.2 jym #include <arm/xscale/pxa2x0_dmac.h> 78 1.2.2.2 jym #include <arm/xscale/pxa2x0_gpio.h> 79 1.2.2.2 jym #include <arm/xscale/pxa2x0_mci.h> 80 1.2.2.2 jym 81 1.2.2.2 jym #ifdef PXAMCI_DEBUG 82 1.2.2.2 jym int pxamci_debug = 1; 83 1.2.2.2 jym #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 84 1.2.2.2 jym #else 85 1.2.2.2 jym #define DPRINTF(n,s) do {} while (0) 86 1.2.2.2 jym #endif 87 1.2.2.2 jym 88 1.2.2.2 jym #ifndef DEBUG 89 1.2.2.2 jym #define STOPCLK_TIMO 2 /* ms */ 90 1.2.2.2 jym #define EXECCMD_TIMO 2 /* ms */ 91 1.2.2.2 jym #else 92 1.2.2.2 jym #define STOPCLK_TIMO 2 /* ms */ 93 1.2.2.2 jym #define EXECCMD_TIMO 5 /* ms */ 94 1.2.2.2 jym #endif 95 1.2.2.2 jym 96 1.2.2.2 jym static int pxamci_host_reset(sdmmc_chipset_handle_t); 97 1.2.2.2 jym static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 98 1.2.2.2 jym static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 99 1.2.2.2 jym static int pxamci_card_detect(sdmmc_chipset_handle_t); 100 1.2.2.2 jym static int pxamci_write_protect(sdmmc_chipset_handle_t); 101 1.2.2.2 jym static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 102 1.2.2.2 jym static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 103 1.2.2.2 jym static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 104 1.2.2.2 jym static void pxamci_exec_command(sdmmc_chipset_handle_t, 105 1.2.2.2 jym struct sdmmc_command *); 106 1.2.2.2 jym static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 107 1.2.2.2 jym static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 108 1.2.2.2 jym 109 1.2.2.2 jym static struct sdmmc_chip_functions pxamci_chip_functions = { 110 1.2.2.2 jym /* host controller reset */ 111 1.2.2.2 jym .host_reset = pxamci_host_reset, 112 1.2.2.2 jym 113 1.2.2.2 jym /* host controller capabilities */ 114 1.2.2.2 jym .host_ocr = pxamci_host_ocr, 115 1.2.2.2 jym .host_maxblklen = pxamci_host_maxblklen, 116 1.2.2.2 jym 117 1.2.2.2 jym /* card detection */ 118 1.2.2.2 jym .card_detect = pxamci_card_detect, 119 1.2.2.2 jym 120 1.2.2.2 jym /* write protect */ 121 1.2.2.2 jym .write_protect = pxamci_write_protect, 122 1.2.2.2 jym 123 1.2.2.2 jym /* bus power, clock frequency, width */ 124 1.2.2.2 jym .bus_power = pxamci_bus_power, 125 1.2.2.2 jym .bus_clock = pxamci_bus_clock, 126 1.2.2.2 jym .bus_width = pxamci_bus_width, 127 1.2.2.2 jym 128 1.2.2.2 jym /* command execution */ 129 1.2.2.2 jym .exec_command = pxamci_exec_command, 130 1.2.2.2 jym 131 1.2.2.2 jym /* card interrupt */ 132 1.2.2.2 jym .card_enable_intr = pxamci_card_enable_intr, 133 1.2.2.2 jym .card_intr_ack = pxamci_card_intr_ack, 134 1.2.2.2 jym }; 135 1.2.2.2 jym 136 1.2.2.2 jym static int pxamci_intr(void *); 137 1.2.2.2 jym static void pxamci_intr_cmd(struct pxamci_softc *); 138 1.2.2.2 jym static void pxamci_intr_data(struct pxamci_softc *); 139 1.2.2.2 jym static void pxamci_intr_done(struct pxamci_softc *); 140 1.2.2.2 jym static void pxamci_dmac_iintr(struct dmac_xfer *, int); 141 1.2.2.2 jym static void pxamci_dmac_ointr(struct dmac_xfer *, int); 142 1.2.2.2 jym 143 1.2.2.2 jym static void pxamci_stop_clock(struct pxamci_softc *); 144 1.2.2.2 jym 145 1.2.2.2 jym #define CSR_READ_1(sc, reg) \ 146 1.2.2.2 jym bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 147 1.2.2.2 jym #define CSR_WRITE_1(sc, reg, val) \ 148 1.2.2.2 jym bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 149 1.2.2.2 jym #define CSR_READ_4(sc, reg) \ 150 1.2.2.2 jym bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 151 1.2.2.2 jym #define CSR_WRITE_4(sc, reg, val) \ 152 1.2.2.2 jym bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 153 1.2.2.2 jym #define CSR_SET_4(sc, reg, val) \ 154 1.2.2.2 jym CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 155 1.2.2.2 jym #define CSR_CLR_4(sc, reg, val) \ 156 1.2.2.2 jym CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 157 1.2.2.2 jym 158 1.2.2.2 jym static void 159 1.2.2.2 jym pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 160 1.2.2.2 jym { 161 1.2.2.2 jym int s; 162 1.2.2.2 jym 163 1.2.2.2 jym s = splsdmmc(); 164 1.2.2.2 jym sc->sc_imask &= ~mask; 165 1.2.2.2 jym CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 166 1.2.2.2 jym splx(s); 167 1.2.2.2 jym } 168 1.2.2.2 jym 169 1.2.2.2 jym static void 170 1.2.2.2 jym pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 171 1.2.2.2 jym { 172 1.2.2.2 jym int s; 173 1.2.2.2 jym 174 1.2.2.2 jym s = splsdmmc(); 175 1.2.2.2 jym sc->sc_imask |= mask; 176 1.2.2.2 jym CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 177 1.2.2.2 jym splx(s); 178 1.2.2.2 jym } 179 1.2.2.2 jym 180 1.2.2.2 jym int 181 1.2.2.2 jym pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 182 1.2.2.2 jym { 183 1.2.2.2 jym struct pxamci_softc *sc = device_private(self); 184 1.2.2.2 jym struct sdmmcbus_attach_args saa; 185 1.2.2.2 jym 186 1.2.2.2 jym sc->sc_dev = self; 187 1.2.2.2 jym 188 1.2.2.2 jym aprint_normal(": MMC/SD Controller\n"); 189 1.2.2.2 jym aprint_naive("\n"); 190 1.2.2.2 jym 191 1.2.2.2 jym /* Enable the clocks to the MMC controller. */ 192 1.2.2.2 jym pxa2x0_clkman_config(CKEN_MMC, 1); 193 1.2.2.2 jym 194 1.2.2.2 jym sc->sc_iot = pxa->pxa_iot; 195 1.2.2.2 jym if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 196 1.2.2.2 jym &sc->sc_ioh)) { 197 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 198 1.2.2.2 jym goto out; 199 1.2.2.2 jym } 200 1.2.2.2 jym 201 1.2.2.2 jym /* 202 1.2.2.2 jym * Establish the card detection and MMC interrupt handlers and 203 1.2.2.2 jym * mask all interrupts until we are prepared to handle them. 204 1.2.2.2 jym */ 205 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_ALL); 206 1.2.2.2 jym sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 207 1.2.2.2 jym pxamci_intr, sc); 208 1.2.2.2 jym if (sc->sc_ih == NULL) { 209 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 210 1.2.2.2 jym "couldn't establish MMC interrupt\n"); 211 1.2.2.2 jym goto free_map; 212 1.2.2.2 jym } 213 1.2.2.2 jym 214 1.2.2.2 jym /* 215 1.2.2.2 jym * Reset the host controller and unmask normal interrupts. 216 1.2.2.2 jym */ 217 1.2.2.2 jym (void) pxamci_host_reset(sc); 218 1.2.2.2 jym 219 1.2.2.2 jym /* Setup bus clock */ 220 1.2.2.2 jym if (CPU_IS_PXA270) { 221 1.2.2.2 jym sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 222 1.2.2.2 jym sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 223 1.2.2.2 jym } else { 224 1.2.2.2 jym sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 225 1.2.2.2 jym sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 226 1.2.2.2 jym } 227 1.2.2.2 jym sc->sc_clkbase = sc->sc_clkmin; 228 1.2.2.2 jym pxamci_bus_clock(sc, sc->sc_clkbase); 229 1.2.2.2 jym 230 1.2.2.2 jym /* Setup max block length */ 231 1.2.2.2 jym if (CPU_IS_PXA270) { 232 1.2.2.2 jym sc->sc_maxblklen = 2048; 233 1.2.2.2 jym } else { 234 1.2.2.2 jym sc->sc_maxblklen = 512; 235 1.2.2.2 jym } 236 1.2.2.2 jym 237 1.2.2.2 jym /* Set default bus width */ 238 1.2.2.2 jym sc->sc_buswidth = 1; 239 1.2.2.2 jym 240 1.2.2.2 jym /* setting DMA */ 241 1.2.2.2 jym #if 1 /* XXX */ 242 1.2.2.2 jym SET(sc->sc_caps, PMC_CAPS_NO_DMA); /* disable DMA */ 243 1.2.2.2 jym #endif 244 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 245 1.2.2.2 jym sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 246 1.2.2.2 jym sc->sc_rxdr.ds_len = 1; 247 1.2.2.2 jym sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 248 1.2.2.2 jym if (sc->sc_rxdx == NULL) { 249 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 250 1.2.2.2 jym "couldn't alloc rx dma xfer\n"); 251 1.2.2.2 jym goto free_intr; 252 1.2.2.2 jym } 253 1.2.2.2 jym sc->sc_rxdx->dx_cookie = sc; 254 1.2.2.2 jym sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 255 1.2.2.2 jym sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 256 1.2.2.2 jym sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 257 1.2.2.2 jym sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 258 1.2.2.2 jym sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 259 1.2.2.2 jym sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 260 1.2.2.2 jym sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 261 1.2.2.2 jym sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 262 1.2.2.2 jym sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 263 1.2.2.2 jym sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 264 1.2.2.2 jym sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 265 1.2.2.2 jym 266 1.2.2.2 jym sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 267 1.2.2.2 jym sc->sc_txdr.ds_len = 1; 268 1.2.2.2 jym sc->sc_txdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 269 1.2.2.2 jym if (sc->sc_txdx == NULL) { 270 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 271 1.2.2.2 jym "couldn't alloc tx dma xfer\n"); 272 1.2.2.2 jym goto free_xfer; 273 1.2.2.2 jym } 274 1.2.2.2 jym sc->sc_txdx->dx_cookie = sc; 275 1.2.2.2 jym sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 276 1.2.2.2 jym sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 277 1.2.2.2 jym sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 278 1.2.2.2 jym sc->sc_txdx->dx_done = pxamci_dmac_ointr; 279 1.2.2.2 jym sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 280 1.2.2.2 jym sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 281 1.2.2.2 jym sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 282 1.2.2.2 jym sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 283 1.2.2.2 jym sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 284 1.2.2.2 jym sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 285 1.2.2.2 jym sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 286 1.2.2.2 jym } 287 1.2.2.2 jym 288 1.2.2.2 jym /* 289 1.2.2.2 jym * Attach the generic SD/MMC bus driver. (The bus driver must 290 1.2.2.2 jym * not invoke any chipset functions before it is attached.) 291 1.2.2.2 jym */ 292 1.2.2.2 jym memset(&saa, 0, sizeof(saa)); 293 1.2.2.2 jym saa.saa_busname = "sdmmc"; 294 1.2.2.2 jym saa.saa_sct = &pxamci_chip_functions; 295 1.2.2.2 jym saa.saa_sch = sc; 296 1.2.2.2 jym saa.saa_dmat = pxa->pxa_dmat; 297 1.2.2.2 jym saa.saa_clkmin = sc->sc_clkmin; 298 1.2.2.2 jym saa.saa_clkmax = sc->sc_clkmax; 299 1.2.2.2 jym saa.saa_caps = 0; 300 1.2.2.2 jym #if notyet 301 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 302 1.2.2.2 jym SET(saa.saa_caps, SMC_CAPS_DMA); 303 1.2.2.2 jym if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 304 1.2.2.2 jym SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 305 1.2.2.2 jym #endif 306 1.2.2.2 jym 307 1.2.2.2 jym sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 308 1.2.2.2 jym if (sc->sc_sdmmc == NULL) { 309 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 310 1.2.2.2 jym goto free_xfer; 311 1.2.2.2 jym } 312 1.2.2.2 jym return 0; 313 1.2.2.2 jym 314 1.2.2.2 jym free_xfer: 315 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 316 1.2.2.2 jym if (sc->sc_rxdx) 317 1.2.2.2 jym pxa2x0_dmac_free_xfer(sc->sc_rxdx); 318 1.2.2.2 jym if (sc->sc_txdx) 319 1.2.2.2 jym pxa2x0_dmac_free_xfer(sc->sc_txdx); 320 1.2.2.2 jym } 321 1.2.2.2 jym free_intr: 322 1.2.2.2 jym pxa2x0_intr_disestablish(sc->sc_ih); 323 1.2.2.2 jym sc->sc_ih = NULL; 324 1.2.2.2 jym free_map: 325 1.2.2.2 jym bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 326 1.2.2.2 jym out: 327 1.2.2.2 jym pxa2x0_clkman_config(CKEN_MMC, 0); 328 1.2.2.2 jym return 1; 329 1.2.2.2 jym } 330 1.2.2.2 jym 331 1.2.2.2 jym /* 332 1.2.2.2 jym * Notify card attach/detach event. 333 1.2.2.2 jym */ 334 1.2.2.2 jym void 335 1.2.2.2 jym pxamci_card_detect_event(struct pxamci_softc *sc) 336 1.2.2.2 jym { 337 1.2.2.2 jym 338 1.2.2.2 jym sdmmc_needs_discover(sc->sc_sdmmc); 339 1.2.2.2 jym } 340 1.2.2.2 jym 341 1.2.2.2 jym /* 342 1.2.2.2 jym * Reset the host controller. Called during initialization, when 343 1.2.2.2 jym * cards are removed, upon resume, and during error recovery. 344 1.2.2.2 jym */ 345 1.2.2.2 jym static int 346 1.2.2.2 jym pxamci_host_reset(sdmmc_chipset_handle_t sch) 347 1.2.2.2 jym { 348 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 349 1.2.2.2 jym int s; 350 1.2.2.2 jym 351 1.2.2.2 jym s = splsdmmc(); 352 1.2.2.2 jym 353 1.2.2.2 jym CSR_WRITE_4(sc, MMC_SPI, 0); 354 1.2.2.2 jym CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 355 1.2.2.2 jym CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 356 1.2.2.2 jym 357 1.2.2.2 jym /* Make sure to initialize the card before the next command. */ 358 1.2.2.2 jym CLR(sc->sc_flags, PMF_CARDINITED); 359 1.2.2.2 jym 360 1.2.2.2 jym splx(s); 361 1.2.2.2 jym 362 1.2.2.2 jym return 0; 363 1.2.2.2 jym } 364 1.2.2.2 jym 365 1.2.2.2 jym static uint32_t 366 1.2.2.2 jym pxamci_host_ocr(sdmmc_chipset_handle_t sch) 367 1.2.2.2 jym { 368 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 369 1.2.2.2 jym int rv; 370 1.2.2.2 jym 371 1.2.2.2 jym if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 372 1.2.2.2 jym rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 373 1.2.2.2 jym return rv; 374 1.2.2.2 jym } 375 1.2.2.2 jym 376 1.2.2.2 jym DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 377 1.2.2.2 jym device_xname(sc->sc_dev))); 378 1.2.2.2 jym return ENXIO; 379 1.2.2.2 jym } 380 1.2.2.2 jym 381 1.2.2.2 jym static int 382 1.2.2.2 jym pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 383 1.2.2.2 jym { 384 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 385 1.2.2.2 jym 386 1.2.2.2 jym return sc->sc_maxblklen; 387 1.2.2.2 jym } 388 1.2.2.2 jym 389 1.2.2.2 jym static int 390 1.2.2.2 jym pxamci_card_detect(sdmmc_chipset_handle_t sch) 391 1.2.2.2 jym { 392 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 393 1.2.2.2 jym 394 1.2.2.2 jym if (__predict_true(sc->sc_tag.card_detect != NULL)) { 395 1.2.2.2 jym return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 396 1.2.2.2 jym } 397 1.2.2.2 jym 398 1.2.2.2 jym DPRINTF(0,("%s: driver lacks card_detect() function.\n", 399 1.2.2.2 jym device_xname(sc->sc_dev))); 400 1.2.2.2 jym return 1; /* always detect */ 401 1.2.2.2 jym } 402 1.2.2.2 jym 403 1.2.2.2 jym static int 404 1.2.2.2 jym pxamci_write_protect(sdmmc_chipset_handle_t sch) 405 1.2.2.2 jym { 406 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 407 1.2.2.2 jym 408 1.2.2.2 jym if (__predict_true(sc->sc_tag.write_protect != NULL)) { 409 1.2.2.2 jym return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 410 1.2.2.2 jym } 411 1.2.2.2 jym 412 1.2.2.2 jym DPRINTF(0,("%s: driver lacks write_protect() function.\n", 413 1.2.2.2 jym device_xname(sc->sc_dev))); 414 1.2.2.2 jym return 0; /* non-protect */ 415 1.2.2.2 jym } 416 1.2.2.2 jym 417 1.2.2.2 jym /* 418 1.2.2.2 jym * Set or change SD bus voltage and enable or disable SD bus power. 419 1.2.2.2 jym * Return zero on success. 420 1.2.2.2 jym */ 421 1.2.2.2 jym static int 422 1.2.2.2 jym pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 423 1.2.2.2 jym { 424 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 425 1.2.2.2 jym 426 1.2.2.2 jym /* 427 1.2.2.2 jym * Bus power management is beyond control of the SD/SDIO/MMC 428 1.2.2.2 jym * block of the PXA2xx processors, so we have to hand this 429 1.2.2.2 jym * task off to the attachment driver. 430 1.2.2.2 jym */ 431 1.2.2.2 jym if (__predict_true(sc->sc_tag.set_power != NULL)) { 432 1.2.2.2 jym return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 433 1.2.2.2 jym } 434 1.2.2.2 jym 435 1.2.2.2 jym DPRINTF(0,("%s: driver lacks set_power() function\n", 436 1.2.2.2 jym device_xname(sc->sc_dev))); 437 1.2.2.2 jym return ENXIO; 438 1.2.2.2 jym } 439 1.2.2.2 jym 440 1.2.2.2 jym /* 441 1.2.2.2 jym * Set or change MMCLK frequency or disable the MMC clock. 442 1.2.2.2 jym * Return zero on success. 443 1.2.2.2 jym */ 444 1.2.2.2 jym static int 445 1.2.2.2 jym pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 446 1.2.2.2 jym { 447 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 448 1.2.2.2 jym int actfreq; 449 1.2.2.2 jym int div; 450 1.2.2.2 jym int rv = 0; 451 1.2.2.2 jym int s; 452 1.2.2.2 jym 453 1.2.2.2 jym s = splsdmmc(); 454 1.2.2.2 jym 455 1.2.2.2 jym /* 456 1.2.2.2 jym * Stop MMC clock before changing the frequency. 457 1.2.2.2 jym */ 458 1.2.2.2 jym pxamci_stop_clock(sc); 459 1.2.2.2 jym 460 1.2.2.2 jym /* Just stop the clock. */ 461 1.2.2.2 jym if (freq == 0) 462 1.2.2.2 jym goto out; 463 1.2.2.2 jym 464 1.2.2.2 jym /* 465 1.2.2.2 jym * PXA27x Errata... 466 1.2.2.2 jym * 467 1.2.2.2 jym * <snip> 468 1.2.2.2 jym * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 469 1.2.2.2 jym * 470 1.2.2.2 jym * SD/SDIO controller can only support up to 9.75 Mbps data 471 1.2.2.2 jym * transfer rate for SDIO card. 472 1.2.2.2 jym * </snip> 473 1.2.2.2 jym * 474 1.2.2.2 jym * If we don't limit the frequency, CRC errors will be 475 1.2.2.2 jym * reported by the controller after we set the bus speed. 476 1.2.2.2 jym * XXX slow down incrementally. 477 1.2.2.2 jym */ 478 1.2.2.2 jym if (CPU_IS_PXA270) { 479 1.2.2.2 jym if (freq > 9750) { 480 1.2.2.2 jym freq = 9750; 481 1.2.2.2 jym } 482 1.2.2.2 jym } 483 1.2.2.2 jym 484 1.2.2.2 jym /* 485 1.2.2.2 jym * Pick the smallest divider that produces a frequency not 486 1.2.2.2 jym * more than `freq' KHz. 487 1.2.2.2 jym */ 488 1.2.2.2 jym actfreq = sc->sc_clkmax; 489 1.2.2.2 jym for (div = 0; div < 7; actfreq /= 2, div++) { 490 1.2.2.2 jym if (actfreq <= freq) 491 1.2.2.2 jym break; 492 1.2.2.2 jym } 493 1.2.2.2 jym if (div == 7) { 494 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 495 1.2.2.2 jym "unsupported bus frequency of %d KHz\n", freq); 496 1.2.2.2 jym rv = 1; 497 1.2.2.2 jym goto out; 498 1.2.2.2 jym } 499 1.2.2.2 jym 500 1.2.2.2 jym DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 501 1.2.2.2 jym device_xname(sc->sc_dev), freq, actfreq, div)); 502 1.2.2.2 jym 503 1.2.2.2 jym sc->sc_clkbase = actfreq; 504 1.2.2.2 jym sc->sc_clkrt = div; 505 1.2.2.2 jym 506 1.2.2.2 jym out: 507 1.2.2.2 jym splx(s); 508 1.2.2.2 jym 509 1.2.2.2 jym return rv; 510 1.2.2.2 jym } 511 1.2.2.2 jym 512 1.2.2.2 jym static int 513 1.2.2.2 jym pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 514 1.2.2.2 jym { 515 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 516 1.2.2.2 jym int rv = 0; 517 1.2.2.2 jym int s; 518 1.2.2.2 jym 519 1.2.2.2 jym s = splsdmmc(); 520 1.2.2.2 jym 521 1.2.2.2 jym switch (width) { 522 1.2.2.2 jym case 1: 523 1.2.2.2 jym break; 524 1.2.2.2 jym case 4: 525 1.2.2.2 jym if (CPU_IS_PXA270) 526 1.2.2.2 jym break; 527 1.2.2.2 jym /*FALLTHROUGH*/ 528 1.2.2.2 jym default: 529 1.2.2.2 jym DPRINTF(0,("%s: unsupported bus width (%d)\n", 530 1.2.2.2 jym device_xname(sc->sc_dev), width)); 531 1.2.2.2 jym rv = 1; 532 1.2.2.2 jym goto out; 533 1.2.2.2 jym } 534 1.2.2.2 jym 535 1.2.2.2 jym sc->sc_buswidth = width; 536 1.2.2.2 jym 537 1.2.2.2 jym out: 538 1.2.2.2 jym splx(s); 539 1.2.2.2 jym 540 1.2.2.2 jym return rv; 541 1.2.2.2 jym } 542 1.2.2.2 jym 543 1.2.2.2 jym static void 544 1.2.2.2 jym pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 545 1.2.2.2 jym { 546 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 547 1.2.2.2 jym uint32_t cmdat; 548 1.2.2.2 jym int error; 549 1.2.2.2 jym int timo; 550 1.2.2.2 jym int s; 551 1.2.2.2 jym 552 1.2.2.2 jym DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x " 553 1.2.2.2 jym "proc=%p \"%s\"\n", device_xname(sc->sc_dev), 554 1.2.2.2 jym cmd->c_opcode, cmd->c_arg, cmd->c_data, cmd->c_datalen, 555 1.2.2.2 jym cmd->c_flags, curproc, curproc ? curproc->p_comm : "")); 556 1.2.2.2 jym 557 1.2.2.2 jym s = splsdmmc(); 558 1.2.2.2 jym 559 1.2.2.2 jym /* Stop the bus clock (MMCLK). [15.8.3] */ 560 1.2.2.2 jym pxamci_stop_clock(sc); 561 1.2.2.2 jym 562 1.2.2.2 jym /* Set the command and argument. */ 563 1.2.2.2 jym CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 564 1.2.2.2 jym CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 565 1.2.2.2 jym CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 566 1.2.2.2 jym 567 1.2.2.2 jym /* Response type */ 568 1.2.2.2 jym if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 569 1.2.2.2 jym cmdat = CMDAT_RESPONSE_FORMAT_NO; 570 1.2.2.2 jym else if (ISSET(cmd->c_flags, SCF_RSP_136)) 571 1.2.2.2 jym cmdat = CMDAT_RESPONSE_FORMAT_R2; 572 1.2.2.2 jym else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 573 1.2.2.2 jym cmdat = CMDAT_RESPONSE_FORMAT_R3; 574 1.2.2.2 jym else 575 1.2.2.2 jym cmdat = CMDAT_RESPONSE_FORMAT_R1; 576 1.2.2.2 jym 577 1.2.2.2 jym if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 578 1.2.2.2 jym cmdat |= CMDAT_BUSY; 579 1.2.2.2 jym if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 580 1.2.2.2 jym cmdat |= CMDAT_WRITE; 581 1.2.2.2 jym if (sc->sc_buswidth == 4) 582 1.2.2.2 jym cmdat |= CMDAT_SD_4DAT; 583 1.2.2.2 jym 584 1.2.2.2 jym /* Fragment the data into proper blocks. */ 585 1.2.2.2 jym if (cmd->c_datalen > 0) { 586 1.2.2.2 jym int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 587 1.2.2.2 jym int numblk = cmd->c_datalen / blklen; 588 1.2.2.2 jym 589 1.2.2.2 jym if (cmd->c_datalen % blklen > 0) { 590 1.2.2.2 jym /* XXX: Split this command. (1.7.4) */ 591 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 592 1.2.2.2 jym "data not a multiple of %u bytes\n", blklen); 593 1.2.2.2 jym cmd->c_error = EINVAL; 594 1.2.2.2 jym goto out; 595 1.2.2.2 jym } 596 1.2.2.2 jym 597 1.2.2.2 jym /* Check limit imposed by block count. */ 598 1.2.2.2 jym if (numblk > NOB_MASK) { 599 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "too much data\n"); 600 1.2.2.2 jym cmd->c_error = EINVAL; 601 1.2.2.2 jym goto out; 602 1.2.2.2 jym } 603 1.2.2.2 jym 604 1.2.2.2 jym CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 605 1.2.2.2 jym CSR_WRITE_4(sc, MMC_NOB, numblk); 606 1.2.2.2 jym CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 607 1.2.2.2 jym 608 1.2.2.2 jym cmdat |= CMDAT_DATA_EN; 609 1.2.2.2 jym 610 1.2.2.2 jym /* setting DMA */ 611 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 612 1.2.2.2 jym struct dmac_xfer_desc *dx_desc; 613 1.2.2.2 jym 614 1.2.2.2 jym cmdat |= CMDAT_MMC_DMA_EN; 615 1.2.2.2 jym 616 1.2.2.2 jym if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 617 1.2.2.2 jym dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 618 1.2.2.2 jym dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 619 1.2.2.2 jym dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 620 1.2.2.2 jym error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 621 1.2.2.2 jym } else { 622 1.2.2.2 jym dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 623 1.2.2.2 jym dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 624 1.2.2.2 jym dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 625 1.2.2.2 jym /* workaround for erratum #91 */ 626 1.2.2.2 jym error = 0; 627 1.2.2.2 jym if (!CPU_IS_PXA270) { 628 1.2.2.2 jym error = 629 1.2.2.2 jym pxa2x0_dmac_start_xfer(sc->sc_txdx); 630 1.2.2.2 jym } 631 1.2.2.2 jym } 632 1.2.2.2 jym if (error) { 633 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 634 1.2.2.2 jym "couldn't start dma xfer. (error=%d)\n", 635 1.2.2.2 jym error); 636 1.2.2.2 jym cmd->c_error = EIO; 637 1.2.2.2 jym goto err; 638 1.2.2.2 jym } 639 1.2.2.2 jym } else { 640 1.2.2.2 jym cmd->c_resid = cmd->c_datalen; 641 1.2.2.2 jym cmd->c_buf = cmd->c_data; 642 1.2.2.2 jym 643 1.2.2.2 jym pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 644 1.2.2.2 jym | MMC_I_TXFIFO_WR_REQ 645 1.2.2.2 jym | MMC_I_DAT_ERR); 646 1.2.2.2 jym } 647 1.2.2.2 jym } 648 1.2.2.2 jym 649 1.2.2.2 jym sc->sc_cmd = cmd; 650 1.2.2.2 jym 651 1.2.2.2 jym /* 652 1.2.2.2 jym * "After reset, the MMC card must be initialized by sending 653 1.2.2.2 jym * 80 clocks to it on the MMCLK signal." [15.4.3.2] 654 1.2.2.2 jym */ 655 1.2.2.2 jym if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 656 1.2.2.2 jym DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 657 1.2.2.2 jym cmdat |= CMDAT_INIT; 658 1.2.2.2 jym SET(sc->sc_flags, PMF_CARDINITED); 659 1.2.2.2 jym } 660 1.2.2.2 jym 661 1.2.2.2 jym /* Begin the transfer and start the bus clock. */ 662 1.2.2.2 jym CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 663 1.2.2.2 jym CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 664 1.2.2.2 jym CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 665 1.2.2.2 jym 666 1.2.2.2 jym /* Wait for it to complete */ 667 1.2.2.2 jym pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 668 1.2.2.2 jym for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 669 1.2.2.2 jym tsleep(sc, PWAIT, "mmcmd", hz); 670 1.2.2.2 jym } 671 1.2.2.2 jym 672 1.2.2.2 jym /* If it completed in time, SCF_ITSDONE is already set. */ 673 1.2.2.2 jym if (sc->sc_cmd == cmd) { 674 1.2.2.2 jym cmd->c_error = ETIMEDOUT; 675 1.2.2.2 jym err: 676 1.2.2.2 jym SET(cmd->c_flags, SCF_ITSDONE); 677 1.2.2.2 jym sc->sc_cmd = NULL; 678 1.2.2.2 jym goto out; 679 1.2.2.2 jym } 680 1.2.2.2 jym 681 1.2.2.2 jym out: 682 1.2.2.2 jym splx(s); 683 1.2.2.2 jym 684 1.2.2.2 jym DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 685 1.2.2.2 jym device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 686 1.2.2.2 jym } 687 1.2.2.2 jym 688 1.2.2.2 jym static void 689 1.2.2.2 jym pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 690 1.2.2.2 jym { 691 1.2.2.2 jym struct pxamci_softc *sc = (struct pxamci_softc *)sch; 692 1.2.2.2 jym 693 1.2.2.2 jym if (enable) { 694 1.2.2.2 jym pxamci_enable_intr(sc, MMC_I_SDIO_INT); 695 1.2.2.2 jym } else { 696 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_SDIO_INT); 697 1.2.2.2 jym } 698 1.2.2.2 jym } 699 1.2.2.2 jym 700 1.2.2.2 jym static void 701 1.2.2.2 jym pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 702 1.2.2.2 jym { 703 1.2.2.2 jym 704 1.2.2.2 jym /* Nothing to do */ 705 1.2.2.2 jym } 706 1.2.2.2 jym 707 1.2.2.2 jym static void 708 1.2.2.2 jym pxamci_stop_clock(struct pxamci_softc *sc) 709 1.2.2.2 jym { 710 1.2.2.2 jym int timo = STOPCLK_TIMO; 711 1.2.2.2 jym 712 1.2.2.2 jym if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 713 1.2.2.2 jym CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 714 1.2.2.2 jym CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 715 1.2.2.2 jym while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 716 1.2.2.2 jym && (timo-- > 0)) { 717 1.2.2.2 jym tsleep(sc, PWAIT, "mmclk", hz); 718 1.2.2.2 jym } 719 1.2.2.2 jym } 720 1.2.2.2 jym if (timo == 0) 721 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 722 1.2.2.2 jym } 723 1.2.2.2 jym 724 1.2.2.2 jym /* 725 1.2.2.2 jym * SD/MMC controller interrput handler 726 1.2.2.2 jym */ 727 1.2.2.2 jym static int 728 1.2.2.2 jym pxamci_intr(void *arg) 729 1.2.2.2 jym { 730 1.2.2.2 jym struct pxamci_softc *sc = arg; 731 1.2.2.2 jym int status; 732 1.2.2.2 jym #ifdef PXAMCI_DEBUG 733 1.2.2.2 jym int ostatus; 734 1.2.2.2 jym 735 1.2.2.2 jym ostatus = 736 1.2.2.2 jym #endif 737 1.2.2.2 jym status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 738 1.2.2.2 jym DPRINTF(9,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 739 1.2.2.2 jym status)); 740 1.2.2.2 jym 741 1.2.2.2 jym /* 742 1.2.2.2 jym * Notify the process waiting in pxamci_clock_stop() when 743 1.2.2.2 jym * the clock has really stopped. 744 1.2.2.2 jym */ 745 1.2.2.2 jym if (ISSET(status, MMC_I_CLK_IS_OFF)) { 746 1.2.2.2 jym DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 747 1.2.2.2 jym wakeup(sc); 748 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 749 1.2.2.2 jym CLR(status, MMC_I_CLK_IS_OFF); 750 1.2.2.2 jym } 751 1.2.2.2 jym 752 1.2.2.2 jym if (sc->sc_cmd == NULL) 753 1.2.2.2 jym goto end; 754 1.2.2.2 jym 755 1.2.2.2 jym if (ISSET(status, MMC_I_RES_ERR)) { 756 1.2.2.2 jym DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 757 1.2.2.2 jym device_xname(sc->sc_dev))); 758 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_RES_ERR); 759 1.2.2.2 jym CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 760 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 761 1.2.2.2 jym && (sc->sc_cmd->c_datalen > 0)) { 762 1.2.2.2 jym if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 763 1.2.2.2 jym pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 764 1.2.2.2 jym } else { 765 1.2.2.2 jym pxa2x0_dmac_abort_xfer(sc->sc_txdx); 766 1.2.2.2 jym } 767 1.2.2.2 jym } 768 1.2.2.2 jym sc->sc_cmd->c_error = ENOEXEC; 769 1.2.2.2 jym pxamci_intr_done(sc); 770 1.2.2.2 jym goto end; 771 1.2.2.2 jym } 772 1.2.2.2 jym 773 1.2.2.2 jym if (ISSET(status, MMC_I_END_CMD_RES)) { 774 1.2.2.2 jym DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 775 1.2.2.2 jym device_xname(sc->sc_dev))); 776 1.2.2.2 jym pxamci_intr_cmd(sc); 777 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 778 1.2.2.2 jym CLR(status, MMC_I_END_CMD_RES); 779 1.2.2.2 jym /* ignore programming done condition */ 780 1.2.2.2 jym if (ISSET(status, MMC_I_PRG_DONE)) { 781 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_PRG_DONE); 782 1.2.2.2 jym CLR(status, MMC_I_PRG_DONE); 783 1.2.2.2 jym } 784 1.2.2.2 jym if (sc->sc_cmd == NULL) 785 1.2.2.2 jym goto end; 786 1.2.2.2 jym } 787 1.2.2.2 jym 788 1.2.2.2 jym if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 789 1.2.2.2 jym DPRINTF(9,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 790 1.2.2.2 jym device_xname(sc->sc_dev))); 791 1.2.2.2 jym CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 792 1.2.2.2 jym pxamci_intr_data(sc); 793 1.2.2.2 jym } 794 1.2.2.2 jym 795 1.2.2.2 jym if (ISSET(status, MMC_I_DAT_ERR)) { 796 1.2.2.2 jym DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 797 1.2.2.2 jym device_xname(sc->sc_dev))); 798 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_DAT_ERR); 799 1.2.2.2 jym CLR(status, MMC_I_DAT_ERR); 800 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 801 1.2.2.2 jym && (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ))) { 802 1.2.2.2 jym pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 803 1.2.2.2 jym } else { 804 1.2.2.2 jym pxa2x0_dmac_abort_xfer(sc->sc_txdx); 805 1.2.2.2 jym } 806 1.2.2.2 jym sc->sc_cmd->c_error = EIO; 807 1.2.2.2 jym pxamci_intr_done(sc); 808 1.2.2.2 jym /* ignore transmission done condition */ 809 1.2.2.2 jym if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 810 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 811 1.2.2.2 jym CLR(status, MMC_I_DATA_TRAN_DONE); 812 1.2.2.2 jym } 813 1.2.2.2 jym goto end; 814 1.2.2.2 jym } 815 1.2.2.2 jym 816 1.2.2.2 jym if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 817 1.2.2.2 jym DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 818 1.2.2.2 jym device_xname(sc->sc_dev))); 819 1.2.2.2 jym pxamci_intr_done(sc); 820 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 821 1.2.2.2 jym CLR(status, MMC_I_DATA_TRAN_DONE); 822 1.2.2.2 jym } 823 1.2.2.2 jym 824 1.2.2.2 jym if (ISSET(status, STAT_SDIO_INT)) { 825 1.2.2.2 jym DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 826 1.2.2.2 jym device_xname(sc->sc_dev))); 827 1.2.2.2 jym sdmmc_card_intr(sc->sc_sdmmc); 828 1.2.2.2 jym CLR(status, STAT_SDIO_INT); 829 1.2.2.2 jym } 830 1.2.2.2 jym 831 1.2.2.2 jym end: 832 1.2.2.2 jym /* Avoid further unhandled interrupts. */ 833 1.2.2.2 jym if (status != 0) { 834 1.2.2.2 jym pxamci_disable_intr(sc, status); 835 1.2.2.2 jym #ifdef PXAMCI_DEBUG 836 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 837 1.2.2.2 jym "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 838 1.2.2.2 jym #endif 839 1.2.2.2 jym } 840 1.2.2.2 jym return 1; 841 1.2.2.2 jym } 842 1.2.2.2 jym 843 1.2.2.2 jym static void 844 1.2.2.2 jym pxamci_intr_cmd(struct pxamci_softc *sc) 845 1.2.2.2 jym { 846 1.2.2.2 jym struct sdmmc_command *cmd = sc->sc_cmd; 847 1.2.2.2 jym uint32_t status; 848 1.2.2.2 jym int error; 849 1.2.2.2 jym int i; 850 1.2.2.2 jym 851 1.2.2.2 jym KASSERT(sc->sc_cmd != NULL); 852 1.2.2.2 jym 853 1.2.2.2 jym #define STAT_ERR (STAT_READ_TIME_OUT \ 854 1.2.2.2 jym | STAT_TIMEOUT_RESPONSE \ 855 1.2.2.2 jym | STAT_CRC_WRITE_ERROR \ 856 1.2.2.2 jym | STAT_CRC_READ_ERROR \ 857 1.2.2.2 jym | STAT_SPI_READ_ERROR_TOKEN) 858 1.2.2.2 jym 859 1.2.2.2 jym if (ISSET(cmd->c_flags, SCF_RSP_136)) { 860 1.2.2.2 jym for (i = 3; i >= 0; i--) { 861 1.2.2.2 jym uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 862 1.2.2.2 jym uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 863 1.2.2.2 jym cmd->c_resp[i] = (h << 16) | l; 864 1.2.2.2 jym } 865 1.2.2.2 jym cmd->c_error = 0; 866 1.2.2.2 jym } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 867 1.2.2.2 jym /* 868 1.2.2.2 jym * Grrr... The processor manual is not clear about 869 1.2.2.2 jym * the layout of the response FIFO. It just states 870 1.2.2.2 jym * that the FIFO is 16 bits wide, has a depth of 8, 871 1.2.2.2 jym * and that the CRC is not copied into the FIFO. 872 1.2.2.2 jym * 873 1.2.2.2 jym * A 16-bit word in the FIFO is filled from highest 874 1.2.2.2 jym * to lowest bit as the response comes in. The two 875 1.2.2.2 jym * start bits and the 6 command index bits are thus 876 1.2.2.2 jym * stored in the upper 8 bits of the first 16-bit 877 1.2.2.2 jym * word that we read back from the FIFO. 878 1.2.2.2 jym * 879 1.2.2.2 jym * Since the sdmmc(4) framework expects the host 880 1.2.2.2 jym * controller to discard the first 8 bits of the 881 1.2.2.2 jym * response, what we must do is discard the upper 882 1.2.2.2 jym * byte of the first 16-bit word. 883 1.2.2.2 jym */ 884 1.2.2.2 jym uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 885 1.2.2.2 jym uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 886 1.2.2.2 jym uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 887 1.2.2.2 jym cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 888 1.2.2.2 jym for (i = 1; i < 4; i++) 889 1.2.2.2 jym cmd->c_resp[i] = 0; 890 1.2.2.2 jym cmd->c_error = 0; 891 1.2.2.2 jym } 892 1.2.2.2 jym 893 1.2.2.2 jym status = CSR_READ_4(sc, MMC_STAT); 894 1.2.2.2 jym 895 1.2.2.2 jym if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 896 1.2.2.2 jym CLR(status, STAT_TIMEOUT_RESPONSE); 897 1.2.2.2 jym 898 1.2.2.2 jym /* XXX only for R6, not for R2 */ 899 1.2.2.2 jym if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 900 1.2.2.2 jym CLR(status, STAT_RES_CRC_ERR); 901 1.2.2.2 jym 902 1.2.2.2 jym if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 903 1.2.2.2 jym cmd->c_error = ETIMEDOUT; 904 1.2.2.2 jym else if (ISSET(status, STAT_RES_CRC_ERR) 905 1.2.2.2 jym && ISSET(cmd->c_flags, SCF_RSP_CRC) 906 1.2.2.2 jym && CPU_IS_PXA270) { 907 1.2.2.2 jym /* workaround for erratum #42 */ 908 1.2.2.2 jym if (ISSET(cmd->c_flags, SCF_RSP_136) 909 1.2.2.2 jym && (cmd->c_resp[0] & 0x80000000U)) { 910 1.2.2.2 jym DPRINTF(1,("%s: ignore CRC error\n", 911 1.2.2.2 jym device_xname(sc->sc_dev))); 912 1.2.2.2 jym } else 913 1.2.2.2 jym cmd->c_error = EIO; 914 1.2.2.2 jym } else if (ISSET(status, STAT_ERR)) 915 1.2.2.2 jym cmd->c_error = EIO; 916 1.2.2.2 jym 917 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 918 1.2.2.2 jym if (cmd->c_error == 0 && cmd->c_datalen > 0) { 919 1.2.2.2 jym /* workaround for erratum #91 */ 920 1.2.2.2 jym if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 921 1.2.2.2 jym && CPU_IS_PXA270 922 1.2.2.2 jym && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 923 1.2.2.2 jym error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 924 1.2.2.2 jym if (error) { 925 1.2.2.2 jym aprint_error_dev(sc->sc_dev, 926 1.2.2.2 jym "couldn't start dma xfer. (error=%d)\n", 927 1.2.2.2 jym error); 928 1.2.2.2 jym cmd->c_error = EIO; 929 1.2.2.2 jym pxamci_intr_done(sc); 930 1.2.2.2 jym return; 931 1.2.2.2 jym } 932 1.2.2.2 jym } 933 1.2.2.2 jym pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 934 1.2.2.2 jym } else { 935 1.2.2.2 jym pxamci_intr_done(sc); 936 1.2.2.2 jym } 937 1.2.2.2 jym } 938 1.2.2.2 jym 939 1.2.2.2 jym static void 940 1.2.2.2 jym pxamci_intr_data(struct pxamci_softc *sc) 941 1.2.2.2 jym { 942 1.2.2.2 jym struct sdmmc_command *cmd = sc->sc_cmd; 943 1.2.2.2 jym int intr; 944 1.2.2.2 jym int n; 945 1.2.2.2 jym 946 1.2.2.2 jym DPRINTF(1,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 947 1.2.2.2 jym device_xname(sc->sc_dev), cmd, cmd->c_resid)); 948 1.2.2.2 jym 949 1.2.2.2 jym n = MIN(32, cmd->c_resid); 950 1.2.2.2 jym cmd->c_resid -= n; 951 1.2.2.2 jym 952 1.2.2.2 jym if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 953 1.2.2.2 jym intr = MMC_I_RXFIFO_RD_REQ; 954 1.2.2.2 jym while (n-- > 0) 955 1.2.2.2 jym *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 956 1.2.2.2 jym } else { 957 1.2.2.2 jym int short_xfer = n < 32; 958 1.2.2.2 jym 959 1.2.2.2 jym intr = MMC_I_TXFIFO_WR_REQ; 960 1.2.2.2 jym while (n-- > 0) 961 1.2.2.2 jym CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 962 1.2.2.2 jym if (short_xfer) 963 1.2.2.2 jym CSR_WRITE_4(sc, MMC_PRTBUF, 1); 964 1.2.2.2 jym } 965 1.2.2.2 jym 966 1.2.2.2 jym if (cmd->c_resid > 0) { 967 1.2.2.2 jym pxamci_enable_intr(sc, intr); 968 1.2.2.2 jym } else { 969 1.2.2.2 jym pxamci_disable_intr(sc, intr); 970 1.2.2.2 jym } 971 1.2.2.2 jym } 972 1.2.2.2 jym 973 1.2.2.2 jym /* 974 1.2.2.2 jym * Wake up the process sleeping in pxamci_exec_command(). 975 1.2.2.2 jym */ 976 1.2.2.2 jym static void 977 1.2.2.2 jym pxamci_intr_done(struct pxamci_softc *sc) 978 1.2.2.2 jym { 979 1.2.2.2 jym #ifdef PXAMCI_DEBUG 980 1.2.2.2 jym uint32_t status; 981 1.2.2.2 jym 982 1.2.2.2 jym status = CSR_READ_4(sc, MMC_STAT); 983 1.2.2.2 jym DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 984 1.2.2.2 jym device_xname(sc->sc_dev), status)); 985 1.2.2.2 jym #endif 986 1.2.2.2 jym 987 1.2.2.2 jym pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 988 1.2.2.2 jym SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 989 1.2.2.2 jym sc->sc_cmd = NULL; 990 1.2.2.2 jym wakeup(sc); 991 1.2.2.2 jym } 992 1.2.2.2 jym 993 1.2.2.2 jym static void 994 1.2.2.2 jym pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 995 1.2.2.2 jym { 996 1.2.2.2 jym struct pxamci_softc *sc = dx->dx_cookie; 997 1.2.2.2 jym 998 1.2.2.2 jym if (status) { 999 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1000 1.2.2.2 jym "non-zero completion status %d\n", status); 1001 1.2.2.2 jym } 1002 1.2.2.2 jym } 1003 1.2.2.2 jym 1004 1.2.2.2 jym static void 1005 1.2.2.2 jym pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1006 1.2.2.2 jym { 1007 1.2.2.2 jym struct pxamci_softc *sc = dx->dx_cookie; 1008 1.2.2.2 jym 1009 1.2.2.2 jym if (status) { 1010 1.2.2.2 jym aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1011 1.2.2.2 jym "non-zero completion status %d\n", status); 1012 1.2.2.2 jym } 1013 1.2.2.2 jym } 1014
Indexes created Tue Oct 21 16:10:11 GMT 2025