pxa2x0_mci.c revision 1.1
1 /* $NetBSD: pxa2x0_mci.c,v 1.1 2009/04/21 03:00:29 nonaka Exp $ */ 2 /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (c) 2007-2009 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 /* 47 * MMC/SD/SDIO controller driver for Intel PXA2xx processors 48 * 49 * Power management is beyond control of the processor's SD/SDIO/MMC 50 * block, so this driver depends on the attachment driver to provide 51 * us with some callback functions via the "tag" member in our softc. 52 * Bus power management calls are then dispatched to the attachment 53 * driver. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.1 2009/04/21 03:00:29 nonaka Exp $"); 58 59 #include <sys/param.h> 60 #include <sys/device.h> 61 #include <sys/systm.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/proc.h> 65 #include <sys/bus.h> 66 #include <sys/mutex.h> 67 #include <sys/condvar.h> 68 69 #include <machine/intr.h> 70 71 #include <dev/sdmmc/sdmmcvar.h> 72 #include <dev/sdmmc/sdmmcchip.h> 73 74 #include <arm/xscale/pxa2x0cpu.h> 75 #include <arm/xscale/pxa2x0reg.h> 76 #include <arm/xscale/pxa2x0var.h> 77 #include <arm/xscale/pxa2x0_dmac.h> 78 #include <arm/xscale/pxa2x0_gpio.h> 79 #include <arm/xscale/pxa2x0_mci.h> 80 81 #ifdef PXAMCI_DEBUG 82 int pxamci_debug = 1; 83 #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 84 #else 85 #define DPRINTF(n,s) do {} while (0) 86 #endif 87 88 #ifndef DEBUG 89 #define STOPCLK_TIMO 2 /* ms */ 90 #define EXECCMD_TIMO 2 /* ms */ 91 #else 92 #define STOPCLK_TIMO 2 /* ms */ 93 #define EXECCMD_TIMO 5 /* ms */ 94 #endif 95 96 static int pxamci_host_reset(sdmmc_chipset_handle_t); 97 static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 98 static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 99 static int pxamci_card_detect(sdmmc_chipset_handle_t); 100 static int pxamci_write_protect(sdmmc_chipset_handle_t); 101 static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 102 static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 103 static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 104 static void pxamci_exec_command(sdmmc_chipset_handle_t, 105 struct sdmmc_command *); 106 static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 107 static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 108 109 static struct sdmmc_chip_functions pxamci_chip_functions = { 110 /* host controller reset */ 111 .host_reset = pxamci_host_reset, 112 113 /* host controller capabilities */ 114 .host_ocr = pxamci_host_ocr, 115 .host_maxblklen = pxamci_host_maxblklen, 116 117 /* card detection */ 118 .card_detect = pxamci_card_detect, 119 120 /* write protect */ 121 .write_protect = pxamci_write_protect, 122 123 /* bus power, clock frequency, width */ 124 .bus_power = pxamci_bus_power, 125 .bus_clock = pxamci_bus_clock, 126 .bus_width = pxamci_bus_width, 127 128 /* command execution */ 129 .exec_command = pxamci_exec_command, 130 131 /* card interrupt */ 132 .card_enable_intr = pxamci_card_enable_intr, 133 .card_intr_ack = pxamci_card_intr_ack, 134 }; 135 136 static int pxamci_intr(void *); 137 static void pxamci_intr_cmd(struct pxamci_softc *); 138 static void pxamci_intr_data(struct pxamci_softc *); 139 static void pxamci_intr_done(struct pxamci_softc *); 140 static void pxamci_dmac_iintr(struct dmac_xfer *, int); 141 static void pxamci_dmac_ointr(struct dmac_xfer *, int); 142 143 static void pxamci_stop_clock(struct pxamci_softc *); 144 145 #define CSR_READ_1(sc, reg) \ 146 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 147 #define CSR_WRITE_1(sc, reg, val) \ 148 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 149 #define CSR_READ_4(sc, reg) \ 150 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 151 #define CSR_WRITE_4(sc, reg, val) \ 152 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 153 #define CSR_SET_4(sc, reg, val) \ 154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 155 #define CSR_CLR_4(sc, reg, val) \ 156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 157 158 static void 159 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 160 { 161 int s; 162 163 s = splsdmmc(); 164 sc->sc_imask &= ~mask; 165 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 166 splx(s); 167 } 168 169 static void 170 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 171 { 172 int s; 173 174 s = splsdmmc(); 175 sc->sc_imask |= mask; 176 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 177 splx(s); 178 } 179 180 int 181 pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 182 { 183 struct pxamci_softc *sc = device_private(self); 184 struct sdmmcbus_attach_args saa; 185 186 sc->sc_dev = self; 187 188 aprint_normal(": MMC/SD Controller\n"); 189 aprint_naive("\n"); 190 191 /* Enable the clocks to the MMC controller. */ 192 pxa2x0_clkman_config(CKEN_MMC, 1); 193 194 sc->sc_iot = pxa->pxa_iot; 195 if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 196 &sc->sc_ioh)) { 197 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 198 goto out; 199 } 200 201 /* 202 * Establish the card detection and MMC interrupt handlers and 203 * mask all interrupts until we are prepared to handle them. 204 */ 205 pxamci_disable_intr(sc, MMC_I_ALL); 206 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 207 pxamci_intr, sc); 208 if (sc->sc_ih == NULL) { 209 aprint_error_dev(sc->sc_dev, 210 "couldn't establish MMC interrupt\n"); 211 goto free_map; 212 } 213 214 /* 215 * Reset the host controller and unmask normal interrupts. 216 */ 217 (void) pxamci_host_reset(sc); 218 219 /* Setup bus clock */ 220 if (CPU_IS_PXA270) { 221 sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 222 sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 223 } else { 224 sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 225 sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 226 } 227 sc->sc_clkbase = sc->sc_clkmin; 228 pxamci_bus_clock(sc, sc->sc_clkbase); 229 230 /* Setup max block length */ 231 if (CPU_IS_PXA270) { 232 sc->sc_maxblklen = 2048; 233 } else { 234 sc->sc_maxblklen = 512; 235 } 236 237 /* Set default bus width */ 238 sc->sc_buswidth = 1; 239 240 /* setting DMA */ 241 #if 1 /* XXX */ 242 SET(sc->sc_caps, PMC_CAPS_NO_DMA); /* disable DMA */ 243 #endif 244 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 245 sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 246 sc->sc_rxdr.ds_len = 1; 247 sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 248 if (sc->sc_rxdx == NULL) { 249 aprint_error_dev(sc->sc_dev, 250 "couldn't alloc rx dma xfer\n"); 251 goto free_intr; 252 } 253 sc->sc_rxdx->dx_cookie = sc; 254 sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 255 sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 256 sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 257 sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 258 sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 259 sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 260 sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 261 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 262 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 263 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 264 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 265 266 sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 267 sc->sc_txdr.ds_len = 1; 268 sc->sc_txdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 269 if (sc->sc_txdx == NULL) { 270 aprint_error_dev(sc->sc_dev, 271 "couldn't alloc tx dma xfer\n"); 272 goto free_xfer; 273 } 274 sc->sc_txdx->dx_cookie = sc; 275 sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 276 sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 277 sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 278 sc->sc_txdx->dx_done = pxamci_dmac_ointr; 279 sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 280 sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 281 sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 282 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 283 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 284 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 285 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 286 } 287 288 /* 289 * Attach the generic SD/MMC bus driver. (The bus driver must 290 * not invoke any chipset functions before it is attached.) 291 */ 292 memset(&saa, 0, sizeof(saa)); 293 saa.saa_busname = "sdmmc"; 294 saa.saa_sct = &pxamci_chip_functions; 295 saa.saa_sch = sc; 296 saa.saa_dmat = pxa->pxa_dmat; 297 saa.saa_clkmin = sc->sc_clkmin; 298 saa.saa_clkmax = sc->sc_clkmax; 299 saa.saa_caps = 0; 300 #if notyet 301 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 302 SET(saa.saa_caps, SMC_CAPS_DMA); 303 if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 304 SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 305 #endif 306 307 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 308 if (sc->sc_sdmmc == NULL) { 309 aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 310 goto free_xfer; 311 } 312 return 0; 313 314 free_xfer: 315 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 316 if (sc->sc_rxdx) 317 pxa2x0_dmac_free_xfer(sc->sc_rxdx); 318 if (sc->sc_txdx) 319 pxa2x0_dmac_free_xfer(sc->sc_txdx); 320 } 321 free_intr: 322 pxa2x0_intr_disestablish(sc->sc_ih); 323 sc->sc_ih = NULL; 324 free_map: 325 bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 326 out: 327 pxa2x0_clkman_config(CKEN_MMC, 0); 328 return 1; 329 } 330 331 /* 332 * Notify card attach/detach event. 333 */ 334 void 335 pxamci_card_detect_event(struct pxamci_softc *sc) 336 { 337 338 sdmmc_needs_discover(sc->sc_sdmmc); 339 } 340 341 /* 342 * Reset the host controller. Called during initialization, when 343 * cards are removed, upon resume, and during error recovery. 344 */ 345 static int 346 pxamci_host_reset(sdmmc_chipset_handle_t sch) 347 { 348 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 349 int s; 350 351 s = splsdmmc(); 352 353 CSR_WRITE_4(sc, MMC_SPI, 0); 354 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 355 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 356 357 /* Make sure to initialize the card before the next command. */ 358 CLR(sc->sc_flags, PMF_CARDINITED); 359 360 splx(s); 361 362 return 0; 363 } 364 365 static uint32_t 366 pxamci_host_ocr(sdmmc_chipset_handle_t sch) 367 { 368 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 369 int rv; 370 371 if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 372 rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 373 return rv; 374 } 375 376 DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 377 device_xname(sc->sc_dev))); 378 return ENXIO; 379 } 380 381 static int 382 pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 383 { 384 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 385 386 return sc->sc_maxblklen; 387 } 388 389 static int 390 pxamci_card_detect(sdmmc_chipset_handle_t sch) 391 { 392 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 393 394 if (__predict_true(sc->sc_tag.card_detect != NULL)) { 395 return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 396 } 397 398 DPRINTF(0,("%s: driver lacks card_detect() function.\n", 399 device_xname(sc->sc_dev))); 400 return 1; /* always detect */ 401 } 402 403 static int 404 pxamci_write_protect(sdmmc_chipset_handle_t sch) 405 { 406 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 407 408 if (__predict_true(sc->sc_tag.write_protect != NULL)) { 409 return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 410 } 411 412 DPRINTF(0,("%s: driver lacks write_protect() function.\n", 413 device_xname(sc->sc_dev))); 414 return 0; /* non-protect */ 415 } 416 417 /* 418 * Set or change SD bus voltage and enable or disable SD bus power. 419 * Return zero on success. 420 */ 421 static int 422 pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 423 { 424 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 425 426 /* 427 * Bus power management is beyond control of the SD/SDIO/MMC 428 * block of the PXA2xx processors, so we have to hand this 429 * task off to the attachment driver. 430 */ 431 if (__predict_true(sc->sc_tag.set_power != NULL)) { 432 return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 433 } 434 435 DPRINTF(0,("%s: driver lacks set_power() function\n", 436 device_xname(sc->sc_dev))); 437 return ENXIO; 438 } 439 440 /* 441 * Set or change MMCLK frequency or disable the MMC clock. 442 * Return zero on success. 443 */ 444 static int 445 pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 446 { 447 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 448 int actfreq; 449 int div; 450 int rv = 0; 451 int s; 452 453 s = splsdmmc(); 454 455 /* 456 * Stop MMC clock before changing the frequency. 457 */ 458 pxamci_stop_clock(sc); 459 460 /* Just stop the clock. */ 461 if (freq == 0) 462 goto out; 463 464 /* 465 * PXA27x Errata... 466 * 467 * <snip> 468 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 469 * 470 * SD/SDIO controller can only support up to 9.75 Mbps data 471 * transfer rate for SDIO card. 472 * </snip> 473 * 474 * If we don't limit the frequency, CRC errors will be 475 * reported by the controller after we set the bus speed. 476 * XXX slow down incrementally. 477 */ 478 if (CPU_IS_PXA270) { 479 if (freq > 9750) { 480 freq = 9750; 481 } 482 } 483 484 /* 485 * Pick the smallest divider that produces a frequency not 486 * more than `freq' KHz. 487 */ 488 actfreq = sc->sc_clkmax; 489 for (div = 0; div < 7; actfreq /= 2, div++) { 490 if (actfreq <= freq) 491 break; 492 } 493 if (div == 7) { 494 aprint_error_dev(sc->sc_dev, 495 "unsupported bus frequency of %d KHz\n", freq); 496 rv = 1; 497 goto out; 498 } 499 500 DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 501 device_xname(sc->sc_dev), freq, actfreq, div)); 502 503 sc->sc_clkbase = actfreq; 504 sc->sc_clkrt = div; 505 506 out: 507 splx(s); 508 509 return rv; 510 } 511 512 static int 513 pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 514 { 515 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 516 int rv = 0; 517 int s; 518 519 s = splsdmmc(); 520 521 switch (width) { 522 case 1: 523 break; 524 case 4: 525 if (CPU_IS_PXA270) 526 break; 527 /*FALLTHROUGH*/ 528 default: 529 DPRINTF(0,("%s: unsupported bus width (%d)\n", 530 device_xname(sc->sc_dev), width)); 531 rv = 1; 532 goto out; 533 } 534 535 sc->sc_buswidth = width; 536 537 out: 538 splx(s); 539 540 return rv; 541 } 542 543 static void 544 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 545 { 546 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 547 uint32_t cmdat; 548 int error; 549 int timo; 550 int s; 551 552 DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x " 553 "proc=%p \"%s\"\n", device_xname(sc->sc_dev), 554 cmd->c_opcode, cmd->c_arg, cmd->c_data, cmd->c_datalen, 555 cmd->c_flags, curproc, curproc ? curproc->p_comm : "")); 556 557 s = splsdmmc(); 558 559 /* Stop the bus clock (MMCLK). [15.8.3] */ 560 pxamci_stop_clock(sc); 561 562 /* Set the command and argument. */ 563 CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 564 CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 565 CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 566 567 /* Response type */ 568 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 569 cmdat = CMDAT_RESPONSE_FORMAT_NO; 570 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 571 cmdat = CMDAT_RESPONSE_FORMAT_R2; 572 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 573 cmdat = CMDAT_RESPONSE_FORMAT_R3; 574 else 575 cmdat = CMDAT_RESPONSE_FORMAT_R1; 576 577 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 578 cmdat |= CMDAT_BUSY; 579 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 580 cmdat |= CMDAT_WRITE; 581 if (sc->sc_buswidth == 4) 582 cmdat |= CMDAT_SD_4DAT; 583 584 /* Fragment the data into proper blocks. */ 585 if (cmd->c_datalen > 0) { 586 int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 587 int numblk = cmd->c_datalen / blklen; 588 589 if (cmd->c_datalen % blklen > 0) { 590 /* XXX: Split this command. (1.7.4) */ 591 aprint_error_dev(sc->sc_dev, 592 "data not a multiple of %u bytes\n", blklen); 593 cmd->c_error = EINVAL; 594 goto out; 595 } 596 597 /* Check limit imposed by block count. */ 598 if (numblk > NOB_MASK) { 599 aprint_error_dev(sc->sc_dev, "too much data\n"); 600 cmd->c_error = EINVAL; 601 goto out; 602 } 603 604 CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 605 CSR_WRITE_4(sc, MMC_NOB, numblk); 606 CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 607 608 cmdat |= CMDAT_DATA_EN; 609 610 /* setting DMA */ 611 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 612 struct dmac_xfer_desc *dx_desc; 613 614 cmdat |= CMDAT_MMC_DMA_EN; 615 616 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 617 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 618 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 619 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 620 error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 621 } else { 622 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 623 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 624 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 625 /* workaround for erratum #91 */ 626 error = 0; 627 if (!CPU_IS_PXA270) { 628 error = 629 pxa2x0_dmac_start_xfer(sc->sc_txdx); 630 } 631 } 632 if (error) { 633 aprint_error_dev(sc->sc_dev, 634 "couldn't start dma xfer. (error=%d)\n", 635 error); 636 cmd->c_error = EIO; 637 goto err; 638 } 639 } else { 640 cmd->c_resid = cmd->c_datalen; 641 cmd->c_buf = cmd->c_data; 642 643 pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 644 | MMC_I_TXFIFO_WR_REQ 645 | MMC_I_DAT_ERR); 646 } 647 } 648 649 sc->sc_cmd = cmd; 650 651 /* 652 * "After reset, the MMC card must be initialized by sending 653 * 80 clocks to it on the MMCLK signal." [15.4.3.2] 654 */ 655 if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 656 DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 657 cmdat |= CMDAT_INIT; 658 SET(sc->sc_flags, PMF_CARDINITED); 659 } 660 661 /* Begin the transfer and start the bus clock. */ 662 CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 663 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 664 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 665 666 /* Wait for it to complete */ 667 pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 668 for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 669 tsleep(sc, PWAIT, "mmcmd", hz); 670 } 671 672 /* If it completed in time, SCF_ITSDONE is already set. */ 673 if (sc->sc_cmd == cmd) { 674 cmd->c_error = ETIMEDOUT; 675 err: 676 SET(cmd->c_flags, SCF_ITSDONE); 677 sc->sc_cmd = NULL; 678 goto out; 679 } 680 681 out: 682 splx(s); 683 684 DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 685 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 686 } 687 688 static void 689 pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 690 { 691 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 692 693 if (enable) { 694 pxamci_enable_intr(sc, MMC_I_SDIO_INT); 695 } else { 696 pxamci_disable_intr(sc, MMC_I_SDIO_INT); 697 } 698 } 699 700 static void 701 pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 702 { 703 704 /* Nothing to do */ 705 } 706 707 static void 708 pxamci_stop_clock(struct pxamci_softc *sc) 709 { 710 int timo = STOPCLK_TIMO; 711 712 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 713 CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 714 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 715 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 716 && (timo-- > 0)) { 717 tsleep(sc, PWAIT, "mmclk", hz); 718 } 719 } 720 if (timo == 0) 721 aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 722 } 723 724 /* 725 * SD/MMC controller interrput handler 726 */ 727 static int 728 pxamci_intr(void *arg) 729 { 730 struct pxamci_softc *sc = arg; 731 int status; 732 #ifdef PXAMCI_DEBUG 733 int ostatus; 734 735 ostatus = 736 #endif 737 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 738 DPRINTF(9,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 739 status)); 740 741 /* 742 * Notify the process waiting in pxamci_clock_stop() when 743 * the clock has really stopped. 744 */ 745 if (ISSET(status, MMC_I_CLK_IS_OFF)) { 746 DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 747 wakeup(sc); 748 pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 749 CLR(status, MMC_I_CLK_IS_OFF); 750 } 751 752 if (sc->sc_cmd == NULL) 753 goto end; 754 755 if (ISSET(status, MMC_I_RES_ERR)) { 756 DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 757 device_xname(sc->sc_dev))); 758 pxamci_disable_intr(sc, MMC_I_RES_ERR); 759 CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 760 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 761 && (sc->sc_cmd->c_datalen > 0)) { 762 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 763 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 764 } else { 765 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 766 } 767 } 768 sc->sc_cmd->c_error = ENOEXEC; 769 pxamci_intr_done(sc); 770 goto end; 771 } 772 773 if (ISSET(status, MMC_I_END_CMD_RES)) { 774 DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 775 device_xname(sc->sc_dev))); 776 pxamci_intr_cmd(sc); 777 pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 778 CLR(status, MMC_I_END_CMD_RES); 779 /* ignore programming done condition */ 780 if (ISSET(status, MMC_I_PRG_DONE)) { 781 pxamci_disable_intr(sc, MMC_I_PRG_DONE); 782 CLR(status, MMC_I_PRG_DONE); 783 } 784 if (sc->sc_cmd == NULL) 785 goto end; 786 } 787 788 if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 789 DPRINTF(9,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 790 device_xname(sc->sc_dev))); 791 CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 792 pxamci_intr_data(sc); 793 } 794 795 if (ISSET(status, MMC_I_DAT_ERR)) { 796 DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 797 device_xname(sc->sc_dev))); 798 pxamci_disable_intr(sc, MMC_I_DAT_ERR); 799 CLR(status, MMC_I_DAT_ERR); 800 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 801 && (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ))) { 802 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 803 } else { 804 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 805 } 806 sc->sc_cmd->c_error = EIO; 807 pxamci_intr_done(sc); 808 /* ignore transmission done condition */ 809 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 810 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 811 CLR(status, MMC_I_DATA_TRAN_DONE); 812 } 813 goto end; 814 } 815 816 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 817 DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 818 device_xname(sc->sc_dev))); 819 pxamci_intr_done(sc); 820 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 821 CLR(status, MMC_I_DATA_TRAN_DONE); 822 } 823 824 if (ISSET(status, STAT_SDIO_INT)) { 825 DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 826 device_xname(sc->sc_dev))); 827 sdmmc_card_intr(sc->sc_sdmmc); 828 CLR(status, STAT_SDIO_INT); 829 } 830 831 end: 832 /* Avoid further unhandled interrupts. */ 833 if (status != 0) { 834 pxamci_disable_intr(sc, status); 835 #ifdef PXAMCI_DEBUG 836 aprint_error_dev(sc->sc_dev, 837 "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 838 #endif 839 } 840 return 1; 841 } 842 843 static void 844 pxamci_intr_cmd(struct pxamci_softc *sc) 845 { 846 struct sdmmc_command *cmd = sc->sc_cmd; 847 uint32_t status; 848 int error; 849 int i; 850 851 KASSERT(sc->sc_cmd != NULL); 852 853 #define STAT_ERR (STAT_READ_TIME_OUT \ 854 | STAT_TIMEOUT_RESPONSE \ 855 | STAT_CRC_WRITE_ERROR \ 856 | STAT_CRC_READ_ERROR \ 857 | STAT_SPI_READ_ERROR_TOKEN) 858 859 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 860 for (i = 3; i >= 0; i--) { 861 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 862 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 863 cmd->c_resp[i] = (h << 16) | l; 864 } 865 cmd->c_error = 0; 866 } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 867 /* 868 * Grrr... The processor manual is not clear about 869 * the layout of the response FIFO. It just states 870 * that the FIFO is 16 bits wide, has a depth of 8, 871 * and that the CRC is not copied into the FIFO. 872 * 873 * A 16-bit word in the FIFO is filled from highest 874 * to lowest bit as the response comes in. The two 875 * start bits and the 6 command index bits are thus 876 * stored in the upper 8 bits of the first 16-bit 877 * word that we read back from the FIFO. 878 * 879 * Since the sdmmc(4) framework expects the host 880 * controller to discard the first 8 bits of the 881 * response, what we must do is discard the upper 882 * byte of the first 16-bit word. 883 */ 884 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 885 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 886 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 887 cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 888 for (i = 1; i < 4; i++) 889 cmd->c_resp[i] = 0; 890 cmd->c_error = 0; 891 } 892 893 status = CSR_READ_4(sc, MMC_STAT); 894 895 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 896 CLR(status, STAT_TIMEOUT_RESPONSE); 897 898 /* XXX only for R6, not for R2 */ 899 if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 900 CLR(status, STAT_RES_CRC_ERR); 901 902 if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 903 cmd->c_error = ETIMEDOUT; 904 else if (ISSET(status, STAT_RES_CRC_ERR) 905 && ISSET(cmd->c_flags, SCF_RSP_CRC) 906 && CPU_IS_PXA270) { 907 /* workaround for erratum #42 */ 908 if (ISSET(cmd->c_flags, SCF_RSP_136) 909 && (cmd->c_resp[0] & 0x80000000U)) { 910 DPRINTF(1,("%s: ignore CRC error\n", 911 device_xname(sc->sc_dev))); 912 } else 913 cmd->c_error = EIO; 914 } else if (ISSET(status, STAT_ERR)) 915 cmd->c_error = EIO; 916 917 pxamci_disable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 918 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 919 /* workaround for erratum #91 */ 920 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 921 && CPU_IS_PXA270 922 && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 923 error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 924 if (error) { 925 aprint_error_dev(sc->sc_dev, 926 "couldn't start dma xfer. (error=%d)\n", 927 error); 928 cmd->c_error = EIO; 929 pxamci_intr_done(sc); 930 return; 931 } 932 } 933 pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 934 } else { 935 pxamci_intr_done(sc); 936 } 937 } 938 939 static void 940 pxamci_intr_data(struct pxamci_softc *sc) 941 { 942 struct sdmmc_command *cmd = sc->sc_cmd; 943 int intr; 944 int n; 945 946 DPRINTF(1,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 947 device_xname(sc->sc_dev), cmd, cmd->c_resid)); 948 949 n = MIN(32, cmd->c_resid); 950 cmd->c_resid -= n; 951 952 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 953 intr = MMC_I_RXFIFO_RD_REQ; 954 while (n-- > 0) 955 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 956 } else { 957 int short_xfer = n < 32; 958 959 intr = MMC_I_TXFIFO_WR_REQ; 960 while (n-- > 0) 961 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 962 if (short_xfer) 963 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 964 } 965 966 if (cmd->c_resid > 0) { 967 pxamci_enable_intr(sc, intr); 968 } else { 969 pxamci_disable_intr(sc, intr); 970 } 971 } 972 973 /* 974 * Wake up the process sleeping in pxamci_exec_command(). 975 */ 976 static void 977 pxamci_intr_done(struct pxamci_softc *sc) 978 { 979 #ifdef PXAMCI_DEBUG 980 uint32_t status; 981 982 status = CSR_READ_4(sc, MMC_STAT); 983 DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 984 device_xname(sc->sc_dev), status)); 985 #endif 986 987 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 988 SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 989 sc->sc_cmd = NULL; 990 wakeup(sc); 991 } 992 993 static void 994 pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 995 { 996 struct pxamci_softc *sc = dx->dx_cookie; 997 998 if (status) { 999 aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1000 "non-zero completion status %d\n", status); 1001 } 1002 } 1003 1004 static void 1005 pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1006 { 1007 struct pxamci_softc *sc = dx->dx_cookie; 1008 1009 if (status) { 1010 aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1011 "non-zero completion status %d\n", status); 1012 } 1013 } 1014
Indexes created Fri Sep 26 20:09:58 GMT 2025