pxa2x0_mci.c revision 1.1.4.5
1 /* $NetBSD: pxa2x0_mci.c,v 1.1.4.5 2010/08/11 22:51:42 yamt Exp $ */ 2 /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (c) 2007-2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 /* 47 * MMC/SD/SDIO controller driver for Intel PXA2xx processors 48 * 49 * Power management is beyond control of the processor's SD/SDIO/MMC 50 * block, so this driver depends on the attachment driver to provide 51 * us with some callback functions via the "tag" member in our softc. 52 * Bus power management calls are then dispatched to the attachment 53 * driver. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.1.4.5 2010/08/11 22:51:42 yamt Exp $"); 58 59 #include <sys/param.h> 60 #include <sys/device.h> 61 #include <sys/systm.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/proc.h> 65 #include <sys/bus.h> 66 #include <sys/mutex.h> 67 #include <sys/condvar.h> 68 69 #include <machine/intr.h> 70 71 #include <dev/sdmmc/sdmmcvar.h> 72 #include <dev/sdmmc/sdmmcchip.h> 73 74 #include <arm/xscale/pxa2x0cpu.h> 75 #include <arm/xscale/pxa2x0reg.h> 76 #include <arm/xscale/pxa2x0var.h> 77 #include <arm/xscale/pxa2x0_dmac.h> 78 #include <arm/xscale/pxa2x0_gpio.h> 79 #include <arm/xscale/pxa2x0_mci.h> 80 81 #ifdef PXAMCI_DEBUG 82 int pxamci_debug = 9; 83 #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 84 #else 85 #define DPRINTF(n,s) do {} while (0) 86 #endif 87 88 #ifndef PXAMCI_DEBUG 89 #define STOPCLK_TIMO 2 /* sec */ 90 #define EXECCMD_TIMO 2 /* sec */ 91 #else 92 #define STOPCLK_TIMO 2 /* sec */ 93 #define EXECCMD_TIMO 5 /* sec */ 94 #endif 95 96 static int pxamci_host_reset(sdmmc_chipset_handle_t); 97 static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 98 static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 99 static int pxamci_card_detect(sdmmc_chipset_handle_t); 100 static int pxamci_write_protect(sdmmc_chipset_handle_t); 101 static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 102 static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 103 static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 104 static void pxamci_exec_command(sdmmc_chipset_handle_t, 105 struct sdmmc_command *); 106 static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 107 static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 108 109 static struct sdmmc_chip_functions pxamci_chip_functions = { 110 /* host controller reset */ 111 .host_reset = pxamci_host_reset, 112 113 /* host controller capabilities */ 114 .host_ocr = pxamci_host_ocr, 115 .host_maxblklen = pxamci_host_maxblklen, 116 117 /* card detection */ 118 .card_detect = pxamci_card_detect, 119 120 /* write protect */ 121 .write_protect = pxamci_write_protect, 122 123 /* bus power, clock frequency, width */ 124 .bus_power = pxamci_bus_power, 125 .bus_clock = pxamci_bus_clock, 126 .bus_width = pxamci_bus_width, 127 128 /* command execution */ 129 .exec_command = pxamci_exec_command, 130 131 /* card interrupt */ 132 .card_enable_intr = pxamci_card_enable_intr, 133 .card_intr_ack = pxamci_card_intr_ack, 134 }; 135 136 static int pxamci_intr(void *); 137 static void pxamci_intr_cmd(struct pxamci_softc *); 138 static void pxamci_intr_data(struct pxamci_softc *); 139 static void pxamci_intr_done(struct pxamci_softc *); 140 static void pxamci_dmac_iintr(struct dmac_xfer *, int); 141 static void pxamci_dmac_ointr(struct dmac_xfer *, int); 142 143 static void pxamci_stop_clock(struct pxamci_softc *); 144 145 #define CSR_READ_1(sc, reg) \ 146 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 147 #define CSR_WRITE_1(sc, reg, val) \ 148 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 149 #define CSR_READ_4(sc, reg) \ 150 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 151 #define CSR_WRITE_4(sc, reg, val) \ 152 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 153 #define CSR_SET_4(sc, reg, val) \ 154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 155 #define CSR_CLR_4(sc, reg, val) \ 156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 157 158 #if 0 /* XXX */ 159 #define DMA_ALIGNED(addr) \ 160 (((u_long)(addr) & 0x7) == 0 || !CPU_IS_PXA250) 161 #else 162 #define DMA_ALIGNED(addr) \ 163 (((u_long)(addr) & 0x1f) == 0) 164 #endif 165 166 static void 167 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 168 { 169 int s; 170 171 s = splsdmmc(); 172 sc->sc_imask &= ~mask; 173 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 174 splx(s); 175 } 176 177 static void 178 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 179 { 180 int s; 181 182 s = splsdmmc(); 183 sc->sc_imask |= mask; 184 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 185 splx(s); 186 } 187 188 int 189 pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 190 { 191 struct pxamci_softc *sc = device_private(self); 192 struct sdmmcbus_attach_args saa; 193 194 sc->sc_dev = self; 195 196 aprint_normal(": MMC/SD Controller\n"); 197 aprint_naive("\n"); 198 199 /* Enable the clocks to the MMC controller. */ 200 pxa2x0_clkman_config(CKEN_MMC, 1); 201 202 sc->sc_iot = pxa->pxa_iot; 203 if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 204 &sc->sc_ioh)) { 205 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 206 goto out; 207 } 208 209 /* 210 * Establish the card detection and MMC interrupt handlers and 211 * mask all interrupts until we are prepared to handle them. 212 */ 213 pxamci_disable_intr(sc, MMC_I_ALL); 214 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 215 pxamci_intr, sc); 216 if (sc->sc_ih == NULL) { 217 aprint_error_dev(sc->sc_dev, 218 "couldn't establish MMC interrupt\n"); 219 goto free_map; 220 } 221 222 /* 223 * Reset the host controller and unmask normal interrupts. 224 */ 225 (void) pxamci_host_reset(sc); 226 227 /* Setup bus clock */ 228 if (CPU_IS_PXA270) { 229 sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 230 sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 231 } else { 232 sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 233 sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 234 } 235 sc->sc_clkbase = sc->sc_clkmin; 236 pxamci_bus_clock(sc, sc->sc_clkbase); 237 238 /* Setup max block length */ 239 if (CPU_IS_PXA270) { 240 sc->sc_maxblklen = 2048; 241 } else { 242 sc->sc_maxblklen = 512; 243 } 244 245 /* Set default bus width */ 246 sc->sc_buswidth = 1; 247 248 /* setting DMA */ 249 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 250 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 251 252 sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 253 sc->sc_rxdr.ds_len = 1; 254 sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 255 if (sc->sc_rxdx == NULL) { 256 aprint_error_dev(sc->sc_dev, 257 "couldn't alloc rx dma xfer\n"); 258 goto free_intr; 259 } 260 sc->sc_rxdx->dx_cookie = sc; 261 sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 262 sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 263 sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 264 sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 265 sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 266 sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 267 sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 268 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 269 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 270 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 271 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 272 273 sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 274 sc->sc_txdr.ds_len = 1; 275 sc->sc_txdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 276 if (sc->sc_txdx == NULL) { 277 aprint_error_dev(sc->sc_dev, 278 "couldn't alloc tx dma xfer\n"); 279 goto free_xfer; 280 } 281 sc->sc_txdx->dx_cookie = sc; 282 sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 283 sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 284 sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 285 sc->sc_txdx->dx_done = pxamci_dmac_ointr; 286 sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 287 sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 288 sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 289 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 290 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 291 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 292 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 293 } 294 295 /* 296 * Attach the generic SD/MMC bus driver. (The bus driver must 297 * not invoke any chipset functions before it is attached.) 298 */ 299 memset(&saa, 0, sizeof(saa)); 300 saa.saa_busname = "sdmmc"; 301 saa.saa_sct = &pxamci_chip_functions; 302 saa.saa_sch = sc; 303 saa.saa_dmat = pxa->pxa_dmat; 304 saa.saa_clkmin = sc->sc_clkmin; 305 saa.saa_clkmax = sc->sc_clkmax; 306 saa.saa_caps = 0; 307 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 308 SET(saa.saa_caps, SMC_CAPS_DMA); 309 if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 310 SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 311 312 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 313 if (sc->sc_sdmmc == NULL) { 314 aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 315 goto free_xfer; 316 } 317 return 0; 318 319 free_xfer: 320 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 321 if (sc->sc_rxdx) 322 pxa2x0_dmac_free_xfer(sc->sc_rxdx); 323 if (sc->sc_txdx) 324 pxa2x0_dmac_free_xfer(sc->sc_txdx); 325 } 326 free_intr: 327 pxa2x0_intr_disestablish(sc->sc_ih); 328 sc->sc_ih = NULL; 329 free_map: 330 bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 331 out: 332 pxa2x0_clkman_config(CKEN_MMC, 0); 333 return 1; 334 } 335 336 /* 337 * Notify card attach/detach event. 338 */ 339 void 340 pxamci_card_detect_event(struct pxamci_softc *sc) 341 { 342 343 sdmmc_needs_discover(sc->sc_sdmmc); 344 } 345 346 /* 347 * Reset the host controller. Called during initialization, when 348 * cards are removed, upon resume, and during error recovery. 349 */ 350 static int 351 pxamci_host_reset(sdmmc_chipset_handle_t sch) 352 { 353 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 354 int s; 355 356 s = splsdmmc(); 357 358 CSR_WRITE_4(sc, MMC_SPI, 0); 359 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 360 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 361 362 /* Make sure to initialize the card before the next command. */ 363 CLR(sc->sc_flags, PMF_CARDINITED); 364 365 splx(s); 366 367 return 0; 368 } 369 370 static uint32_t 371 pxamci_host_ocr(sdmmc_chipset_handle_t sch) 372 { 373 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 374 int rv; 375 376 if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 377 rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 378 return rv; 379 } 380 381 DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 382 device_xname(sc->sc_dev))); 383 return ENXIO; 384 } 385 386 static int 387 pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 388 { 389 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 390 391 return sc->sc_maxblklen; 392 } 393 394 static int 395 pxamci_card_detect(sdmmc_chipset_handle_t sch) 396 { 397 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 398 399 if (__predict_true(sc->sc_tag.card_detect != NULL)) { 400 return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 401 } 402 403 DPRINTF(0,("%s: driver lacks card_detect() function.\n", 404 device_xname(sc->sc_dev))); 405 return 1; /* always detect */ 406 } 407 408 static int 409 pxamci_write_protect(sdmmc_chipset_handle_t sch) 410 { 411 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 412 413 if (__predict_true(sc->sc_tag.write_protect != NULL)) { 414 return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 415 } 416 417 DPRINTF(0,("%s: driver lacks write_protect() function.\n", 418 device_xname(sc->sc_dev))); 419 return 0; /* non-protect */ 420 } 421 422 /* 423 * Set or change SD bus voltage and enable or disable SD bus power. 424 * Return zero on success. 425 */ 426 static int 427 pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 428 { 429 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 430 431 /* 432 * Bus power management is beyond control of the SD/SDIO/MMC 433 * block of the PXA2xx processors, so we have to hand this 434 * task off to the attachment driver. 435 */ 436 if (__predict_true(sc->sc_tag.set_power != NULL)) { 437 return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 438 } 439 440 DPRINTF(0,("%s: driver lacks set_power() function\n", 441 device_xname(sc->sc_dev))); 442 return ENXIO; 443 } 444 445 /* 446 * Set or change MMCLK frequency or disable the MMC clock. 447 * Return zero on success. 448 */ 449 static int 450 pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 451 { 452 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 453 int actfreq; 454 int div; 455 int rv = 0; 456 int s; 457 458 s = splsdmmc(); 459 460 /* 461 * Stop MMC clock before changing the frequency. 462 */ 463 pxamci_stop_clock(sc); 464 465 /* Just stop the clock. */ 466 if (freq == 0) 467 goto out; 468 469 /* 470 * PXA27x Errata... 471 * 472 * <snip> 473 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 474 * 475 * SD/SDIO controller can only support up to 9.75 Mbps data 476 * transfer rate for SDIO card. 477 * </snip> 478 * 479 * If we don't limit the frequency, CRC errors will be 480 * reported by the controller after we set the bus speed. 481 * XXX slow down incrementally. 482 */ 483 if (CPU_IS_PXA270) { 484 if (freq > 9750) { 485 freq = 9750; 486 } 487 } 488 489 /* 490 * Pick the smallest divider that produces a frequency not 491 * more than `freq' KHz. 492 */ 493 actfreq = sc->sc_clkmax; 494 for (div = 0; div < 7; actfreq /= 2, div++) { 495 if (actfreq <= freq) 496 break; 497 } 498 if (div == 7) { 499 aprint_error_dev(sc->sc_dev, 500 "unsupported bus frequency of %d KHz\n", freq); 501 rv = 1; 502 goto out; 503 } 504 505 DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 506 device_xname(sc->sc_dev), freq, actfreq, div)); 507 508 sc->sc_clkbase = actfreq; 509 sc->sc_clkrt = div; 510 511 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 512 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 513 514 out: 515 splx(s); 516 517 return rv; 518 } 519 520 static int 521 pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 522 { 523 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 524 int rv = 0; 525 int s; 526 527 s = splsdmmc(); 528 529 switch (width) { 530 case 1: 531 break; 532 case 4: 533 if (CPU_IS_PXA270) 534 break; 535 /*FALLTHROUGH*/ 536 default: 537 DPRINTF(0,("%s: unsupported bus width (%d)\n", 538 device_xname(sc->sc_dev), width)); 539 rv = 1; 540 goto out; 541 } 542 543 sc->sc_buswidth = width; 544 545 out: 546 splx(s); 547 548 return rv; 549 } 550 551 static void 552 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 553 { 554 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 555 uint32_t cmdat; 556 int error; 557 int timo; 558 int s; 559 560 DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x\n", 561 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_arg, cmd->c_data, 562 cmd->c_datalen, cmd->c_flags)); 563 564 s = splsdmmc(); 565 566 /* Stop the bus clock (MMCLK). [15.8.3] */ 567 pxamci_stop_clock(sc); 568 569 /* Set the command and argument. */ 570 CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 571 CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 572 CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 573 574 /* Response type */ 575 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 576 cmdat = CMDAT_RESPONSE_FORMAT_NO; 577 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 578 cmdat = CMDAT_RESPONSE_FORMAT_R2; 579 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 580 cmdat = CMDAT_RESPONSE_FORMAT_R3; 581 else 582 cmdat = CMDAT_RESPONSE_FORMAT_R1; 583 584 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 585 cmdat |= CMDAT_BUSY; 586 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 587 cmdat |= CMDAT_WRITE; 588 if (sc->sc_buswidth == 4) 589 cmdat |= CMDAT_SD_4DAT; 590 591 /* Fragment the data into proper blocks. */ 592 if (cmd->c_datalen > 0) { 593 int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 594 int numblk = cmd->c_datalen / blklen; 595 596 if (cmd->c_datalen % blklen > 0) { 597 /* XXX: Split this command. (1.7.4) */ 598 aprint_error_dev(sc->sc_dev, 599 "data not a multiple of %u bytes\n", blklen); 600 cmd->c_error = EINVAL; 601 goto out; 602 } 603 604 /* Check limit imposed by block count. */ 605 if (numblk > NOB_MASK) { 606 aprint_error_dev(sc->sc_dev, "too much data\n"); 607 cmd->c_error = EINVAL; 608 goto out; 609 } 610 611 CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 612 CSR_WRITE_4(sc, MMC_NOB, numblk); 613 CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 614 615 cmdat |= CMDAT_DATA_EN; 616 617 /* setting DMA */ 618 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 619 && DMA_ALIGNED(cmd->c_data)) { 620 struct dmac_xfer_desc *dx_desc; 621 622 DPRINTF(1,("%s: using DMA\n",device_xname(sc->sc_dev))); 623 624 cmdat |= CMDAT_MMC_DMA_EN; 625 626 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 627 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 628 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 629 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 630 error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 631 } else { 632 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 633 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 634 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 635 /* workaround for erratum #91 */ 636 error = 0; 637 if (!CPU_IS_PXA270) { 638 error = 639 pxa2x0_dmac_start_xfer(sc->sc_txdx); 640 } 641 } 642 if (error) { 643 aprint_error_dev(sc->sc_dev, 644 "couldn't start dma xfer. (error=%d)\n", 645 error); 646 cmd->c_error = EIO; 647 goto err; 648 } 649 } else { 650 DPRINTF(1,("%s: using PIO\n",device_xname(sc->sc_dev))); 651 652 cmd->c_resid = cmd->c_datalen; 653 cmd->c_buf = cmd->c_data; 654 655 pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 656 | MMC_I_TXFIFO_WR_REQ 657 | MMC_I_DAT_ERR); 658 } 659 } 660 661 sc->sc_cmd = cmd; 662 663 /* 664 * "After reset, the MMC card must be initialized by sending 665 * 80 clocks to it on the MMCLK signal." [15.4.3.2] 666 */ 667 if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 668 DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 669 cmdat |= CMDAT_INIT; 670 SET(sc->sc_flags, PMF_CARDINITED); 671 } 672 673 /* Begin the transfer and start the bus clock. */ 674 CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 675 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 676 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 677 678 /* Wait for it to complete */ 679 pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 680 for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 681 tsleep(sc, PWAIT, "mmcmd", hz); 682 } 683 684 /* If it completed in time, SCF_ITSDONE is already set. */ 685 if (sc->sc_cmd == cmd) { 686 cmd->c_error = ETIMEDOUT; 687 err: 688 SET(cmd->c_flags, SCF_ITSDONE); 689 sc->sc_cmd = NULL; 690 goto out; 691 } 692 693 out: 694 splx(s); 695 696 DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 697 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 698 } 699 700 static void 701 pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 702 { 703 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 704 705 if (enable) { 706 pxamci_enable_intr(sc, MMC_I_SDIO_INT); 707 } else { 708 pxamci_disable_intr(sc, MMC_I_SDIO_INT); 709 } 710 } 711 712 static void 713 pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 714 { 715 716 /* Nothing to do */ 717 } 718 719 static void 720 pxamci_stop_clock(struct pxamci_softc *sc) 721 { 722 int timo = STOPCLK_TIMO; 723 724 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 725 CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 726 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 727 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 728 && (timo-- > 0)) { 729 tsleep(sc, PWAIT, "mmclk", hz); 730 } 731 } 732 if (timo == 0) 733 aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 734 } 735 736 /* 737 * SD/MMC controller interrput handler 738 */ 739 static int 740 pxamci_intr(void *arg) 741 { 742 struct pxamci_softc *sc = arg; 743 int status; 744 #ifdef PXAMCI_DEBUG 745 int ostatus; 746 747 ostatus = 748 #endif 749 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 750 DPRINTF(10,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 751 status)); 752 753 /* 754 * Notify the process waiting in pxamci_clock_stop() when 755 * the clock has really stopped. 756 */ 757 if (ISSET(status, MMC_I_CLK_IS_OFF)) { 758 DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 759 wakeup(sc); 760 pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 761 CLR(status, MMC_I_CLK_IS_OFF); 762 } 763 764 if (sc->sc_cmd == NULL) 765 goto end; 766 767 if (ISSET(status, MMC_I_RES_ERR)) { 768 DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 769 device_xname(sc->sc_dev))); 770 pxamci_disable_intr(sc, MMC_I_RES_ERR); 771 CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 772 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 773 && (sc->sc_cmd->c_datalen > 0) 774 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 775 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 776 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 777 } else { 778 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 779 } 780 } 781 sc->sc_cmd->c_error = ENOEXEC; 782 pxamci_intr_done(sc); 783 goto end; 784 } 785 786 if (ISSET(status, MMC_I_END_CMD_RES)) { 787 DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 788 device_xname(sc->sc_dev))); 789 pxamci_intr_cmd(sc); 790 pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 791 CLR(status, MMC_I_END_CMD_RES); 792 /* ignore programming done condition */ 793 if (ISSET(status, MMC_I_PRG_DONE)) { 794 pxamci_disable_intr(sc, MMC_I_PRG_DONE); 795 CLR(status, MMC_I_PRG_DONE); 796 } 797 if (sc->sc_cmd == NULL) 798 goto end; 799 } 800 801 if (ISSET(status, MMC_I_DAT_ERR)) { 802 DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 803 device_xname(sc->sc_dev))); 804 sc->sc_cmd->c_error = EIO; 805 pxamci_intr_done(sc); 806 pxamci_disable_intr(sc, MMC_I_DAT_ERR); 807 CLR(status, MMC_I_DAT_ERR); 808 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 809 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 810 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 811 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 812 } else { 813 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 814 } 815 } 816 /* ignore transmission done condition */ 817 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 818 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 819 CLR(status, MMC_I_DATA_TRAN_DONE); 820 } 821 goto end; 822 } 823 824 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 825 DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 826 device_xname(sc->sc_dev))); 827 pxamci_intr_done(sc); 828 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 829 CLR(status, MMC_I_DATA_TRAN_DONE); 830 } 831 832 if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 833 DPRINTF(10,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 834 device_xname(sc->sc_dev))); 835 pxamci_intr_data(sc); 836 CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 837 } 838 839 if (ISSET(status, STAT_SDIO_INT)) { 840 DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 841 device_xname(sc->sc_dev))); 842 sdmmc_card_intr(sc->sc_sdmmc); 843 CLR(status, STAT_SDIO_INT); 844 } 845 846 end: 847 /* Avoid further unhandled interrupts. */ 848 if (status != 0) { 849 pxamci_disable_intr(sc, status); 850 #ifdef PXAMCI_DEBUG 851 aprint_error_dev(sc->sc_dev, 852 "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 853 #endif 854 } 855 return 1; 856 } 857 858 static void 859 pxamci_intr_cmd(struct pxamci_softc *sc) 860 { 861 struct sdmmc_command *cmd = sc->sc_cmd; 862 uint32_t status; 863 int error; 864 int i; 865 866 KASSERT(sc->sc_cmd != NULL); 867 868 #define STAT_ERR (STAT_READ_TIME_OUT \ 869 | STAT_TIMEOUT_RESPONSE \ 870 | STAT_CRC_WRITE_ERROR \ 871 | STAT_CRC_READ_ERROR \ 872 | STAT_SPI_READ_ERROR_TOKEN) 873 874 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 875 for (i = 3; i >= 0; i--) { 876 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 877 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 878 cmd->c_resp[i] = (h << 16) | l; 879 } 880 cmd->c_error = 0; 881 } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 882 /* 883 * Grrr... The processor manual is not clear about 884 * the layout of the response FIFO. It just states 885 * that the FIFO is 16 bits wide, has a depth of 8, 886 * and that the CRC is not copied into the FIFO. 887 * 888 * A 16-bit word in the FIFO is filled from highest 889 * to lowest bit as the response comes in. The two 890 * start bits and the 6 command index bits are thus 891 * stored in the upper 8 bits of the first 16-bit 892 * word that we read back from the FIFO. 893 * 894 * Since the sdmmc(4) framework expects the host 895 * controller to discard the first 8 bits of the 896 * response, what we must do is discard the upper 897 * byte of the first 16-bit word. 898 */ 899 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 900 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 901 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 902 cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 903 for (i = 1; i < 4; i++) 904 cmd->c_resp[i] = 0; 905 cmd->c_error = 0; 906 } 907 908 status = CSR_READ_4(sc, MMC_STAT); 909 910 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 911 CLR(status, STAT_TIMEOUT_RESPONSE); 912 913 /* XXX only for R6, not for R2 */ 914 if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 915 CLR(status, STAT_RES_CRC_ERR); 916 917 if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 918 cmd->c_error = ETIMEDOUT; 919 else if (ISSET(status, STAT_RES_CRC_ERR) 920 && ISSET(cmd->c_flags, SCF_RSP_CRC) 921 && CPU_IS_PXA270) { 922 /* workaround for erratum #42 */ 923 if (ISSET(cmd->c_flags, SCF_RSP_136) 924 && (cmd->c_resp[0] & 0x80000000U)) { 925 DPRINTF(1,("%s: ignore CRC error\n", 926 device_xname(sc->sc_dev))); 927 } else 928 cmd->c_error = EIO; 929 } else if (ISSET(status, STAT_ERR)) 930 cmd->c_error = EIO; 931 932 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 933 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 934 && DMA_ALIGNED(cmd->c_data)) { 935 /* workaround for erratum #91 */ 936 if (CPU_IS_PXA270 937 && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 938 error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 939 if (error) { 940 aprint_error_dev(sc->sc_dev, 941 "couldn't start dma xfer." 942 " (error=%d)\n", error); 943 cmd->c_error = EIO; 944 pxamci_intr_done(sc); 945 return; 946 } 947 } 948 pxamci_enable_intr(sc, 949 MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 950 } 951 } else { 952 pxamci_intr_done(sc); 953 } 954 } 955 956 static void 957 pxamci_intr_data(struct pxamci_softc *sc) 958 { 959 struct sdmmc_command *cmd = sc->sc_cmd; 960 int intr; 961 int n; 962 963 DPRINTF(10,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 964 device_xname(sc->sc_dev), cmd, cmd->c_resid)); 965 966 n = MIN(32, cmd->c_resid); 967 cmd->c_resid -= n; 968 969 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 970 intr = MMC_I_RXFIFO_RD_REQ; 971 while (n-- > 0) 972 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 973 } else { 974 int short_xfer = n < 32; 975 976 intr = MMC_I_TXFIFO_WR_REQ; 977 while (n-- > 0) 978 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 979 if (short_xfer) 980 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 981 } 982 983 if (cmd->c_resid > 0) { 984 pxamci_enable_intr(sc, intr); 985 } else { 986 pxamci_disable_intr(sc, intr); 987 pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE); 988 } 989 } 990 991 /* 992 * Wake up the process sleeping in pxamci_exec_command(). 993 */ 994 static void 995 pxamci_intr_done(struct pxamci_softc *sc) 996 { 997 998 DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 999 device_xname(sc->sc_dev), CSR_READ_4(sc, MMC_STAT))); 1000 1001 pxamci_disable_intr(sc, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ| 1002 MMC_I_DATA_TRAN_DONE|MMC_I_END_CMD_RES|MMC_I_RES_ERR|MMC_I_DAT_ERR); 1003 SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 1004 sc->sc_cmd = NULL; 1005 wakeup(sc); 1006 } 1007 1008 static void 1009 pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 1010 { 1011 struct pxamci_softc *sc = dx->dx_cookie; 1012 1013 DPRINTF(1,("%s: pxamci_dmac_iintr: status = %#x\n", 1014 device_xname(sc->sc_dev), status)); 1015 1016 if (status) { 1017 aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1018 "non-zero completion status %d\n", status); 1019 } 1020 } 1021 1022 static void 1023 pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1024 { 1025 struct pxamci_softc *sc = dx->dx_cookie; 1026 1027 DPRINTF(1,("%s: pxamci_dmac_ointr: status = %#x\n", 1028 device_xname(sc->sc_dev), status)); 1029 1030 if (status == 0) { 1031 if (sc->sc_cmd != NULL && (sc->sc_cmd->c_datalen & 31) != 0) { 1032 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 1033 } 1034 } else { 1035 aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1036 "non-zero completion status %d\n", status); 1037 } 1038 } 1039
Indexes created Sat Oct 18 21:09:54 GMT 2025