pxa2x0_mci.c revision 1.10
1 /* $NetBSD: pxa2x0_mci.c,v 1.10 2012/01/21 19:44:28 nonaka Exp $ */ 2 /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007-2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* 46 * MMC/SD/SDIO controller driver for Intel PXA2xx processors 47 * 48 * Power management is beyond control of the processor's SD/SDIO/MMC 49 * block, so this driver depends on the attachment driver to provide 50 * us with some callback functions via the "tag" member in our softc. 51 * Bus power management calls are then dispatched to the attachment 52 * driver. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.10 2012/01/21 19:44:28 nonaka Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/device.h> 60 #include <sys/systm.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/proc.h> 64 #include <sys/bus.h> 65 #include <sys/mutex.h> 66 #include <sys/condvar.h> 67 68 #include <machine/intr.h> 69 70 #include <dev/sdmmc/sdmmcvar.h> 71 #include <dev/sdmmc/sdmmcchip.h> 72 73 #include <arm/xscale/pxa2x0cpu.h> 74 #include <arm/xscale/pxa2x0reg.h> 75 #include <arm/xscale/pxa2x0var.h> 76 #include <arm/xscale/pxa2x0_dmac.h> 77 #include <arm/xscale/pxa2x0_gpio.h> 78 #include <arm/xscale/pxa2x0_mci.h> 79 80 #ifdef PXAMCI_DEBUG 81 int pxamci_debug = 9; 82 #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 83 #else 84 #define DPRINTF(n,s) do {} while (0) 85 #endif 86 87 #ifndef PXAMCI_DEBUG 88 #define STOPCLK_TIMO 2 /* sec */ 89 #define EXECCMD_TIMO 2 /* sec */ 90 #else 91 #define STOPCLK_TIMO 2 /* sec */ 92 #define EXECCMD_TIMO 5 /* sec */ 93 #endif 94 95 static int pxamci_host_reset(sdmmc_chipset_handle_t); 96 static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 97 static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 98 static int pxamci_card_detect(sdmmc_chipset_handle_t); 99 static int pxamci_write_protect(sdmmc_chipset_handle_t); 100 static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 101 static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 102 static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 103 static int pxamci_bus_rod(sdmmc_chipset_handle_t, int); 104 static void pxamci_exec_command(sdmmc_chipset_handle_t, 105 struct sdmmc_command *); 106 static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 107 static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 108 109 static struct sdmmc_chip_functions pxamci_chip_functions = { 110 /* host controller reset */ 111 .host_reset = pxamci_host_reset, 112 113 /* host controller capabilities */ 114 .host_ocr = pxamci_host_ocr, 115 .host_maxblklen = pxamci_host_maxblklen, 116 117 /* card detection */ 118 .card_detect = pxamci_card_detect, 119 120 /* write protect */ 121 .write_protect = pxamci_write_protect, 122 123 /* bus power, clock frequency, width */ 124 .bus_power = pxamci_bus_power, 125 .bus_clock = pxamci_bus_clock, 126 .bus_width = pxamci_bus_width, 127 .bus_rod = pxamci_bus_rod, 128 129 /* command execution */ 130 .exec_command = pxamci_exec_command, 131 132 /* card interrupt */ 133 .card_enable_intr = pxamci_card_enable_intr, 134 .card_intr_ack = pxamci_card_intr_ack, 135 }; 136 137 static int pxamci_intr(void *); 138 static void pxamci_intr_cmd(struct pxamci_softc *); 139 static void pxamci_intr_data(struct pxamci_softc *); 140 static void pxamci_intr_done(struct pxamci_softc *); 141 static void pxamci_dmac_iintr(struct dmac_xfer *, int); 142 static void pxamci_dmac_ointr(struct dmac_xfer *, int); 143 144 static void pxamci_stop_clock(struct pxamci_softc *); 145 146 #define CSR_READ_1(sc, reg) \ 147 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 148 #define CSR_WRITE_1(sc, reg, val) \ 149 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 150 #define CSR_READ_4(sc, reg) \ 151 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 152 #define CSR_WRITE_4(sc, reg, val) \ 153 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 154 #define CSR_SET_4(sc, reg, val) \ 155 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 156 #define CSR_CLR_4(sc, reg, val) \ 157 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 158 159 #if 0 /* XXX */ 160 #define DMA_ALIGNED(addr) \ 161 (((u_long)(addr) & 0x7) == 0 || !CPU_IS_PXA250) 162 #else 163 #define DMA_ALIGNED(addr) \ 164 (((u_long)(addr) & 0x1f) == 0) 165 #endif 166 167 static void 168 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 169 { 170 int s; 171 172 s = splsdmmc(); 173 sc->sc_imask &= ~mask; 174 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 175 splx(s); 176 } 177 178 static void 179 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 180 { 181 int s; 182 183 s = splsdmmc(); 184 sc->sc_imask |= mask; 185 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 186 splx(s); 187 } 188 189 int 190 pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 191 { 192 struct pxamci_softc *sc = device_private(self); 193 struct sdmmcbus_attach_args saa; 194 195 sc->sc_dev = self; 196 197 aprint_normal(": MMC/SD Controller\n"); 198 aprint_naive("\n"); 199 200 /* Enable the clocks to the MMC controller. */ 201 pxa2x0_clkman_config(CKEN_MMC, 1); 202 203 sc->sc_iot = pxa->pxa_iot; 204 if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 205 &sc->sc_ioh)) { 206 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 207 goto out; 208 } 209 210 /* 211 * Establish the card detection and MMC interrupt handlers and 212 * mask all interrupts until we are prepared to handle them. 213 */ 214 pxamci_disable_intr(sc, MMC_I_ALL); 215 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 216 pxamci_intr, sc); 217 if (sc->sc_ih == NULL) { 218 aprint_error_dev(sc->sc_dev, 219 "couldn't establish MMC interrupt\n"); 220 goto free_map; 221 } 222 223 /* 224 * Reset the host controller and unmask normal interrupts. 225 */ 226 (void) pxamci_host_reset(sc); 227 228 /* Setup bus clock */ 229 if (CPU_IS_PXA270) { 230 sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 231 sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 232 } else { 233 sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 234 sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 235 } 236 sc->sc_clkbase = sc->sc_clkmin; 237 pxamci_bus_clock(sc, sc->sc_clkbase); 238 239 /* Setup max block length */ 240 if (CPU_IS_PXA270) { 241 sc->sc_maxblklen = 2048; 242 } else { 243 sc->sc_maxblklen = 512; 244 } 245 246 /* Set default bus width */ 247 sc->sc_buswidth = 1; 248 249 /* setting DMA */ 250 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 251 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 252 253 sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 254 sc->sc_rxdr.ds_len = 1; 255 sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(); 256 if (sc->sc_rxdx == NULL) { 257 aprint_error_dev(sc->sc_dev, 258 "couldn't alloc rx dma xfer\n"); 259 goto free_intr; 260 } 261 sc->sc_rxdx->dx_cookie = sc; 262 sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 263 sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 264 sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 265 sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 266 sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 267 sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 268 sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 269 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 270 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 271 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 272 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 273 274 sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 275 sc->sc_txdr.ds_len = 1; 276 sc->sc_txdx = pxa2x0_dmac_allocate_xfer(); 277 if (sc->sc_txdx == NULL) { 278 aprint_error_dev(sc->sc_dev, 279 "couldn't alloc tx dma xfer\n"); 280 goto free_xfer; 281 } 282 sc->sc_txdx->dx_cookie = sc; 283 sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 284 sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 285 sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 286 sc->sc_txdx->dx_done = pxamci_dmac_ointr; 287 sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 288 sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 289 sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 290 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 291 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 292 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 293 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 294 } 295 296 /* 297 * Attach the generic SD/MMC bus driver. (The bus driver must 298 * not invoke any chipset functions before it is attached.) 299 */ 300 memset(&saa, 0, sizeof(saa)); 301 saa.saa_busname = "sdmmc"; 302 saa.saa_sct = &pxamci_chip_functions; 303 saa.saa_sch = sc; 304 saa.saa_dmat = pxa->pxa_dmat; 305 saa.saa_clkmin = sc->sc_clkmin; 306 saa.saa_clkmax = sc->sc_clkmax; 307 saa.saa_caps = 0; 308 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 309 SET(saa.saa_caps, SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA); 310 if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 311 SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 312 313 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 314 if (sc->sc_sdmmc == NULL) { 315 aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 316 goto free_xfer; 317 } 318 return 0; 319 320 free_xfer: 321 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 322 if (sc->sc_rxdx) 323 pxa2x0_dmac_free_xfer(sc->sc_rxdx); 324 if (sc->sc_txdx) 325 pxa2x0_dmac_free_xfer(sc->sc_txdx); 326 } 327 free_intr: 328 pxa2x0_intr_disestablish(sc->sc_ih); 329 sc->sc_ih = NULL; 330 free_map: 331 bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 332 out: 333 pxa2x0_clkman_config(CKEN_MMC, 0); 334 return 1; 335 } 336 337 /* 338 * Notify card attach/detach event. 339 */ 340 void 341 pxamci_card_detect_event(struct pxamci_softc *sc) 342 { 343 344 sdmmc_needs_discover(sc->sc_sdmmc); 345 } 346 347 /* 348 * Reset the host controller. Called during initialization, when 349 * cards are removed, upon resume, and during error recovery. 350 */ 351 static int 352 pxamci_host_reset(sdmmc_chipset_handle_t sch) 353 { 354 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 355 int s; 356 357 s = splsdmmc(); 358 359 CSR_WRITE_4(sc, MMC_SPI, 0); 360 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 361 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 362 363 /* Make sure to initialize the card before the next command. */ 364 CLR(sc->sc_flags, PMF_CARDINITED); 365 366 splx(s); 367 368 return 0; 369 } 370 371 static uint32_t 372 pxamci_host_ocr(sdmmc_chipset_handle_t sch) 373 { 374 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 375 int rv; 376 377 if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 378 rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 379 return rv; 380 } 381 382 DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 383 device_xname(sc->sc_dev))); 384 return ENXIO; 385 } 386 387 static int 388 pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 389 { 390 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 391 392 return sc->sc_maxblklen; 393 } 394 395 static int 396 pxamci_card_detect(sdmmc_chipset_handle_t sch) 397 { 398 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 399 400 if (__predict_true(sc->sc_tag.card_detect != NULL)) { 401 return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 402 } 403 404 DPRINTF(0,("%s: driver lacks card_detect() function.\n", 405 device_xname(sc->sc_dev))); 406 return 1; /* always detect */ 407 } 408 409 static int 410 pxamci_write_protect(sdmmc_chipset_handle_t sch) 411 { 412 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 413 414 if (__predict_true(sc->sc_tag.write_protect != NULL)) { 415 return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 416 } 417 418 DPRINTF(0,("%s: driver lacks write_protect() function.\n", 419 device_xname(sc->sc_dev))); 420 return 0; /* non-protect */ 421 } 422 423 /* 424 * Set or change SD bus voltage and enable or disable SD bus power. 425 * Return zero on success. 426 */ 427 static int 428 pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 429 { 430 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 431 432 /* 433 * Bus power management is beyond control of the SD/SDIO/MMC 434 * block of the PXA2xx processors, so we have to hand this 435 * task off to the attachment driver. 436 */ 437 if (__predict_true(sc->sc_tag.set_power != NULL)) { 438 return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 439 } 440 441 DPRINTF(0,("%s: driver lacks set_power() function\n", 442 device_xname(sc->sc_dev))); 443 return ENXIO; 444 } 445 446 /* 447 * Set or change MMCLK frequency or disable the MMC clock. 448 * Return zero on success. 449 */ 450 static int 451 pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 452 { 453 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 454 int actfreq; 455 int div; 456 int rv = 0; 457 int s; 458 459 s = splsdmmc(); 460 461 /* 462 * Stop MMC clock before changing the frequency. 463 */ 464 pxamci_stop_clock(sc); 465 466 /* Just stop the clock. */ 467 if (freq == 0) 468 goto out; 469 470 /* 471 * PXA27x Errata... 472 * 473 * <snip> 474 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 475 * 476 * SD/SDIO controller can only support up to 9.75 Mbps data 477 * transfer rate for SDIO card. 478 * </snip> 479 * 480 * If we don't limit the frequency, CRC errors will be 481 * reported by the controller after we set the bus speed. 482 * XXX slow down incrementally. 483 */ 484 if (CPU_IS_PXA270) { 485 if (freq > 9750) { 486 freq = 9750; 487 } 488 } 489 490 /* 491 * Pick the smallest divider that produces a frequency not 492 * more than `freq' KHz. 493 */ 494 actfreq = sc->sc_clkmax; 495 for (div = 0; div < 7; actfreq /= 2, div++) { 496 if (actfreq <= freq) 497 break; 498 } 499 if (div == 7) { 500 aprint_error_dev(sc->sc_dev, 501 "unsupported bus frequency of %d KHz\n", freq); 502 rv = 1; 503 goto out; 504 } 505 506 DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 507 device_xname(sc->sc_dev), freq, actfreq, div)); 508 509 sc->sc_clkbase = actfreq; 510 sc->sc_clkrt = div; 511 512 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 513 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 514 515 out: 516 splx(s); 517 518 return rv; 519 } 520 521 static int 522 pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 523 { 524 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 525 int rv = 0; 526 int s; 527 528 s = splsdmmc(); 529 530 switch (width) { 531 case 1: 532 break; 533 case 4: 534 if (CPU_IS_PXA270) 535 break; 536 /*FALLTHROUGH*/ 537 default: 538 DPRINTF(0,("%s: unsupported bus width (%d)\n", 539 device_xname(sc->sc_dev), width)); 540 rv = 1; 541 goto out; 542 } 543 544 sc->sc_buswidth = width; 545 546 out: 547 splx(s); 548 549 return rv; 550 } 551 552 static int 553 pxamci_bus_rod(sdmmc_chipset_handle_t sch, int on) 554 { 555 556 /* not support */ 557 return -1; 558 } 559 560 static void 561 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 562 { 563 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 564 uint32_t cmdat; 565 int error; 566 int timo; 567 int s; 568 569 DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x\n", 570 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_arg, cmd->c_data, 571 cmd->c_datalen, cmd->c_flags)); 572 573 s = splsdmmc(); 574 575 /* Stop the bus clock (MMCLK). [15.8.3] */ 576 pxamci_stop_clock(sc); 577 578 /* Set the command and argument. */ 579 CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 580 CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 581 CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 582 583 /* Response type */ 584 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 585 cmdat = CMDAT_RESPONSE_FORMAT_NO; 586 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 587 cmdat = CMDAT_RESPONSE_FORMAT_R2; 588 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 589 cmdat = CMDAT_RESPONSE_FORMAT_R3; 590 else 591 cmdat = CMDAT_RESPONSE_FORMAT_R1; 592 593 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 594 cmdat |= CMDAT_BUSY; 595 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 596 cmdat |= CMDAT_WRITE; 597 if (sc->sc_buswidth == 4) 598 cmdat |= CMDAT_SD_4DAT; 599 600 /* Fragment the data into proper blocks. */ 601 if (cmd->c_datalen > 0) { 602 int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 603 int numblk = cmd->c_datalen / blklen; 604 605 if (cmd->c_datalen % blklen > 0) { 606 /* XXX: Split this command. (1.7.4) */ 607 aprint_error_dev(sc->sc_dev, 608 "data not a multiple of %u bytes\n", blklen); 609 cmd->c_error = EINVAL; 610 goto out; 611 } 612 613 /* Check limit imposed by block count. */ 614 if (numblk > NOB_MASK) { 615 aprint_error_dev(sc->sc_dev, "too much data\n"); 616 cmd->c_error = EINVAL; 617 goto out; 618 } 619 620 CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 621 CSR_WRITE_4(sc, MMC_NOB, numblk); 622 CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 623 624 cmdat |= CMDAT_DATA_EN; 625 626 /* setting DMA */ 627 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 628 && DMA_ALIGNED(cmd->c_data)) { 629 struct dmac_xfer_desc *dx_desc; 630 631 DPRINTF(1,("%s: using DMA\n",device_xname(sc->sc_dev))); 632 633 cmdat |= CMDAT_MMC_DMA_EN; 634 635 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 636 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 637 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 638 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 639 error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 640 } else { 641 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 642 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 643 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 644 /* workaround for erratum #91 */ 645 error = 0; 646 if (!CPU_IS_PXA270) { 647 error = 648 pxa2x0_dmac_start_xfer(sc->sc_txdx); 649 } 650 } 651 if (error) { 652 aprint_error_dev(sc->sc_dev, 653 "couldn't start dma xfer. (error=%d)\n", 654 error); 655 cmd->c_error = EIO; 656 goto err; 657 } 658 } else { 659 DPRINTF(1,("%s: using PIO\n",device_xname(sc->sc_dev))); 660 661 cmd->c_resid = cmd->c_datalen; 662 cmd->c_buf = cmd->c_data; 663 664 pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 665 | MMC_I_TXFIFO_WR_REQ 666 | MMC_I_DAT_ERR); 667 } 668 } 669 670 sc->sc_cmd = cmd; 671 672 /* 673 * "After reset, the MMC card must be initialized by sending 674 * 80 clocks to it on the MMCLK signal." [15.4.3.2] 675 */ 676 if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 677 DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 678 cmdat |= CMDAT_INIT; 679 SET(sc->sc_flags, PMF_CARDINITED); 680 } 681 682 /* Begin the transfer and start the bus clock. */ 683 CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 684 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 685 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 686 687 /* Wait for it to complete */ 688 pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 689 for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 690 tsleep(sc, PWAIT, "mmcmd", hz); 691 } 692 693 /* If it completed in time, SCF_ITSDONE is already set. */ 694 if (sc->sc_cmd == cmd) { 695 cmd->c_error = ETIMEDOUT; 696 err: 697 SET(cmd->c_flags, SCF_ITSDONE); 698 sc->sc_cmd = NULL; 699 goto out; 700 } 701 702 out: 703 splx(s); 704 705 DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 706 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 707 } 708 709 static void 710 pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 711 { 712 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 713 714 if (enable) { 715 pxamci_enable_intr(sc, MMC_I_SDIO_INT); 716 } else { 717 pxamci_disable_intr(sc, MMC_I_SDIO_INT); 718 } 719 } 720 721 static void 722 pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 723 { 724 725 /* Nothing to do */ 726 } 727 728 static void 729 pxamci_stop_clock(struct pxamci_softc *sc) 730 { 731 int timo = STOPCLK_TIMO; 732 733 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 734 CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 735 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 736 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 737 && (timo-- > 0)) { 738 tsleep(sc, PWAIT, "mmclk", hz); 739 } 740 } 741 if (timo == 0) 742 aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 743 } 744 745 /* 746 * SD/MMC controller interrput handler 747 */ 748 static int 749 pxamci_intr(void *arg) 750 { 751 struct pxamci_softc *sc = arg; 752 int status; 753 #ifdef PXAMCI_DEBUG 754 int ostatus; 755 756 ostatus = 757 #endif 758 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 759 DPRINTF(10,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 760 status)); 761 762 /* 763 * Notify the process waiting in pxamci_clock_stop() when 764 * the clock has really stopped. 765 */ 766 if (ISSET(status, MMC_I_CLK_IS_OFF)) { 767 DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 768 wakeup(sc); 769 pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 770 CLR(status, MMC_I_CLK_IS_OFF); 771 } 772 773 if (sc->sc_cmd == NULL) 774 goto end; 775 776 if (ISSET(status, MMC_I_RES_ERR)) { 777 DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 778 device_xname(sc->sc_dev))); 779 pxamci_disable_intr(sc, MMC_I_RES_ERR); 780 CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 781 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 782 && (sc->sc_cmd->c_datalen > 0) 783 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 784 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 785 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 786 } else { 787 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 788 } 789 } 790 sc->sc_cmd->c_error = ENOEXEC; 791 pxamci_intr_done(sc); 792 goto end; 793 } 794 795 if (ISSET(status, MMC_I_END_CMD_RES)) { 796 DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 797 device_xname(sc->sc_dev))); 798 pxamci_intr_cmd(sc); 799 pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 800 CLR(status, MMC_I_END_CMD_RES); 801 /* ignore programming done condition */ 802 if (ISSET(status, MMC_I_PRG_DONE)) { 803 pxamci_disable_intr(sc, MMC_I_PRG_DONE); 804 CLR(status, MMC_I_PRG_DONE); 805 } 806 if (sc->sc_cmd == NULL) 807 goto end; 808 } 809 810 if (ISSET(status, MMC_I_DAT_ERR)) { 811 DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 812 device_xname(sc->sc_dev))); 813 sc->sc_cmd->c_error = EIO; 814 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 815 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 816 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 817 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 818 } else { 819 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 820 } 821 } 822 pxamci_intr_done(sc); 823 pxamci_disable_intr(sc, MMC_I_DAT_ERR); 824 CLR(status, MMC_I_DAT_ERR); 825 /* ignore transmission done condition */ 826 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 827 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 828 CLR(status, MMC_I_DATA_TRAN_DONE); 829 } 830 goto end; 831 } 832 833 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 834 DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 835 device_xname(sc->sc_dev))); 836 pxamci_intr_done(sc); 837 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 838 CLR(status, MMC_I_DATA_TRAN_DONE); 839 } 840 841 if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 842 DPRINTF(10,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 843 device_xname(sc->sc_dev))); 844 pxamci_intr_data(sc); 845 CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 846 } 847 848 if (ISSET(status, STAT_SDIO_INT)) { 849 DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 850 device_xname(sc->sc_dev))); 851 sdmmc_card_intr(sc->sc_sdmmc); 852 CLR(status, STAT_SDIO_INT); 853 } 854 855 end: 856 /* Avoid further unhandled interrupts. */ 857 if (status != 0) { 858 pxamci_disable_intr(sc, status); 859 #ifdef PXAMCI_DEBUG 860 aprint_error_dev(sc->sc_dev, 861 "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 862 #endif 863 } 864 return 1; 865 } 866 867 static void 868 pxamci_intr_cmd(struct pxamci_softc *sc) 869 { 870 struct sdmmc_command *cmd = sc->sc_cmd; 871 uint32_t status; 872 int error; 873 int i; 874 875 KASSERT(sc->sc_cmd != NULL); 876 877 #define STAT_ERR (STAT_READ_TIME_OUT \ 878 | STAT_TIMEOUT_RESPONSE \ 879 | STAT_CRC_WRITE_ERROR \ 880 | STAT_CRC_READ_ERROR \ 881 | STAT_SPI_READ_ERROR_TOKEN) 882 883 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 884 for (i = 3; i >= 0; i--) { 885 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 886 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 887 cmd->c_resp[i] = (h << 16) | l; 888 } 889 cmd->c_error = 0; 890 } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 891 /* 892 * Grrr... The processor manual is not clear about 893 * the layout of the response FIFO. It just states 894 * that the FIFO is 16 bits wide, has a depth of 8, 895 * and that the CRC is not copied into the FIFO. 896 * 897 * A 16-bit word in the FIFO is filled from highest 898 * to lowest bit as the response comes in. The two 899 * start bits and the 6 command index bits are thus 900 * stored in the upper 8 bits of the first 16-bit 901 * word that we read back from the FIFO. 902 * 903 * Since the sdmmc(4) framework expects the host 904 * controller to discard the first 8 bits of the 905 * response, what we must do is discard the upper 906 * byte of the first 16-bit word. 907 */ 908 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 909 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 910 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 911 cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 912 for (i = 1; i < 4; i++) 913 cmd->c_resp[i] = 0; 914 cmd->c_error = 0; 915 } 916 917 status = CSR_READ_4(sc, MMC_STAT); 918 919 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 920 CLR(status, STAT_TIMEOUT_RESPONSE); 921 922 /* XXX only for R6, not for R2 */ 923 if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 924 CLR(status, STAT_RES_CRC_ERR); 925 926 if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 927 cmd->c_error = ETIMEDOUT; 928 else if (ISSET(status, STAT_RES_CRC_ERR) 929 && ISSET(cmd->c_flags, SCF_RSP_CRC) 930 && CPU_IS_PXA270) { 931 /* workaround for erratum #42 */ 932 if (ISSET(cmd->c_flags, SCF_RSP_136) 933 && (cmd->c_resp[0] & 0x80000000U)) { 934 DPRINTF(1,("%s: ignore CRC error\n", 935 device_xname(sc->sc_dev))); 936 } else 937 cmd->c_error = EIO; 938 } else if (ISSET(status, STAT_ERR)) 939 cmd->c_error = EIO; 940 941 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 942 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 943 && DMA_ALIGNED(cmd->c_data)) { 944 /* workaround for erratum #91 */ 945 if (CPU_IS_PXA270 946 && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 947 error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 948 if (error) { 949 aprint_error_dev(sc->sc_dev, 950 "couldn't start dma xfer." 951 " (error=%d)\n", error); 952 cmd->c_error = EIO; 953 pxamci_intr_done(sc); 954 return; 955 } 956 } 957 pxamci_enable_intr(sc, 958 MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 959 } 960 } else { 961 pxamci_intr_done(sc); 962 } 963 } 964 965 static void 966 pxamci_intr_data(struct pxamci_softc *sc) 967 { 968 struct sdmmc_command *cmd = sc->sc_cmd; 969 int intr; 970 int n; 971 972 DPRINTF(10,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 973 device_xname(sc->sc_dev), cmd, cmd->c_resid)); 974 975 n = MIN(32, cmd->c_resid); 976 cmd->c_resid -= n; 977 978 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 979 intr = MMC_I_RXFIFO_RD_REQ; 980 while (n-- > 0) 981 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 982 } else { 983 int short_xfer = n < 32; 984 985 intr = MMC_I_TXFIFO_WR_REQ; 986 while (n-- > 0) 987 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 988 if (short_xfer) 989 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 990 } 991 992 if (cmd->c_resid > 0) { 993 pxamci_enable_intr(sc, intr); 994 } else { 995 pxamci_disable_intr(sc, intr); 996 pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE); 997 } 998 } 999 1000 /* 1001 * Wake up the process sleeping in pxamci_exec_command(). 1002 */ 1003 static void 1004 pxamci_intr_done(struct pxamci_softc *sc) 1005 { 1006 1007 DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 1008 device_xname(sc->sc_dev), CSR_READ_4(sc, MMC_STAT))); 1009 1010 pxamci_disable_intr(sc, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ| 1011 MMC_I_DATA_TRAN_DONE|MMC_I_END_CMD_RES|MMC_I_RES_ERR|MMC_I_DAT_ERR); 1012 SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 1013 sc->sc_cmd = NULL; 1014 wakeup(sc); 1015 } 1016 1017 static void 1018 pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 1019 { 1020 struct pxamci_softc *sc = dx->dx_cookie; 1021 1022 DPRINTF(1,("%s: pxamci_dmac_iintr: status = %#x\n", 1023 device_xname(sc->sc_dev), status)); 1024 1025 if (status) { 1026 aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1027 "non-zero completion status %d\n", status); 1028 } 1029 } 1030 1031 static void 1032 pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1033 { 1034 struct pxamci_softc *sc = dx->dx_cookie; 1035 1036 DPRINTF(1,("%s: pxamci_dmac_ointr: status = %#x\n", 1037 device_xname(sc->sc_dev), status)); 1038 1039 if (status == 0) { 1040 if (sc->sc_cmd != NULL && (sc->sc_cmd->c_datalen & 31) != 0) { 1041 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 1042 } 1043 } else { 1044 aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1045 "non-zero completion status %d\n", status); 1046 } 1047 } 1048
Indexes created Sun Sep 28 12:09:53 GMT 2025