pxa2x0_mci.c revision 1.4
1 /* $NetBSD: pxa2x0_mci.c,v 1.4 2010/03/13 12:28:44 nonaka Exp $ */ 2 /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (c) 2007-2009 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 /* 47 * MMC/SD/SDIO controller driver for Intel PXA2xx processors 48 * 49 * Power management is beyond control of the processor's SD/SDIO/MMC 50 * block, so this driver depends on the attachment driver to provide 51 * us with some callback functions via the "tag" member in our softc. 52 * Bus power management calls are then dispatched to the attachment 53 * driver. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.4 2010/03/13 12:28:44 nonaka Exp $"); 58 59 #include <sys/param.h> 60 #include <sys/device.h> 61 #include <sys/systm.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/proc.h> 65 #include <sys/bus.h> 66 #include <sys/mutex.h> 67 #include <sys/condvar.h> 68 69 #include <machine/intr.h> 70 71 #include <dev/sdmmc/sdmmcvar.h> 72 #include <dev/sdmmc/sdmmcchip.h> 73 74 #include <arm/xscale/pxa2x0cpu.h> 75 #include <arm/xscale/pxa2x0reg.h> 76 #include <arm/xscale/pxa2x0var.h> 77 #include <arm/xscale/pxa2x0_dmac.h> 78 #include <arm/xscale/pxa2x0_gpio.h> 79 #include <arm/xscale/pxa2x0_mci.h> 80 81 #ifdef PXAMCI_DEBUG 82 int pxamci_debug = 1; 83 #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 84 #else 85 #define DPRINTF(n,s) do {} while (0) 86 #endif 87 88 #ifndef DEBUG 89 #define STOPCLK_TIMO 2 /* ms */ 90 #define EXECCMD_TIMO 2 /* ms */ 91 #else 92 #define STOPCLK_TIMO 2 /* ms */ 93 #define EXECCMD_TIMO 5 /* ms */ 94 #endif 95 96 static int pxamci_host_reset(sdmmc_chipset_handle_t); 97 static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 98 static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 99 static int pxamci_card_detect(sdmmc_chipset_handle_t); 100 static int pxamci_write_protect(sdmmc_chipset_handle_t); 101 static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 102 static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 103 static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 104 static void pxamci_exec_command(sdmmc_chipset_handle_t, 105 struct sdmmc_command *); 106 static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 107 static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 108 109 static struct sdmmc_chip_functions pxamci_chip_functions = { 110 /* host controller reset */ 111 .host_reset = pxamci_host_reset, 112 113 /* host controller capabilities */ 114 .host_ocr = pxamci_host_ocr, 115 .host_maxblklen = pxamci_host_maxblklen, 116 117 /* card detection */ 118 .card_detect = pxamci_card_detect, 119 120 /* write protect */ 121 .write_protect = pxamci_write_protect, 122 123 /* bus power, clock frequency, width */ 124 .bus_power = pxamci_bus_power, 125 .bus_clock = pxamci_bus_clock, 126 .bus_width = pxamci_bus_width, 127 128 /* command execution */ 129 .exec_command = pxamci_exec_command, 130 131 /* card interrupt */ 132 .card_enable_intr = pxamci_card_enable_intr, 133 .card_intr_ack = pxamci_card_intr_ack, 134 }; 135 136 static int pxamci_intr(void *); 137 static void pxamci_intr_cmd(struct pxamci_softc *); 138 static void pxamci_intr_data(struct pxamci_softc *); 139 static void pxamci_intr_done(struct pxamci_softc *); 140 static void pxamci_dmac_iintr(struct dmac_xfer *, int); 141 static void pxamci_dmac_ointr(struct dmac_xfer *, int); 142 143 static void pxamci_stop_clock(struct pxamci_softc *); 144 145 #define CSR_READ_1(sc, reg) \ 146 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 147 #define CSR_WRITE_1(sc, reg, val) \ 148 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 149 #define CSR_READ_4(sc, reg) \ 150 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 151 #define CSR_WRITE_4(sc, reg, val) \ 152 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 153 #define CSR_SET_4(sc, reg, val) \ 154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 155 #define CSR_CLR_4(sc, reg, val) \ 156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 157 158 static void 159 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 160 { 161 int s; 162 163 s = splsdmmc(); 164 sc->sc_imask &= ~mask; 165 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 166 splx(s); 167 } 168 169 static void 170 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 171 { 172 int s; 173 174 s = splsdmmc(); 175 sc->sc_imask |= mask; 176 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 177 splx(s); 178 } 179 180 int 181 pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 182 { 183 struct pxamci_softc *sc = device_private(self); 184 struct sdmmcbus_attach_args saa; 185 186 sc->sc_dev = self; 187 188 aprint_normal(": MMC/SD Controller\n"); 189 aprint_naive("\n"); 190 191 /* Enable the clocks to the MMC controller. */ 192 pxa2x0_clkman_config(CKEN_MMC, 1); 193 194 sc->sc_iot = pxa->pxa_iot; 195 if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 196 &sc->sc_ioh)) { 197 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 198 goto out; 199 } 200 201 /* 202 * Establish the card detection and MMC interrupt handlers and 203 * mask all interrupts until we are prepared to handle them. 204 */ 205 pxamci_disable_intr(sc, MMC_I_ALL); 206 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 207 pxamci_intr, sc); 208 if (sc->sc_ih == NULL) { 209 aprint_error_dev(sc->sc_dev, 210 "couldn't establish MMC interrupt\n"); 211 goto free_map; 212 } 213 214 /* 215 * Reset the host controller and unmask normal interrupts. 216 */ 217 (void) pxamci_host_reset(sc); 218 219 /* Setup bus clock */ 220 if (CPU_IS_PXA270) { 221 sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 222 sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 223 } else { 224 sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 225 sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 226 } 227 sc->sc_clkbase = sc->sc_clkmin; 228 pxamci_bus_clock(sc, sc->sc_clkbase); 229 230 /* Setup max block length */ 231 if (CPU_IS_PXA270) { 232 sc->sc_maxblklen = 2048; 233 } else { 234 sc->sc_maxblklen = 512; 235 } 236 237 /* Set default bus width */ 238 sc->sc_buswidth = 1; 239 240 /* setting DMA */ 241 #if 1 /* XXX */ 242 SET(sc->sc_caps, PMC_CAPS_NO_DMA); /* disable DMA */ 243 #endif 244 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 245 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 246 247 sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 248 sc->sc_rxdr.ds_len = 1; 249 sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 250 if (sc->sc_rxdx == NULL) { 251 aprint_error_dev(sc->sc_dev, 252 "couldn't alloc rx dma xfer\n"); 253 goto free_intr; 254 } 255 sc->sc_rxdx->dx_cookie = sc; 256 sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 257 sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 258 sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 259 sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 260 sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 261 sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 262 sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 263 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 264 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 265 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 266 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 267 268 sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 269 sc->sc_txdr.ds_len = 1; 270 sc->sc_txdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 271 if (sc->sc_txdx == NULL) { 272 aprint_error_dev(sc->sc_dev, 273 "couldn't alloc tx dma xfer\n"); 274 goto free_xfer; 275 } 276 sc->sc_txdx->dx_cookie = sc; 277 sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 278 sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 279 sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 280 sc->sc_txdx->dx_done = pxamci_dmac_ointr; 281 sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 282 sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 283 sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 284 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 285 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 286 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 287 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 288 } 289 290 /* 291 * Attach the generic SD/MMC bus driver. (The bus driver must 292 * not invoke any chipset functions before it is attached.) 293 */ 294 memset(&saa, 0, sizeof(saa)); 295 saa.saa_busname = "sdmmc"; 296 saa.saa_sct = &pxamci_chip_functions; 297 saa.saa_sch = sc; 298 saa.saa_dmat = pxa->pxa_dmat; 299 saa.saa_clkmin = sc->sc_clkmin; 300 saa.saa_clkmax = sc->sc_clkmax; 301 saa.saa_caps = 0; 302 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 303 SET(saa.saa_caps, SMC_CAPS_DMA); 304 #if notyet 305 if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 306 SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 307 #endif 308 309 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 310 if (sc->sc_sdmmc == NULL) { 311 aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 312 goto free_xfer; 313 } 314 return 0; 315 316 free_xfer: 317 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 318 if (sc->sc_rxdx) 319 pxa2x0_dmac_free_xfer(sc->sc_rxdx); 320 if (sc->sc_txdx) 321 pxa2x0_dmac_free_xfer(sc->sc_txdx); 322 } 323 free_intr: 324 pxa2x0_intr_disestablish(sc->sc_ih); 325 sc->sc_ih = NULL; 326 free_map: 327 bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 328 out: 329 pxa2x0_clkman_config(CKEN_MMC, 0); 330 return 1; 331 } 332 333 /* 334 * Notify card attach/detach event. 335 */ 336 void 337 pxamci_card_detect_event(struct pxamci_softc *sc) 338 { 339 340 sdmmc_needs_discover(sc->sc_sdmmc); 341 } 342 343 /* 344 * Reset the host controller. Called during initialization, when 345 * cards are removed, upon resume, and during error recovery. 346 */ 347 static int 348 pxamci_host_reset(sdmmc_chipset_handle_t sch) 349 { 350 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 351 int s; 352 353 s = splsdmmc(); 354 355 CSR_WRITE_4(sc, MMC_SPI, 0); 356 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 357 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 358 359 /* Make sure to initialize the card before the next command. */ 360 CLR(sc->sc_flags, PMF_CARDINITED); 361 362 splx(s); 363 364 return 0; 365 } 366 367 static uint32_t 368 pxamci_host_ocr(sdmmc_chipset_handle_t sch) 369 { 370 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 371 int rv; 372 373 if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 374 rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 375 return rv; 376 } 377 378 DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 379 device_xname(sc->sc_dev))); 380 return ENXIO; 381 } 382 383 static int 384 pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 385 { 386 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 387 388 return sc->sc_maxblklen; 389 } 390 391 static int 392 pxamci_card_detect(sdmmc_chipset_handle_t sch) 393 { 394 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 395 396 if (__predict_true(sc->sc_tag.card_detect != NULL)) { 397 return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 398 } 399 400 DPRINTF(0,("%s: driver lacks card_detect() function.\n", 401 device_xname(sc->sc_dev))); 402 return 1; /* always detect */ 403 } 404 405 static int 406 pxamci_write_protect(sdmmc_chipset_handle_t sch) 407 { 408 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 409 410 if (__predict_true(sc->sc_tag.write_protect != NULL)) { 411 return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 412 } 413 414 DPRINTF(0,("%s: driver lacks write_protect() function.\n", 415 device_xname(sc->sc_dev))); 416 return 0; /* non-protect */ 417 } 418 419 /* 420 * Set or change SD bus voltage and enable or disable SD bus power. 421 * Return zero on success. 422 */ 423 static int 424 pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 425 { 426 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 427 428 /* 429 * Bus power management is beyond control of the SD/SDIO/MMC 430 * block of the PXA2xx processors, so we have to hand this 431 * task off to the attachment driver. 432 */ 433 if (__predict_true(sc->sc_tag.set_power != NULL)) { 434 return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 435 } 436 437 DPRINTF(0,("%s: driver lacks set_power() function\n", 438 device_xname(sc->sc_dev))); 439 return ENXIO; 440 } 441 442 /* 443 * Set or change MMCLK frequency or disable the MMC clock. 444 * Return zero on success. 445 */ 446 static int 447 pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 448 { 449 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 450 int actfreq; 451 int div; 452 int rv = 0; 453 int s; 454 455 s = splsdmmc(); 456 457 /* 458 * Stop MMC clock before changing the frequency. 459 */ 460 pxamci_stop_clock(sc); 461 462 /* Just stop the clock. */ 463 if (freq == 0) 464 goto out; 465 466 /* 467 * PXA27x Errata... 468 * 469 * <snip> 470 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 471 * 472 * SD/SDIO controller can only support up to 9.75 Mbps data 473 * transfer rate for SDIO card. 474 * </snip> 475 * 476 * If we don't limit the frequency, CRC errors will be 477 * reported by the controller after we set the bus speed. 478 * XXX slow down incrementally. 479 */ 480 if (CPU_IS_PXA270) { 481 if (freq > 9750) { 482 freq = 9750; 483 } 484 } 485 486 /* 487 * Pick the smallest divider that produces a frequency not 488 * more than `freq' KHz. 489 */ 490 actfreq = sc->sc_clkmax; 491 for (div = 0; div < 7; actfreq /= 2, div++) { 492 if (actfreq <= freq) 493 break; 494 } 495 if (div == 7) { 496 aprint_error_dev(sc->sc_dev, 497 "unsupported bus frequency of %d KHz\n", freq); 498 rv = 1; 499 goto out; 500 } 501 502 DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 503 device_xname(sc->sc_dev), freq, actfreq, div)); 504 505 sc->sc_clkbase = actfreq; 506 sc->sc_clkrt = div; 507 508 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 509 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 510 511 out: 512 splx(s); 513 514 return rv; 515 } 516 517 static int 518 pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 519 { 520 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 521 int rv = 0; 522 int s; 523 524 s = splsdmmc(); 525 526 switch (width) { 527 case 1: 528 break; 529 case 4: 530 if (CPU_IS_PXA270) 531 break; 532 /*FALLTHROUGH*/ 533 default: 534 DPRINTF(0,("%s: unsupported bus width (%d)\n", 535 device_xname(sc->sc_dev), width)); 536 rv = 1; 537 goto out; 538 } 539 540 sc->sc_buswidth = width; 541 542 out: 543 splx(s); 544 545 return rv; 546 } 547 548 static void 549 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 550 { 551 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 552 uint32_t cmdat; 553 int error; 554 int timo; 555 int s; 556 557 DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x\n", 558 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_arg, cmd->c_data, 559 cmd->c_datalen, cmd->c_flags)); 560 561 s = splsdmmc(); 562 563 /* Stop the bus clock (MMCLK). [15.8.3] */ 564 pxamci_stop_clock(sc); 565 566 /* Set the command and argument. */ 567 CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 568 CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 569 CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 570 571 /* Response type */ 572 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 573 cmdat = CMDAT_RESPONSE_FORMAT_NO; 574 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 575 cmdat = CMDAT_RESPONSE_FORMAT_R2; 576 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 577 cmdat = CMDAT_RESPONSE_FORMAT_R3; 578 else 579 cmdat = CMDAT_RESPONSE_FORMAT_R1; 580 581 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 582 cmdat |= CMDAT_BUSY; 583 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 584 cmdat |= CMDAT_WRITE; 585 if (sc->sc_buswidth == 4) 586 cmdat |= CMDAT_SD_4DAT; 587 588 /* Fragment the data into proper blocks. */ 589 if (cmd->c_datalen > 0) { 590 int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 591 int numblk = cmd->c_datalen / blklen; 592 593 if (cmd->c_datalen % blklen > 0) { 594 /* XXX: Split this command. (1.7.4) */ 595 aprint_error_dev(sc->sc_dev, 596 "data not a multiple of %u bytes\n", blklen); 597 cmd->c_error = EINVAL; 598 goto out; 599 } 600 601 /* Check limit imposed by block count. */ 602 if (numblk > NOB_MASK) { 603 aprint_error_dev(sc->sc_dev, "too much data\n"); 604 cmd->c_error = EINVAL; 605 goto out; 606 } 607 608 CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 609 CSR_WRITE_4(sc, MMC_NOB, numblk); 610 CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 611 612 cmdat |= CMDAT_DATA_EN; 613 614 /* setting DMA */ 615 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 616 struct dmac_xfer_desc *dx_desc; 617 618 cmdat |= CMDAT_MMC_DMA_EN; 619 620 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 621 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 622 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 623 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 624 error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 625 } else { 626 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 627 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 628 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 629 /* workaround for erratum #91 */ 630 error = 0; 631 if (!CPU_IS_PXA270) { 632 error = 633 pxa2x0_dmac_start_xfer(sc->sc_txdx); 634 } 635 } 636 if (error) { 637 aprint_error_dev(sc->sc_dev, 638 "couldn't start dma xfer. (error=%d)\n", 639 error); 640 cmd->c_error = EIO; 641 goto err; 642 } 643 } else { 644 cmd->c_resid = cmd->c_datalen; 645 cmd->c_buf = cmd->c_data; 646 647 pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 648 | MMC_I_TXFIFO_WR_REQ 649 | MMC_I_DAT_ERR); 650 } 651 } 652 653 sc->sc_cmd = cmd; 654 655 /* 656 * "After reset, the MMC card must be initialized by sending 657 * 80 clocks to it on the MMCLK signal." [15.4.3.2] 658 */ 659 if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 660 DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 661 cmdat |= CMDAT_INIT; 662 SET(sc->sc_flags, PMF_CARDINITED); 663 } 664 665 /* Begin the transfer and start the bus clock. */ 666 CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 667 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 668 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 669 670 /* Wait for it to complete */ 671 pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 672 for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 673 tsleep(sc, PWAIT, "mmcmd", hz); 674 } 675 676 /* If it completed in time, SCF_ITSDONE is already set. */ 677 if (sc->sc_cmd == cmd) { 678 cmd->c_error = ETIMEDOUT; 679 err: 680 SET(cmd->c_flags, SCF_ITSDONE); 681 sc->sc_cmd = NULL; 682 goto out; 683 } 684 685 out: 686 splx(s); 687 688 DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 689 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 690 } 691 692 static void 693 pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 694 { 695 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 696 697 if (enable) { 698 pxamci_enable_intr(sc, MMC_I_SDIO_INT); 699 } else { 700 pxamci_disable_intr(sc, MMC_I_SDIO_INT); 701 } 702 } 703 704 static void 705 pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 706 { 707 708 /* Nothing to do */ 709 } 710 711 static void 712 pxamci_stop_clock(struct pxamci_softc *sc) 713 { 714 int timo = STOPCLK_TIMO; 715 716 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 717 CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 718 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 719 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 720 && (timo-- > 0)) { 721 tsleep(sc, PWAIT, "mmclk", hz); 722 } 723 } 724 if (timo == 0) 725 aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 726 } 727 728 /* 729 * SD/MMC controller interrput handler 730 */ 731 static int 732 pxamci_intr(void *arg) 733 { 734 struct pxamci_softc *sc = arg; 735 int status; 736 #ifdef PXAMCI_DEBUG 737 int ostatus; 738 739 ostatus = 740 #endif 741 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 742 DPRINTF(9,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 743 status)); 744 745 /* 746 * Notify the process waiting in pxamci_clock_stop() when 747 * the clock has really stopped. 748 */ 749 if (ISSET(status, MMC_I_CLK_IS_OFF)) { 750 DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 751 wakeup(sc); 752 pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 753 CLR(status, MMC_I_CLK_IS_OFF); 754 } 755 756 if (sc->sc_cmd == NULL) 757 goto end; 758 759 if (ISSET(status, MMC_I_RES_ERR)) { 760 DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 761 device_xname(sc->sc_dev))); 762 pxamci_disable_intr(sc, MMC_I_RES_ERR); 763 CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 764 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 765 && (sc->sc_cmd->c_datalen > 0)) { 766 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 767 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 768 } else { 769 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 770 } 771 } 772 sc->sc_cmd->c_error = ENOEXEC; 773 pxamci_intr_done(sc); 774 goto end; 775 } 776 777 if (ISSET(status, MMC_I_END_CMD_RES)) { 778 DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 779 device_xname(sc->sc_dev))); 780 pxamci_intr_cmd(sc); 781 pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 782 CLR(status, MMC_I_END_CMD_RES); 783 /* ignore programming done condition */ 784 if (ISSET(status, MMC_I_PRG_DONE)) { 785 pxamci_disable_intr(sc, MMC_I_PRG_DONE); 786 CLR(status, MMC_I_PRG_DONE); 787 } 788 if (sc->sc_cmd == NULL) 789 goto end; 790 } 791 792 if (ISSET(status, MMC_I_DAT_ERR)) { 793 DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 794 device_xname(sc->sc_dev))); 795 sc->sc_cmd->c_error = EIO; 796 pxamci_intr_done(sc); 797 pxamci_disable_intr(sc, MMC_I_DAT_ERR); 798 CLR(status, MMC_I_DAT_ERR); 799 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 800 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 801 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 802 } else { 803 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 804 } 805 } 806 /* ignore transmission done condition */ 807 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 808 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 809 CLR(status, MMC_I_DATA_TRAN_DONE); 810 } 811 goto end; 812 } 813 814 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 815 DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 816 device_xname(sc->sc_dev))); 817 pxamci_intr_done(sc); 818 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 819 CLR(status, MMC_I_DATA_TRAN_DONE); 820 } 821 822 if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 823 DPRINTF(9,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 824 device_xname(sc->sc_dev))); 825 pxamci_intr_data(sc); 826 CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 827 } 828 829 if (ISSET(status, STAT_SDIO_INT)) { 830 DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 831 device_xname(sc->sc_dev))); 832 sdmmc_card_intr(sc->sc_sdmmc); 833 CLR(status, STAT_SDIO_INT); 834 } 835 836 end: 837 /* Avoid further unhandled interrupts. */ 838 if (status != 0) { 839 pxamci_disable_intr(sc, status); 840 #ifdef PXAMCI_DEBUG 841 aprint_error_dev(sc->sc_dev, 842 "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 843 #endif 844 } 845 return 1; 846 } 847 848 static void 849 pxamci_intr_cmd(struct pxamci_softc *sc) 850 { 851 struct sdmmc_command *cmd = sc->sc_cmd; 852 uint32_t status; 853 int error; 854 int i; 855 856 KASSERT(sc->sc_cmd != NULL); 857 858 #define STAT_ERR (STAT_READ_TIME_OUT \ 859 | STAT_TIMEOUT_RESPONSE \ 860 | STAT_CRC_WRITE_ERROR \ 861 | STAT_CRC_READ_ERROR \ 862 | STAT_SPI_READ_ERROR_TOKEN) 863 864 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 865 for (i = 3; i >= 0; i--) { 866 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 867 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 868 cmd->c_resp[i] = (h << 16) | l; 869 } 870 cmd->c_error = 0; 871 } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 872 /* 873 * Grrr... The processor manual is not clear about 874 * the layout of the response FIFO. It just states 875 * that the FIFO is 16 bits wide, has a depth of 8, 876 * and that the CRC is not copied into the FIFO. 877 * 878 * A 16-bit word in the FIFO is filled from highest 879 * to lowest bit as the response comes in. The two 880 * start bits and the 6 command index bits are thus 881 * stored in the upper 8 bits of the first 16-bit 882 * word that we read back from the FIFO. 883 * 884 * Since the sdmmc(4) framework expects the host 885 * controller to discard the first 8 bits of the 886 * response, what we must do is discard the upper 887 * byte of the first 16-bit word. 888 */ 889 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 890 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 891 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 892 cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 893 for (i = 1; i < 4; i++) 894 cmd->c_resp[i] = 0; 895 cmd->c_error = 0; 896 } 897 898 status = CSR_READ_4(sc, MMC_STAT); 899 900 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 901 CLR(status, STAT_TIMEOUT_RESPONSE); 902 903 /* XXX only for R6, not for R2 */ 904 if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 905 CLR(status, STAT_RES_CRC_ERR); 906 907 if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 908 cmd->c_error = ETIMEDOUT; 909 else if (ISSET(status, STAT_RES_CRC_ERR) 910 && ISSET(cmd->c_flags, SCF_RSP_CRC) 911 && CPU_IS_PXA270) { 912 /* workaround for erratum #42 */ 913 if (ISSET(cmd->c_flags, SCF_RSP_136) 914 && (cmd->c_resp[0] & 0x80000000U)) { 915 DPRINTF(1,("%s: ignore CRC error\n", 916 device_xname(sc->sc_dev))); 917 } else 918 cmd->c_error = EIO; 919 } else if (ISSET(status, STAT_ERR)) 920 cmd->c_error = EIO; 921 922 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 923 /* workaround for erratum #91 */ 924 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 925 && CPU_IS_PXA270 926 && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 927 error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 928 if (error) { 929 aprint_error_dev(sc->sc_dev, 930 "couldn't start dma xfer. (error=%d)\n", 931 error); 932 cmd->c_error = EIO; 933 pxamci_intr_done(sc); 934 return; 935 } 936 pxamci_enable_intr(sc, 937 MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 938 } 939 } else { 940 pxamci_intr_done(sc); 941 } 942 } 943 944 static void 945 pxamci_intr_data(struct pxamci_softc *sc) 946 { 947 struct sdmmc_command *cmd = sc->sc_cmd; 948 int intr; 949 int n; 950 951 DPRINTF(1,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 952 device_xname(sc->sc_dev), cmd, cmd->c_resid)); 953 954 n = MIN(32, cmd->c_resid); 955 cmd->c_resid -= n; 956 957 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 958 intr = MMC_I_RXFIFO_RD_REQ; 959 while (n-- > 0) 960 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 961 } else { 962 int short_xfer = n < 32; 963 964 intr = MMC_I_TXFIFO_WR_REQ; 965 while (n-- > 0) 966 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 967 if (short_xfer) 968 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 969 } 970 971 if (cmd->c_resid > 0) { 972 pxamci_enable_intr(sc, intr); 973 } else { 974 pxamci_disable_intr(sc, intr); 975 pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE); 976 } 977 } 978 979 /* 980 * Wake up the process sleeping in pxamci_exec_command(). 981 */ 982 static void 983 pxamci_intr_done(struct pxamci_softc *sc) 984 { 985 986 DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 987 device_xname(sc->sc_dev), CSR_READ_4(sc, MMC_STAT))); 988 989 pxamci_disable_intr(sc, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ| 990 MMC_I_DATA_TRAN_DONE|MMC_I_END_CMD_RES|MMC_I_RES_ERR|MMC_I_DAT_ERR); 991 SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 992 sc->sc_cmd = NULL; 993 wakeup(sc); 994 } 995 996 static void 997 pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 998 { 999 struct pxamci_softc *sc = dx->dx_cookie; 1000 1001 if (status) { 1002 aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1003 "non-zero completion status %d\n", status); 1004 } 1005 } 1006 1007 static void 1008 pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1009 { 1010 struct pxamci_softc *sc = dx->dx_cookie; 1011 1012 if (status) { 1013 aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1014 "non-zero completion status %d\n", status); 1015 } 1016 } 1017
Indexes created Sun Oct 19 02:09:48 GMT 2025