pxa2x0_mci.c revision 1.7
1 /* $NetBSD: pxa2x0_mci.c,v 1.7 2010/10/07 12:06:09 kiyohara Exp $ */ 2 /* $OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (c) 2007-2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 /* 47 * MMC/SD/SDIO controller driver for Intel PXA2xx processors 48 * 49 * Power management is beyond control of the processor's SD/SDIO/MMC 50 * block, so this driver depends on the attachment driver to provide 51 * us with some callback functions via the "tag" member in our softc. 52 * Bus power management calls are then dispatched to the attachment 53 * driver. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.7 2010/10/07 12:06:09 kiyohara Exp $"); 58 59 #include <sys/param.h> 60 #include <sys/device.h> 61 #include <sys/systm.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/proc.h> 65 #include <sys/bus.h> 66 #include <sys/mutex.h> 67 #include <sys/condvar.h> 68 69 #include <machine/intr.h> 70 71 #include <dev/sdmmc/sdmmcvar.h> 72 #include <dev/sdmmc/sdmmcchip.h> 73 74 #include <arm/xscale/pxa2x0cpu.h> 75 #include <arm/xscale/pxa2x0reg.h> 76 #include <arm/xscale/pxa2x0var.h> 77 #include <arm/xscale/pxa2x0_dmac.h> 78 #include <arm/xscale/pxa2x0_gpio.h> 79 #include <arm/xscale/pxa2x0_mci.h> 80 81 #ifdef PXAMCI_DEBUG 82 int pxamci_debug = 9; 83 #define DPRINTF(n,s) do { if ((n) <= pxamci_debug) printf s; } while (0) 84 #else 85 #define DPRINTF(n,s) do {} while (0) 86 #endif 87 88 #ifndef PXAMCI_DEBUG 89 #define STOPCLK_TIMO 2 /* sec */ 90 #define EXECCMD_TIMO 2 /* sec */ 91 #else 92 #define STOPCLK_TIMO 2 /* sec */ 93 #define EXECCMD_TIMO 5 /* sec */ 94 #endif 95 96 static int pxamci_host_reset(sdmmc_chipset_handle_t); 97 static uint32_t pxamci_host_ocr(sdmmc_chipset_handle_t); 98 static int pxamci_host_maxblklen(sdmmc_chipset_handle_t); 99 static int pxamci_card_detect(sdmmc_chipset_handle_t); 100 static int pxamci_write_protect(sdmmc_chipset_handle_t); 101 static int pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t); 102 static int pxamci_bus_clock(sdmmc_chipset_handle_t, int); 103 static int pxamci_bus_width(sdmmc_chipset_handle_t, int); 104 static int pxamci_bus_rod(sdmmc_chipset_handle_t, int); 105 static void pxamci_exec_command(sdmmc_chipset_handle_t, 106 struct sdmmc_command *); 107 static void pxamci_card_enable_intr(sdmmc_chipset_handle_t, int); 108 static void pxamci_card_intr_ack(sdmmc_chipset_handle_t); 109 110 static struct sdmmc_chip_functions pxamci_chip_functions = { 111 /* host controller reset */ 112 .host_reset = pxamci_host_reset, 113 114 /* host controller capabilities */ 115 .host_ocr = pxamci_host_ocr, 116 .host_maxblklen = pxamci_host_maxblklen, 117 118 /* card detection */ 119 .card_detect = pxamci_card_detect, 120 121 /* write protect */ 122 .write_protect = pxamci_write_protect, 123 124 /* bus power, clock frequency, width */ 125 .bus_power = pxamci_bus_power, 126 .bus_clock = pxamci_bus_clock, 127 .bus_width = pxamci_bus_width, 128 .bus_rod = pxamci_bus_rod, 129 130 /* command execution */ 131 .exec_command = pxamci_exec_command, 132 133 /* card interrupt */ 134 .card_enable_intr = pxamci_card_enable_intr, 135 .card_intr_ack = pxamci_card_intr_ack, 136 }; 137 138 static int pxamci_intr(void *); 139 static void pxamci_intr_cmd(struct pxamci_softc *); 140 static void pxamci_intr_data(struct pxamci_softc *); 141 static void pxamci_intr_done(struct pxamci_softc *); 142 static void pxamci_dmac_iintr(struct dmac_xfer *, int); 143 static void pxamci_dmac_ointr(struct dmac_xfer *, int); 144 145 static void pxamci_stop_clock(struct pxamci_softc *); 146 147 #define CSR_READ_1(sc, reg) \ 148 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 149 #define CSR_WRITE_1(sc, reg, val) \ 150 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 151 #define CSR_READ_4(sc, reg) \ 152 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 153 #define CSR_WRITE_4(sc, reg, val) \ 154 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 155 #define CSR_SET_4(sc, reg, val) \ 156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 157 #define CSR_CLR_4(sc, reg, val) \ 158 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 159 160 #if 0 /* XXX */ 161 #define DMA_ALIGNED(addr) \ 162 (((u_long)(addr) & 0x7) == 0 || !CPU_IS_PXA250) 163 #else 164 #define DMA_ALIGNED(addr) \ 165 (((u_long)(addr) & 0x1f) == 0) 166 #endif 167 168 static void 169 pxamci_enable_intr(struct pxamci_softc *sc, uint32_t mask) 170 { 171 int s; 172 173 s = splsdmmc(); 174 sc->sc_imask &= ~mask; 175 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 176 splx(s); 177 } 178 179 static void 180 pxamci_disable_intr(struct pxamci_softc *sc, uint32_t mask) 181 { 182 int s; 183 184 s = splsdmmc(); 185 sc->sc_imask |= mask; 186 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 187 splx(s); 188 } 189 190 int 191 pxamci_attach_sub(device_t self, struct pxaip_attach_args *pxa) 192 { 193 struct pxamci_softc *sc = device_private(self); 194 struct sdmmcbus_attach_args saa; 195 196 sc->sc_dev = self; 197 198 aprint_normal(": MMC/SD Controller\n"); 199 aprint_naive("\n"); 200 201 /* Enable the clocks to the MMC controller. */ 202 pxa2x0_clkman_config(CKEN_MMC, 1); 203 204 sc->sc_iot = pxa->pxa_iot; 205 if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0, 206 &sc->sc_ioh)) { 207 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 208 goto out; 209 } 210 211 /* 212 * Establish the card detection and MMC interrupt handlers and 213 * mask all interrupts until we are prepared to handle them. 214 */ 215 pxamci_disable_intr(sc, MMC_I_ALL); 216 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC, 217 pxamci_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error_dev(sc->sc_dev, 220 "couldn't establish MMC interrupt\n"); 221 goto free_map; 222 } 223 224 /* 225 * Reset the host controller and unmask normal interrupts. 226 */ 227 (void) pxamci_host_reset(sc); 228 229 /* Setup bus clock */ 230 if (CPU_IS_PXA270) { 231 sc->sc_clkmin = PXA270_MMC_CLKRT_MIN / 1000; 232 sc->sc_clkmax = PXA270_MMC_CLKRT_MAX / 1000; 233 } else { 234 sc->sc_clkmin = PXA250_MMC_CLKRT_MIN / 1000; 235 sc->sc_clkmax = PXA250_MMC_CLKRT_MAX / 1000; 236 } 237 sc->sc_clkbase = sc->sc_clkmin; 238 pxamci_bus_clock(sc, sc->sc_clkbase); 239 240 /* Setup max block length */ 241 if (CPU_IS_PXA270) { 242 sc->sc_maxblklen = 2048; 243 } else { 244 sc->sc_maxblklen = 512; 245 } 246 247 /* Set default bus width */ 248 sc->sc_buswidth = 1; 249 250 /* setting DMA */ 251 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 252 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 253 254 sc->sc_rxdr.ds_addr = PXA2X0_MMC_BASE + MMC_RXFIFO; 255 sc->sc_rxdr.ds_len = 1; 256 sc->sc_rxdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 257 if (sc->sc_rxdx == NULL) { 258 aprint_error_dev(sc->sc_dev, 259 "couldn't alloc rx dma xfer\n"); 260 goto free_intr; 261 } 262 sc->sc_rxdx->dx_cookie = sc; 263 sc->sc_rxdx->dx_priority = DMAC_PRIORITY_NORMAL; 264 sc->sc_rxdx->dx_dev_width = DMAC_DEV_WIDTH_1; 265 sc->sc_rxdx->dx_burst_size = DMAC_BURST_SIZE_32; 266 sc->sc_rxdx->dx_done = pxamci_dmac_iintr; 267 sc->sc_rxdx->dx_peripheral = DMAC_PERIPH_MMCRX; 268 sc->sc_rxdx->dx_flow = DMAC_FLOW_CTRL_SRC; 269 sc->sc_rxdx->dx_loop_notify = DMAC_DONT_LOOP; 270 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 271 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 272 sc->sc_rxdx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_rxdr; 273 sc->sc_rxdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 274 275 sc->sc_txdr.ds_addr = PXA2X0_MMC_BASE + MMC_TXFIFO; 276 sc->sc_txdr.ds_len = 1; 277 sc->sc_txdx = pxa2x0_dmac_allocate_xfer(M_NOWAIT); 278 if (sc->sc_txdx == NULL) { 279 aprint_error_dev(sc->sc_dev, 280 "couldn't alloc tx dma xfer\n"); 281 goto free_xfer; 282 } 283 sc->sc_txdx->dx_cookie = sc; 284 sc->sc_txdx->dx_priority = DMAC_PRIORITY_NORMAL; 285 sc->sc_txdx->dx_dev_width = DMAC_DEV_WIDTH_1; 286 sc->sc_txdx->dx_burst_size = DMAC_BURST_SIZE_32; 287 sc->sc_txdx->dx_done = pxamci_dmac_ointr; 288 sc->sc_txdx->dx_peripheral = DMAC_PERIPH_MMCTX; 289 sc->sc_txdx->dx_flow = DMAC_FLOW_CTRL_DEST; 290 sc->sc_txdx->dx_loop_notify = DMAC_DONT_LOOP; 291 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 292 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 293 sc->sc_txdx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_txdr; 294 sc->sc_txdx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 295 } 296 297 /* 298 * Attach the generic SD/MMC bus driver. (The bus driver must 299 * not invoke any chipset functions before it is attached.) 300 */ 301 memset(&saa, 0, sizeof(saa)); 302 saa.saa_busname = "sdmmc"; 303 saa.saa_sct = &pxamci_chip_functions; 304 saa.saa_sch = sc; 305 saa.saa_dmat = pxa->pxa_dmat; 306 saa.saa_clkmin = sc->sc_clkmin; 307 saa.saa_clkmax = sc->sc_clkmax; 308 saa.saa_caps = 0; 309 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) 310 SET(saa.saa_caps, SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA); 311 if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT)) 312 SET(saa.saa_caps, SMC_CAPS_4BIT_MODE); 313 314 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 315 if (sc->sc_sdmmc == NULL) { 316 aprint_error_dev(sc->sc_dev, "couldn't attach bus\n"); 317 goto free_xfer; 318 } 319 return 0; 320 321 free_xfer: 322 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA)) { 323 if (sc->sc_rxdx) 324 pxa2x0_dmac_free_xfer(sc->sc_rxdx); 325 if (sc->sc_txdx) 326 pxa2x0_dmac_free_xfer(sc->sc_txdx); 327 } 328 free_intr: 329 pxa2x0_intr_disestablish(sc->sc_ih); 330 sc->sc_ih = NULL; 331 free_map: 332 bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE); 333 out: 334 pxa2x0_clkman_config(CKEN_MMC, 0); 335 return 1; 336 } 337 338 /* 339 * Notify card attach/detach event. 340 */ 341 void 342 pxamci_card_detect_event(struct pxamci_softc *sc) 343 { 344 345 sdmmc_needs_discover(sc->sc_sdmmc); 346 } 347 348 /* 349 * Reset the host controller. Called during initialization, when 350 * cards are removed, upon resume, and during error recovery. 351 */ 352 static int 353 pxamci_host_reset(sdmmc_chipset_handle_t sch) 354 { 355 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 356 int s; 357 358 s = splsdmmc(); 359 360 CSR_WRITE_4(sc, MMC_SPI, 0); 361 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 362 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 363 364 /* Make sure to initialize the card before the next command. */ 365 CLR(sc->sc_flags, PMF_CARDINITED); 366 367 splx(s); 368 369 return 0; 370 } 371 372 static uint32_t 373 pxamci_host_ocr(sdmmc_chipset_handle_t sch) 374 { 375 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 376 int rv; 377 378 if (__predict_true(sc->sc_tag.get_ocr != NULL)) { 379 rv = (*sc->sc_tag.get_ocr)(sc->sc_tag.cookie); 380 return rv; 381 } 382 383 DPRINTF(0,("%s: driver lacks get_ocr() function.\n", 384 device_xname(sc->sc_dev))); 385 return ENXIO; 386 } 387 388 static int 389 pxamci_host_maxblklen(sdmmc_chipset_handle_t sch) 390 { 391 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 392 393 return sc->sc_maxblklen; 394 } 395 396 static int 397 pxamci_card_detect(sdmmc_chipset_handle_t sch) 398 { 399 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 400 401 if (__predict_true(sc->sc_tag.card_detect != NULL)) { 402 return (*sc->sc_tag.card_detect)(sc->sc_tag.cookie); 403 } 404 405 DPRINTF(0,("%s: driver lacks card_detect() function.\n", 406 device_xname(sc->sc_dev))); 407 return 1; /* always detect */ 408 } 409 410 static int 411 pxamci_write_protect(sdmmc_chipset_handle_t sch) 412 { 413 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 414 415 if (__predict_true(sc->sc_tag.write_protect != NULL)) { 416 return (*sc->sc_tag.write_protect)(sc->sc_tag.cookie); 417 } 418 419 DPRINTF(0,("%s: driver lacks write_protect() function.\n", 420 device_xname(sc->sc_dev))); 421 return 0; /* non-protect */ 422 } 423 424 /* 425 * Set or change SD bus voltage and enable or disable SD bus power. 426 * Return zero on success. 427 */ 428 static int 429 pxamci_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 430 { 431 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 432 433 /* 434 * Bus power management is beyond control of the SD/SDIO/MMC 435 * block of the PXA2xx processors, so we have to hand this 436 * task off to the attachment driver. 437 */ 438 if (__predict_true(sc->sc_tag.set_power != NULL)) { 439 return (*sc->sc_tag.set_power)(sc->sc_tag.cookie, ocr); 440 } 441 442 DPRINTF(0,("%s: driver lacks set_power() function\n", 443 device_xname(sc->sc_dev))); 444 return ENXIO; 445 } 446 447 /* 448 * Set or change MMCLK frequency or disable the MMC clock. 449 * Return zero on success. 450 */ 451 static int 452 pxamci_bus_clock(sdmmc_chipset_handle_t sch, int freq) 453 { 454 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 455 int actfreq; 456 int div; 457 int rv = 0; 458 int s; 459 460 s = splsdmmc(); 461 462 /* 463 * Stop MMC clock before changing the frequency. 464 */ 465 pxamci_stop_clock(sc); 466 467 /* Just stop the clock. */ 468 if (freq == 0) 469 goto out; 470 471 /* 472 * PXA27x Errata... 473 * 474 * <snip> 475 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps 476 * 477 * SD/SDIO controller can only support up to 9.75 Mbps data 478 * transfer rate for SDIO card. 479 * </snip> 480 * 481 * If we don't limit the frequency, CRC errors will be 482 * reported by the controller after we set the bus speed. 483 * XXX slow down incrementally. 484 */ 485 if (CPU_IS_PXA270) { 486 if (freq > 9750) { 487 freq = 9750; 488 } 489 } 490 491 /* 492 * Pick the smallest divider that produces a frequency not 493 * more than `freq' KHz. 494 */ 495 actfreq = sc->sc_clkmax; 496 for (div = 0; div < 7; actfreq /= 2, div++) { 497 if (actfreq <= freq) 498 break; 499 } 500 if (div == 7) { 501 aprint_error_dev(sc->sc_dev, 502 "unsupported bus frequency of %d KHz\n", freq); 503 rv = 1; 504 goto out; 505 } 506 507 DPRINTF(1,("%s: freq = %d, actfreq = %d, div = %d\n", 508 device_xname(sc->sc_dev), freq, actfreq, div)); 509 510 sc->sc_clkbase = actfreq; 511 sc->sc_clkrt = div; 512 513 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 514 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 515 516 out: 517 splx(s); 518 519 return rv; 520 } 521 522 static int 523 pxamci_bus_width(sdmmc_chipset_handle_t sch, int width) 524 { 525 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 526 int rv = 0; 527 int s; 528 529 s = splsdmmc(); 530 531 switch (width) { 532 case 1: 533 break; 534 case 4: 535 if (CPU_IS_PXA270) 536 break; 537 /*FALLTHROUGH*/ 538 default: 539 DPRINTF(0,("%s: unsupported bus width (%d)\n", 540 device_xname(sc->sc_dev), width)); 541 rv = 1; 542 goto out; 543 } 544 545 sc->sc_buswidth = width; 546 547 out: 548 splx(s); 549 550 return rv; 551 } 552 553 static int 554 pxamci_bus_rod(sdmmc_chipset_handle_t sch, int on) 555 { 556 557 /* not support */ 558 return -1; 559 } 560 561 static void 562 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 563 { 564 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 565 uint32_t cmdat; 566 int error; 567 int timo; 568 int s; 569 570 DPRINTF(1,("%s: start cmd %d arg=%#x data=%p dlen=%d flags=%#x\n", 571 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_arg, cmd->c_data, 572 cmd->c_datalen, cmd->c_flags)); 573 574 s = splsdmmc(); 575 576 /* Stop the bus clock (MMCLK). [15.8.3] */ 577 pxamci_stop_clock(sc); 578 579 /* Set the command and argument. */ 580 CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode & CMD_MASK); 581 CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & ARGH_MASK); 582 CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & ARGL_MASK); 583 584 /* Response type */ 585 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 586 cmdat = CMDAT_RESPONSE_FORMAT_NO; 587 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 588 cmdat = CMDAT_RESPONSE_FORMAT_R2; 589 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 590 cmdat = CMDAT_RESPONSE_FORMAT_R3; 591 else 592 cmdat = CMDAT_RESPONSE_FORMAT_R1; 593 594 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 595 cmdat |= CMDAT_BUSY; 596 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 597 cmdat |= CMDAT_WRITE; 598 if (sc->sc_buswidth == 4) 599 cmdat |= CMDAT_SD_4DAT; 600 601 /* Fragment the data into proper blocks. */ 602 if (cmd->c_datalen > 0) { 603 int blklen = MIN(cmd->c_datalen, cmd->c_blklen); 604 int numblk = cmd->c_datalen / blklen; 605 606 if (cmd->c_datalen % blklen > 0) { 607 /* XXX: Split this command. (1.7.4) */ 608 aprint_error_dev(sc->sc_dev, 609 "data not a multiple of %u bytes\n", blklen); 610 cmd->c_error = EINVAL; 611 goto out; 612 } 613 614 /* Check limit imposed by block count. */ 615 if (numblk > NOB_MASK) { 616 aprint_error_dev(sc->sc_dev, "too much data\n"); 617 cmd->c_error = EINVAL; 618 goto out; 619 } 620 621 CSR_WRITE_4(sc, MMC_BLKLEN, blklen); 622 CSR_WRITE_4(sc, MMC_NOB, numblk); 623 CSR_WRITE_4(sc, MMC_RDTO, RDTO_MASK); 624 625 cmdat |= CMDAT_DATA_EN; 626 627 /* setting DMA */ 628 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 629 && DMA_ALIGNED(cmd->c_data)) { 630 struct dmac_xfer_desc *dx_desc; 631 632 DPRINTF(1,("%s: using DMA\n",device_xname(sc->sc_dev))); 633 634 cmdat |= CMDAT_MMC_DMA_EN; 635 636 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 637 dx_desc = &sc->sc_rxdx->dx_desc[DMAC_DESC_DST]; 638 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 639 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 640 error = pxa2x0_dmac_start_xfer(sc->sc_rxdx); 641 } else { 642 dx_desc = &sc->sc_txdx->dx_desc[DMAC_DESC_SRC]; 643 dx_desc->xd_nsegs = cmd->c_dmamap->dm_nsegs; 644 dx_desc->xd_dma_segs = cmd->c_dmamap->dm_segs; 645 /* workaround for erratum #91 */ 646 error = 0; 647 if (!CPU_IS_PXA270) { 648 error = 649 pxa2x0_dmac_start_xfer(sc->sc_txdx); 650 } 651 } 652 if (error) { 653 aprint_error_dev(sc->sc_dev, 654 "couldn't start dma xfer. (error=%d)\n", 655 error); 656 cmd->c_error = EIO; 657 goto err; 658 } 659 } else { 660 DPRINTF(1,("%s: using PIO\n",device_xname(sc->sc_dev))); 661 662 cmd->c_resid = cmd->c_datalen; 663 cmd->c_buf = cmd->c_data; 664 665 pxamci_enable_intr(sc, MMC_I_RXFIFO_RD_REQ 666 | MMC_I_TXFIFO_WR_REQ 667 | MMC_I_DAT_ERR); 668 } 669 } 670 671 sc->sc_cmd = cmd; 672 673 /* 674 * "After reset, the MMC card must be initialized by sending 675 * 80 clocks to it on the MMCLK signal." [15.4.3.2] 676 */ 677 if (!ISSET(sc->sc_flags, PMF_CARDINITED)) { 678 DPRINTF(1,("%s: first command\n", device_xname(sc->sc_dev))); 679 cmdat |= CMDAT_INIT; 680 SET(sc->sc_flags, PMF_CARDINITED); 681 } 682 683 /* Begin the transfer and start the bus clock. */ 684 CSR_WRITE_4(sc, MMC_CMDAT, cmdat); 685 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 686 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); 687 688 /* Wait for it to complete */ 689 pxamci_enable_intr(sc, MMC_I_END_CMD_RES|MMC_I_RES_ERR); 690 for (timo = EXECCMD_TIMO; (sc->sc_cmd == cmd) && (timo > 0); timo--) { 691 tsleep(sc, PWAIT, "mmcmd", hz); 692 } 693 694 /* If it completed in time, SCF_ITSDONE is already set. */ 695 if (sc->sc_cmd == cmd) { 696 cmd->c_error = ETIMEDOUT; 697 err: 698 SET(cmd->c_flags, SCF_ITSDONE); 699 sc->sc_cmd = NULL; 700 goto out; 701 } 702 703 out: 704 splx(s); 705 706 DPRINTF(1,("%s: cmd %d done (flags=%08x error=%d)\n", 707 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 708 } 709 710 static void 711 pxamci_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 712 { 713 struct pxamci_softc *sc = (struct pxamci_softc *)sch; 714 715 if (enable) { 716 pxamci_enable_intr(sc, MMC_I_SDIO_INT); 717 } else { 718 pxamci_disable_intr(sc, MMC_I_SDIO_INT); 719 } 720 } 721 722 static void 723 pxamci_card_intr_ack(sdmmc_chipset_handle_t sch) 724 { 725 726 /* Nothing to do */ 727 } 728 729 static void 730 pxamci_stop_clock(struct pxamci_softc *sc) 731 { 732 int timo = STOPCLK_TIMO; 733 734 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { 735 CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF); 736 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP); 737 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) 738 && (timo-- > 0)) { 739 tsleep(sc, PWAIT, "mmclk", hz); 740 } 741 } 742 if (timo == 0) 743 aprint_error_dev(sc->sc_dev, "clock stop timeout\n"); 744 } 745 746 /* 747 * SD/MMC controller interrput handler 748 */ 749 static int 750 pxamci_intr(void *arg) 751 { 752 struct pxamci_softc *sc = arg; 753 int status; 754 #ifdef PXAMCI_DEBUG 755 int ostatus; 756 757 ostatus = 758 #endif 759 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); 760 DPRINTF(10,("%s: intr status = %08x\n", device_xname(sc->sc_dev), 761 status)); 762 763 /* 764 * Notify the process waiting in pxamci_clock_stop() when 765 * the clock has really stopped. 766 */ 767 if (ISSET(status, MMC_I_CLK_IS_OFF)) { 768 DPRINTF(2,("%s: clock is now off\n", device_xname(sc->sc_dev))); 769 wakeup(sc); 770 pxamci_disable_intr(sc, MMC_I_CLK_IS_OFF); 771 CLR(status, MMC_I_CLK_IS_OFF); 772 } 773 774 if (sc->sc_cmd == NULL) 775 goto end; 776 777 if (ISSET(status, MMC_I_RES_ERR)) { 778 DPRINTF(9, ("%s: handling MMC_I_RES_ERR\n", 779 device_xname(sc->sc_dev))); 780 pxamci_disable_intr(sc, MMC_I_RES_ERR); 781 CLR(status, MMC_I_RES_ERR|MMC_I_END_CMD_RES); 782 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 783 && (sc->sc_cmd->c_datalen > 0) 784 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 785 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 786 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 787 } else { 788 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 789 } 790 } 791 sc->sc_cmd->c_error = ENOEXEC; 792 pxamci_intr_done(sc); 793 goto end; 794 } 795 796 if (ISSET(status, MMC_I_END_CMD_RES)) { 797 DPRINTF(9,("%s: handling MMC_I_END_CMD_RES\n", 798 device_xname(sc->sc_dev))); 799 pxamci_intr_cmd(sc); 800 pxamci_disable_intr(sc, MMC_I_END_CMD_RES); 801 CLR(status, MMC_I_END_CMD_RES); 802 /* ignore programming done condition */ 803 if (ISSET(status, MMC_I_PRG_DONE)) { 804 pxamci_disable_intr(sc, MMC_I_PRG_DONE); 805 CLR(status, MMC_I_PRG_DONE); 806 } 807 if (sc->sc_cmd == NULL) 808 goto end; 809 } 810 811 if (ISSET(status, MMC_I_DAT_ERR)) { 812 DPRINTF(9, ("%s: handling MMC_I_DAT_ERR\n", 813 device_xname(sc->sc_dev))); 814 sc->sc_cmd->c_error = EIO; 815 pxamci_intr_done(sc); 816 pxamci_disable_intr(sc, MMC_I_DAT_ERR); 817 CLR(status, MMC_I_DAT_ERR); 818 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 819 && DMA_ALIGNED(sc->sc_cmd->c_data)) { 820 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 821 pxa2x0_dmac_abort_xfer(sc->sc_rxdx); 822 } else { 823 pxa2x0_dmac_abort_xfer(sc->sc_txdx); 824 } 825 } 826 /* ignore transmission done condition */ 827 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 828 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 829 CLR(status, MMC_I_DATA_TRAN_DONE); 830 } 831 goto end; 832 } 833 834 if (ISSET(status, MMC_I_DATA_TRAN_DONE)) { 835 DPRINTF(9,("%s: handling MMC_I_DATA_TRAN_DONE\n", 836 device_xname(sc->sc_dev))); 837 pxamci_intr_done(sc); 838 pxamci_disable_intr(sc, MMC_I_DATA_TRAN_DONE); 839 CLR(status, MMC_I_DATA_TRAN_DONE); 840 } 841 842 if (ISSET(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ)) { 843 DPRINTF(10,("%s: handling MMC_I_xxFIFO_xx_REQ\n", 844 device_xname(sc->sc_dev))); 845 pxamci_intr_data(sc); 846 CLR(status, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ); 847 } 848 849 if (ISSET(status, STAT_SDIO_INT)) { 850 DPRINTF(9,("%s: handling STAT_SDIO_INT\n", 851 device_xname(sc->sc_dev))); 852 sdmmc_card_intr(sc->sc_sdmmc); 853 CLR(status, STAT_SDIO_INT); 854 } 855 856 end: 857 /* Avoid further unhandled interrupts. */ 858 if (status != 0) { 859 pxamci_disable_intr(sc, status); 860 #ifdef PXAMCI_DEBUG 861 aprint_error_dev(sc->sc_dev, 862 "unhandled interrupt 0x%x out of 0x%x\n", status, ostatus); 863 #endif 864 } 865 return 1; 866 } 867 868 static void 869 pxamci_intr_cmd(struct pxamci_softc *sc) 870 { 871 struct sdmmc_command *cmd = sc->sc_cmd; 872 uint32_t status; 873 int error; 874 int i; 875 876 KASSERT(sc->sc_cmd != NULL); 877 878 #define STAT_ERR (STAT_READ_TIME_OUT \ 879 | STAT_TIMEOUT_RESPONSE \ 880 | STAT_CRC_WRITE_ERROR \ 881 | STAT_CRC_READ_ERROR \ 882 | STAT_SPI_READ_ERROR_TOKEN) 883 884 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 885 for (i = 3; i >= 0; i--) { 886 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 887 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 888 cmd->c_resp[i] = (h << 16) | l; 889 } 890 cmd->c_error = 0; 891 } else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 892 /* 893 * Grrr... The processor manual is not clear about 894 * the layout of the response FIFO. It just states 895 * that the FIFO is 16 bits wide, has a depth of 8, 896 * and that the CRC is not copied into the FIFO. 897 * 898 * A 16-bit word in the FIFO is filled from highest 899 * to lowest bit as the response comes in. The two 900 * start bits and the 6 command index bits are thus 901 * stored in the upper 8 bits of the first 16-bit 902 * word that we read back from the FIFO. 903 * 904 * Since the sdmmc(4) framework expects the host 905 * controller to discard the first 8 bits of the 906 * response, what we must do is discard the upper 907 * byte of the first 16-bit word. 908 */ 909 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; 910 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; 911 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; 912 cmd->c_resp[0] = (h << 24) | (m << 8) | (l >> 8); 913 for (i = 1; i < 4; i++) 914 cmd->c_resp[i] = 0; 915 cmd->c_error = 0; 916 } 917 918 status = CSR_READ_4(sc, MMC_STAT); 919 920 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 921 CLR(status, STAT_TIMEOUT_RESPONSE); 922 923 /* XXX only for R6, not for R2 */ 924 if (!ISSET(cmd->c_flags, SCF_RSP_IDX)) 925 CLR(status, STAT_RES_CRC_ERR); 926 927 if (ISSET(status, STAT_TIMEOUT_RESPONSE)) 928 cmd->c_error = ETIMEDOUT; 929 else if (ISSET(status, STAT_RES_CRC_ERR) 930 && ISSET(cmd->c_flags, SCF_RSP_CRC) 931 && CPU_IS_PXA270) { 932 /* workaround for erratum #42 */ 933 if (ISSET(cmd->c_flags, SCF_RSP_136) 934 && (cmd->c_resp[0] & 0x80000000U)) { 935 DPRINTF(1,("%s: ignore CRC error\n", 936 device_xname(sc->sc_dev))); 937 } else 938 cmd->c_error = EIO; 939 } else if (ISSET(status, STAT_ERR)) 940 cmd->c_error = EIO; 941 942 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 943 if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA) 944 && DMA_ALIGNED(cmd->c_data)) { 945 /* workaround for erratum #91 */ 946 if (CPU_IS_PXA270 947 && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 948 error = pxa2x0_dmac_start_xfer(sc->sc_txdx); 949 if (error) { 950 aprint_error_dev(sc->sc_dev, 951 "couldn't start dma xfer." 952 " (error=%d)\n", error); 953 cmd->c_error = EIO; 954 pxamci_intr_done(sc); 955 return; 956 } 957 } 958 pxamci_enable_intr(sc, 959 MMC_I_DATA_TRAN_DONE|MMC_I_DAT_ERR); 960 } 961 } else { 962 pxamci_intr_done(sc); 963 } 964 } 965 966 static void 967 pxamci_intr_data(struct pxamci_softc *sc) 968 { 969 struct sdmmc_command *cmd = sc->sc_cmd; 970 int intr; 971 int n; 972 973 DPRINTF(10,("%s: pxamci_intr_data: cmd = %p, resid = %d\n", 974 device_xname(sc->sc_dev), cmd, cmd->c_resid)); 975 976 n = MIN(32, cmd->c_resid); 977 cmd->c_resid -= n; 978 979 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 980 intr = MMC_I_RXFIFO_RD_REQ; 981 while (n-- > 0) 982 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); 983 } else { 984 int short_xfer = n < 32; 985 986 intr = MMC_I_TXFIFO_WR_REQ; 987 while (n-- > 0) 988 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); 989 if (short_xfer) 990 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 991 } 992 993 if (cmd->c_resid > 0) { 994 pxamci_enable_intr(sc, intr); 995 } else { 996 pxamci_disable_intr(sc, intr); 997 pxamci_enable_intr(sc, MMC_I_DATA_TRAN_DONE); 998 } 999 } 1000 1001 /* 1002 * Wake up the process sleeping in pxamci_exec_command(). 1003 */ 1004 static void 1005 pxamci_intr_done(struct pxamci_softc *sc) 1006 { 1007 1008 DPRINTF(1,("%s: pxamci_intr_done: mmc status = %#x\n", 1009 device_xname(sc->sc_dev), CSR_READ_4(sc, MMC_STAT))); 1010 1011 pxamci_disable_intr(sc, MMC_I_TXFIFO_WR_REQ|MMC_I_RXFIFO_RD_REQ| 1012 MMC_I_DATA_TRAN_DONE|MMC_I_END_CMD_RES|MMC_I_RES_ERR|MMC_I_DAT_ERR); 1013 SET(sc->sc_cmd->c_flags, SCF_ITSDONE); 1014 sc->sc_cmd = NULL; 1015 wakeup(sc); 1016 } 1017 1018 static void 1019 pxamci_dmac_iintr(struct dmac_xfer *dx, int status) 1020 { 1021 struct pxamci_softc *sc = dx->dx_cookie; 1022 1023 DPRINTF(1,("%s: pxamci_dmac_iintr: status = %#x\n", 1024 device_xname(sc->sc_dev), status)); 1025 1026 if (status) { 1027 aprint_error_dev(sc->sc_dev, "pxamci_dmac_iintr: " 1028 "non-zero completion status %d\n", status); 1029 } 1030 } 1031 1032 static void 1033 pxamci_dmac_ointr(struct dmac_xfer *dx, int status) 1034 { 1035 struct pxamci_softc *sc = dx->dx_cookie; 1036 1037 DPRINTF(1,("%s: pxamci_dmac_ointr: status = %#x\n", 1038 device_xname(sc->sc_dev), status)); 1039 1040 if (status == 0) { 1041 if (sc->sc_cmd != NULL && (sc->sc_cmd->c_datalen & 31) != 0) { 1042 CSR_WRITE_4(sc, MMC_PRTBUF, 1); 1043 } 1044 } else { 1045 aprint_error_dev(sc->sc_dev, "pxamci_dmac_ointr: " 1046 "non-zero completion status %d\n", status); 1047 } 1048 } 1049
Indexes created Mon Sep 29 15:09:53 GMT 2025