pxa2x0_rtc.c revision 1.1
1 /* $NetBSD: pxa2x0_rtc.c,v 1.1 2007/02/25 13:46:40 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 2007 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_rtc.c,v 1.1 2007/02/25 13:46:40 nonaka Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 32 #include <dev/clock_subr.h> 33 34 #include <machine/bus.h> 35 36 #include <arm/xscale/pxa2x0cpu.h> 37 #include <arm/xscale/pxa2x0reg.h> 38 #include <arm/xscale/pxa2x0var.h> 39 40 #ifdef PXARTC_DEBUG 41 #define DPRINTF(s) printf s 42 #else 43 #define DPRINTF(s) 44 #endif 45 46 struct pxartc_softc { 47 struct device sc_dev; 48 bus_space_tag_t sc_iot; 49 bus_space_handle_t sc_ioh; 50 51 struct todr_chip_handle sc_todr; 52 53 int sc_flags; 54 #define FLAG_WRISTWATCH (1 << 0) 55 }; 56 57 static int pxartc_match(struct device *, struct cfdata *, void *); 58 static void pxartc_attach(struct device *, struct device *, void *); 59 60 CFATTACH_DECL(pxartc, sizeof(struct pxartc_softc), 61 pxartc_match, pxartc_attach, NULL, NULL); 62 63 /* todr(9) interface */ 64 static int pxartc_todr_gettime(todr_chip_handle_t, volatile struct timeval *); 65 static int pxartc_todr_settime(todr_chip_handle_t, volatile struct timeval *); 66 67 static int pxartc_wristwatch_read(struct pxartc_softc *,struct clock_ymdhms *); 68 static int pxartc_wristwatch_write(struct pxartc_softc *,struct clock_ymdhms *); 69 70 static int 71 pxartc_match(struct device *parent, struct cfdata *cf, void *aux) 72 { 73 struct pxaip_attach_args *pxa = aux; 74 75 if (pxa->pxa_size == PXA270_RTC_SIZE) { 76 if (!CPU_IS_PXA270) { 77 return 0; 78 } 79 } else { 80 pxa->pxa_size = PXA250_RTC_SIZE; 81 } 82 83 return 1; 84 } 85 86 static void 87 pxartc_attach(struct device *parent, struct device *self, void *aux) 88 { 89 struct pxartc_softc *sc = (struct pxartc_softc *)self; 90 struct pxaip_attach_args *pxa = aux; 91 92 sc->sc_iot = pxa->pxa_iot; 93 94 aprint_normal(": PXA2x0 Real-time Clock\n"); 95 96 if (bus_space_map(sc->sc_iot, PXA2X0_RTC_BASE, pxa->pxa_size, 0, 97 &sc->sc_ioh)) { 98 aprint_error("%s: couldn't map registers\n", 99 sc->sc_dev.dv_xname); 100 return; 101 } 102 103 if (pxa->pxa_size == PXA270_RTC_SIZE) { 104 aprint_normal("%s: using wristwatch register\n", 105 sc->sc_dev.dv_xname); 106 sc->sc_flags |= FLAG_WRISTWATCH; 107 } 108 109 sc->sc_todr.cookie = sc; 110 sc->sc_todr.todr_gettime = pxartc_todr_gettime; 111 sc->sc_todr.todr_settime = pxartc_todr_settime; 112 sc->sc_todr.todr_setwen = NULL; 113 114 todr_attach(&sc->sc_todr); 115 } 116 117 static int 118 pxartc_todr_gettime(todr_chip_handle_t ch, volatile struct timeval *tv) 119 { 120 struct pxartc_softc *sc = ch->cookie; 121 struct clock_ymdhms dt; 122 123 if ((sc->sc_flags & FLAG_WRISTWATCH) == 0) { 124 tv->tv_sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR); 125 tv->tv_usec = 0; 126 DPRINTF(("%s: RCNR = %08lx\n", sc->sc_dev.dv_xname,tv->tv_sec)); 127 #ifdef PXARTC_DEBUG 128 clock_secs_to_ymdhms(tv->tv_sec, &dt); 129 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 130 sc->sc_dev.dv_xname, 131 dt.dt_year, dt.dt_mon, dt.dt_day, 132 dt.dt_hour, dt.dt_min, dt.dt_sec)); 133 #endif 134 return 0; 135 } 136 137 memset(&dt, 0, sizeof(dt)); 138 139 if (pxartc_wristwatch_read(sc, &dt) == 0) 140 return -1; 141 142 tv->tv_sec = clock_ymdhms_to_secs(&dt); 143 tv->tv_usec = 0; 144 return 0; 145 } 146 147 static int 148 pxartc_todr_settime(todr_chip_handle_t ch, volatile struct timeval *tv) 149 { 150 struct pxartc_softc *sc = ch->cookie; 151 struct clock_ymdhms dt; 152 153 if ((sc->sc_flags & FLAG_WRISTWATCH) == 0) { 154 #ifdef PXARTC_DEBUG 155 DPRINTF(("%s: RCNR = %08lx\n", sc->sc_dev.dv_xname,tv->tv_sec)); 156 clock_secs_to_ymdhms(tv->tv_sec, &dt); 157 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 158 sc->sc_dev.dv_xname, 159 dt.dt_year, dt.dt_mon, dt.dt_day, 160 dt.dt_hour, dt.dt_min, dt.dt_sec)); 161 #endif 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR, tv->tv_sec); 163 #ifdef PXARTC_DEBUG 164 { 165 uint32_t cntr; 166 delay(1); 167 cntr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR); 168 DPRINTF(("%s: new RCNR = %08x\n", sc->sc_dev.dv_xname, cntr)); 169 clock_secs_to_ymdhms(cntr, &dt); 170 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 171 sc->sc_dev.dv_xname, 172 dt.dt_year, dt.dt_mon, dt.dt_day, 173 dt.dt_hour, dt.dt_min, dt.dt_sec)); 174 } 175 #endif 176 return 0; 177 } 178 179 clock_secs_to_ymdhms(tv->tv_sec, &dt); 180 181 if (pxartc_wristwatch_write(sc, &dt) == 0) 182 return -1; 183 return 0; 184 } 185 186 static int 187 pxartc_wristwatch_read(struct pxartc_softc *sc, struct clock_ymdhms *dt) 188 { 189 uint32_t dayr, yearr; 190 int s; 191 192 DPRINTF(("%s: pxartc_wristwatch_read()\n", sc->sc_dev.dv_xname)); 193 194 s = splhigh(); 195 dayr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR); 196 yearr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR); 197 splx(s); 198 199 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", sc->sc_dev.dv_xname, 200 dayr, yearr)); 201 202 dt->dt_sec = (dayr >> RDCR_SECOND_SHIFT) & RDCR_SECOND_MASK; 203 dt->dt_min = (dayr >> RDCR_MINUTE_SHIFT) & RDCR_MINUTE_MASK; 204 dt->dt_hour = (dayr >> RDCR_HOUR_SHIFT) & RDCR_HOUR_MASK; 205 dt->dt_day = (yearr >> RYCR_DOM_SHIFT) & RYCR_DOM_MASK; 206 dt->dt_mon = (yearr >> RYCR_MONTH_SHIFT) & RYCR_MONTH_MASK; 207 dt->dt_year = (yearr >> RYCR_YEAR_SHIFT) & RYCR_YEAR_MASK; 208 209 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", sc->sc_dev.dv_xname, 210 dt->dt_year, dt->dt_mon, dt->dt_day, 211 dt->dt_hour, dt->dt_min, dt->dt_sec)); 212 213 return 1; 214 } 215 216 static int 217 pxartc_wristwatch_write(struct pxartc_softc *sc, struct clock_ymdhms *dt) 218 { 219 uint32_t dayr, yearr; 220 uint32_t wom; /* week of month: 1=first week of month */ 221 int s; 222 223 DPRINTF(("%s: pxartc_wristwatch_write()\n", sc->sc_dev.dv_xname)); 224 225 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", sc->sc_dev.dv_xname, 226 dt->dt_year, dt->dt_mon, dt->dt_day, 227 dt->dt_hour, dt->dt_min, dt->dt_sec)); 228 229 dayr = (dt->dt_sec & RDCR_SECOND_MASK) << RDCR_SECOND_SHIFT; 230 dayr |= (dt->dt_min & RDCR_MINUTE_MASK) << RDCR_MINUTE_SHIFT; 231 dayr |= (dt->dt_hour & RDCR_HOUR_MASK) << RDCR_HOUR_SHIFT; 232 dayr |= ((dt->dt_wday + 1) & RDCR_DOW_MASK) << RDCR_DOW_SHIFT; 233 wom = ((dt->dt_day - 1 + 6 - dt->dt_wday) / 7) + 1; 234 dayr |= (wom & RDCR_WOM_MASK) << RDCR_WOM_SHIFT; 235 yearr = (dt->dt_day & RYCR_DOM_MASK) << RYCR_DOM_SHIFT; 236 yearr |= (dt->dt_mon & RYCR_MONTH_MASK) << RYCR_MONTH_SHIFT; 237 yearr |= (dt->dt_year & RYCR_YEAR_MASK) << RYCR_YEAR_SHIFT; 238 239 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", sc->sc_dev.dv_xname, 240 dayr, yearr)); 241 242 /* 243 * We must write RYCR register before write RDCR register. 244 * 245 * See PXA270 Processor Family Developer's Manual p.946 246 * 21.4.2.3.1 Writing RDCR and RYCR Counter Registers with Valid Data. 247 */ 248 s = splhigh(); 249 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR, yearr); 250 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR, dayr); 251 splx(s); 252 253 #ifdef PXARTC_DEBUG 254 { 255 struct clock_ymdhms dummy; 256 pxartc_wristwatch_read(sc, &dummy); 257 } 258 #endif 259 260 return 1; 261 } 262
Indexes created Thu Oct 02 07:10:07 GMT 2025