pxa2x0_rtc.c revision 1.6.38.1
1 /* $NetBSD: pxa2x0_rtc.c,v 1.6.38.1 2020/04/08 14:07:31 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2007 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_rtc.c,v 1.6.38.1 2020/04/08 14:07:31 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 32 #include <dev/clock_subr.h> 33 34 #include <sys/bus.h> 35 36 #include <arm/xscale/pxa2x0cpu.h> 37 #include <arm/xscale/pxa2x0reg.h> 38 #include <arm/xscale/pxa2x0var.h> 39 40 #ifdef PXARTC_DEBUG 41 #define DPRINTF(s) printf s 42 #else 43 #define DPRINTF(s) 44 #endif 45 46 struct pxartc_softc { 47 device_t sc_dev; 48 bus_space_tag_t sc_iot; 49 bus_space_handle_t sc_ioh; 50 51 struct todr_chip_handle sc_todr; 52 53 int sc_flags; 54 #define FLAG_WRISTWATCH (1 << 0) 55 }; 56 57 static int pxartc_match(device_t, cfdata_t, void *); 58 static void pxartc_attach(device_t, device_t, void *); 59 60 CFATTACH_DECL_NEW(pxartc, sizeof(struct pxartc_softc), 61 pxartc_match, pxartc_attach, NULL, NULL); 62 63 /* todr(9) interface */ 64 static int pxartc_todr_gettime(todr_chip_handle_t, struct timeval *); 65 static int pxartc_todr_settime(todr_chip_handle_t, struct timeval *); 66 static int pxartc_wristwatch_gettime(todr_chip_handle_t, struct clock_ymdhms *); 67 static int pxartc_wristwatch_settime(todr_chip_handle_t, struct clock_ymdhms *); 68 69 static int 70 pxartc_match(device_t parent, cfdata_t cf, void *aux) 71 { 72 struct pxaip_attach_args *pxa = aux; 73 74 if (strcmp(pxa->pxa_name, cf->cf_name) != 0) 75 return 0; 76 77 if (pxa->pxa_size == 0) { 78 pxa->pxa_size = 79 CPU_IS_PXA270 ? PXA270_RTC_SIZE : PXA250_RTC_SIZE; 80 } 81 return 1; 82 } 83 84 static void 85 pxartc_attach(device_t parent, device_t self, void *aux) 86 { 87 struct pxartc_softc *sc = device_private(self); 88 struct pxaip_attach_args *pxa = aux; 89 90 sc->sc_dev = self; 91 sc->sc_iot = pxa->pxa_iot; 92 93 aprint_normal(": Real-time Clock\n"); 94 95 if (bus_space_map(sc->sc_iot, pxa->pxa_addr, pxa->pxa_size, 0, 96 &sc->sc_ioh)) { 97 aprint_error("%s: couldn't map registers\n", 98 device_xname(sc->sc_dev)); 99 return; 100 } 101 102 memset(&sc->sc_todr, 0, sizeof(sc->sc_todr)); 103 sc->sc_todr.cookie = sc; 104 if (pxa->pxa_size == PXA270_RTC_SIZE) { 105 aprint_normal("%s: using wristwatch register\n", 106 device_xname(sc->sc_dev)); 107 sc->sc_flags |= FLAG_WRISTWATCH; 108 sc->sc_todr.todr_gettime_ymdhms = pxartc_wristwatch_gettime; 109 sc->sc_todr.todr_settime_ymdhms = pxartc_wristwatch_settime; 110 } else { 111 sc->sc_todr.todr_gettime = pxartc_todr_gettime; 112 sc->sc_todr.todr_settime = pxartc_todr_settime; 113 } 114 115 todr_attach(&sc->sc_todr); 116 } 117 118 static int 119 pxartc_todr_gettime(todr_chip_handle_t ch, struct timeval *tv) 120 { 121 struct pxartc_softc *sc = ch->cookie; 122 123 tv->tv_sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR); 124 tv->tv_usec = 0; 125 #ifdef PXARTC_DEBUG 126 DPRINTF(("%s: RCNR = %08llx\n", device_xname(sc->sc_dev), 127 tv->tv_sec)); 128 clock_secs_to_ymdhms(tv->tv_sec, &dt); 129 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 130 device_xname(sc->sc_dev), 131 dt.dt_year, dt.dt_mon, dt.dt_day, 132 dt.dt_hour, dt.dt_min, dt.dt_sec)); 133 #endif 134 return 0; 135 } 136 137 static int 138 pxartc_todr_settime(todr_chip_handle_t ch, struct timeval *tv) 139 { 140 struct pxartc_softc *sc = ch->cookie; 141 142 #ifdef PXARTC_DEBUG 143 DPRINTF(("%s: RCNR = %08llx\n", device_xname(sc->sc_dev), 144 tv->tv_sec)); 145 clock_secs_to_ymdhms(tv->tv_sec, &dt); 146 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 147 device_xname(sc->sc_dev), 148 dt.dt_year, dt.dt_mon, dt.dt_day, 149 dt.dt_hour, dt.dt_min, dt.dt_sec)); 150 #endif 151 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR, tv->tv_sec); 152 #ifdef PXARTC_DEBUG 153 { 154 uint32_t cntr; 155 delay(1); 156 cntr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR); 157 DPRINTF(("%s: new RCNR = %08x\n", device_xname(sc->sc_dev), 158 cntr)); 159 clock_secs_to_ymdhms(cntr, &dt); 160 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 161 device_xname(sc->sc_dev), 162 dt.dt_year, dt.dt_mon, dt.dt_day, 163 dt.dt_hour, dt.dt_min, dt.dt_sec)); 164 } 165 #endif 166 return 0; 167 } 168 169 static int 170 pxartc_wristwatch_gettime(todr_chip_handle_t ch, struct clock_ymdhms *dt) 171 { 172 struct pxartc_softc *sc = ch->cookie; 173 uint32_t dayr, yearr; 174 int s; 175 176 DPRINTF(("%s: pxartc_wristwatch_gettime()\n", 177 device_xname(sc->sc_dev))); 178 179 s = splhigh(); 180 dayr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR); 181 yearr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR); 182 splx(s); 183 184 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", device_xname(sc->sc_dev), 185 dayr, yearr)); 186 187 dt->dt_sec = (dayr >> RDCR_SECOND_SHIFT) & RDCR_SECOND_MASK; 188 dt->dt_min = (dayr >> RDCR_MINUTE_SHIFT) & RDCR_MINUTE_MASK; 189 dt->dt_hour = (dayr >> RDCR_HOUR_SHIFT) & RDCR_HOUR_MASK; 190 dt->dt_day = (yearr >> RYCR_DOM_SHIFT) & RYCR_DOM_MASK; 191 dt->dt_mon = (yearr >> RYCR_MONTH_SHIFT) & RYCR_MONTH_MASK; 192 dt->dt_year = (yearr >> RYCR_YEAR_SHIFT) & RYCR_YEAR_MASK; 193 194 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 195 device_xname(sc->sc_dev), 196 dt->dt_year, dt->dt_mon, dt->dt_day, 197 dt->dt_hour, dt->dt_min, dt->dt_sec)); 198 199 return 0; 200 } 201 202 static int 203 pxartc_wristwatch_settime(todr_chip_handle_t ch, struct clock_ymdhms *dt) 204 { 205 struct pxartc_softc *sc = ch->cookie; 206 uint32_t dayr, yearr; 207 uint32_t wom; /* week of month: 1=first week of month */ 208 int s; 209 210 DPRINTF(("%s: pxartc_wristwatch_settime()\n", 211 device_xname(sc->sc_dev))); 212 213 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", 214 device_xname(sc->sc_dev), 215 dt->dt_year, dt->dt_mon, dt->dt_day, 216 dt->dt_hour, dt->dt_min, dt->dt_sec)); 217 218 dayr = (dt->dt_sec & RDCR_SECOND_MASK) << RDCR_SECOND_SHIFT; 219 dayr |= (dt->dt_min & RDCR_MINUTE_MASK) << RDCR_MINUTE_SHIFT; 220 dayr |= (dt->dt_hour & RDCR_HOUR_MASK) << RDCR_HOUR_SHIFT; 221 dayr |= ((dt->dt_wday + 1) & RDCR_DOW_MASK) << RDCR_DOW_SHIFT; 222 wom = ((dt->dt_day - 1 + 6 - dt->dt_wday) / 7) + 1; 223 dayr |= (wom & RDCR_WOM_MASK) << RDCR_WOM_SHIFT; 224 yearr = (dt->dt_day & RYCR_DOM_MASK) << RYCR_DOM_SHIFT; 225 yearr |= (dt->dt_mon & RYCR_MONTH_MASK) << RYCR_MONTH_SHIFT; 226 yearr |= (dt->dt_year & RYCR_YEAR_MASK) << RYCR_YEAR_SHIFT; 227 228 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", device_xname(sc->sc_dev), 229 dayr, yearr)); 230 231 /* 232 * We must write RYCR register before write RDCR register. 233 * 234 * See PXA270 Processor Family Developer's Manual p.946 235 * 21.4.2.3.1 Writing RDCR and RYCR Counter Registers with Valid Data. 236 */ 237 s = splhigh(); 238 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR, yearr); 239 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR, dayr); 240 splx(s); 241 242 #ifdef PXARTC_DEBUG 243 { 244 struct clock_ymdhms dummy; 245 pxartc_wristwatch_gettime(sc, &dummy); 246 } 247 #endif 248 249 return 0; 250 } 251
Indexes created Sat Oct 18 23:09:54 GMT 2025