pxa2x0cpu.h revision 1.1 1 1.1 bsh /* $NetBSD: pxa2x0cpu.h,v 1.1 2005/07/04 00:42:37 bsh Exp $ */
2 1.1 bsh
3 1.1 bsh /*
4 1.1 bsh * Copyright (c) 2005 Genetec Corporation. All rights reserved.
5 1.1 bsh * Written by Hiroyuki Bessho for Genetec Corporation.
6 1.1 bsh *
7 1.1 bsh * Redistribution and use in source and binary forms, with or without
8 1.1 bsh * modification, are permitted provided that the following conditions
9 1.1 bsh * are met:
10 1.1 bsh * 1. Redistributions of source code must retain the above copyright
11 1.1 bsh * notice, this list of conditions and the following disclaimer.
12 1.1 bsh * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 bsh * notice, this list of conditions and the following disclaimer in the
14 1.1 bsh * documentation and/or other materials provided with the distribution.
15 1.1 bsh * 3. The name of Genetec Corporation may not be used to endorse or
16 1.1 bsh * promote products derived from this software without specific prior
17 1.1 bsh * written permission.
18 1.1 bsh *
19 1.1 bsh * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
20 1.1 bsh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 bsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 bsh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
23 1.1 bsh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 bsh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 bsh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 bsh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 bsh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 bsh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 bsh * POSSIBILITY OF SUCH DAMAGE.
30 1.1 bsh *
31 1.1 bsh */
32 1.1 bsh
33 1.1 bsh /*
34 1.1 bsh * In kernel config file, users can have options
35 1.1 bsh * CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
36 1.1 bsh *
37 1.1 bsh * If kernel is configured to support PXA250 and PXA270, CPU type is
38 1.1 bsh * determined run-time by reading a co-processor register.
39 1.1 bsh */
40 1.1 bsh
41 1.1 bsh #ifndef _ARM_XSCALE_PXA2X0CPU_H
42 1.1 bsh #define _ARM_XSCALE_PXA2X0CPU_H
43 1.1 bsh
44 1.1 bsh #ifdef _KERNEL_OPT
45 1.1 bsh #include "opt_cputypes.h" /* User's choice of CPU */
46 1.1 bsh #endif
47 1.1 bsh
48 1.1 bsh #if !defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
49 1.1 bsh #error neither CPU_XSCALE_PXA250 nor CPU_XSCALE_PXA270 is defined.
50 1.1 bsh #endif
51 1.1 bsh
52 1.1 bsh #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
53 1.1 bsh # define __CPU_XSCALE_PXA2XX
54 1.1 bsh #endif
55 1.1 bsh
56 1.1 bsh #define CPU_ID_PXA_MASK (CPU_ID_IMPLEMETOR_MASK|CPU_ID_VARIANT_MASK|\
57 1.1 bsh CPU_ID_ARCH_MASK|CPU_ID_XSCALE_COREGEN_MASK)
58 1.1 bsh
59 1.1 bsh #define __CPU_IS_PXA250 ((cpufunc_id() & CPU_ID_XSCALE_COREGEN_MASK) == 0x2000)
60 1.1 bsh #define __CPU_IS_PXA270 ((cpufunc_id() & CPU_ID_XSCALE_COREGEN_MASK) == 0x4000)
61 1.1 bsh
62 1.1 bsh # if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
63 1.1 bsh #define CPU_IS_PXA250 __CPU_IS_PXA250
64 1.1 bsh #define CPU_IS_PXA270 __CPU_IS_PXA270
65 1.1 bsh #elif defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
66 1.1 bsh #define CPU_IS_PXA250 (1)
67 1.1 bsh #define CPU_IS_PXA270 (0)
68 1.1 bsh #elif !defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
69 1.1 bsh #define CPU_IS_PXA250 (0)
70 1.1 bsh #define CPU_IS_PXA270 (1)
71 1.1 bsh #elif !defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
72 1.1 bsh #define CPU_IS_PXA250 (0)
73 1.1 bsh #define CPU_IS_PXA270 (0)
74 1.1 bsh #endif
75 1.1 bsh
76 1.1 bsh #include <arm/xscale/pxa2x0reg.h>
77 1.1 bsh
78 1.1 bsh #ifdef CPU_XSCALE_PXA270
79 1.1 bsh #define PXA2X0_GPIO_SIZE PXA270_GPIO_SIZE
80 1.1 bsh #define GPIO_REG PXA270_GPIO_REG
81 1.1 bsh #define GPIO_NPINS PXA270_GPIO_NPINS
82 1.1 bsh #else
83 1.1 bsh #define PXA2X0_GPIO_SIZE PXA250_GPIO_SIZE
84 1.1 bsh #define GPIO_REG PXA250_GPIO_REG
85 1.1 bsh #define GPIO_NPINS PXA250_GPIO_NPINS
86 1.1 bsh #endif
87 1.1 bsh
88 1.1 bsh #endif /* _ARM_XSCALE_PXA2X0CPU_H */
89