pxa2x0reg.h revision 1.12
1 /* $NetBSD: pxa2x0reg.h,v 1.12 2006/12/16 03:39:59 ober Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCMCIA_SLOT0 0x20000000 66 #define PXA2X0_PCMCIA_SLOT1 0x30000000 67 68 #define PXA2X0_PERIPH_START 0x40000000 69 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 70 #define PXA270_PERIPH_END 0x530fffff 71 #define PXA250_PERIPH_END 0x480fffff 72 73 #define PXA2X0_SDRAM0_START 0xa0000000 74 #define PXA2X0_SDRAM1_START 0xa4000000 75 #define PXA2X0_SDRAM2_START 0xa8000000 76 #define PXA2X0_SDRAM3_START 0xac000000 77 #define PXA2X0_SDRAM_BANKS 4 78 #define PXA2X0_SDRAM_BANK_SIZE 0x04000000 79 80 /* 81 * Physical address of integrated peripherals 82 */ 83 84 #define PXA2X0_DMAC_BASE 0x40000000 85 #define PXA2X0_DMAC_SIZE 0x300 86 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 87 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 88 #define PXA2X0_I2C_BASE 0x40300000 /* I2C Bus Interface Unit */ 89 #define PXA2X0_I2C_SIZE 0x000016a4 90 #define PXA2X0_I2S_BASE 0x40400000 /* Inter-IC Sound Controller */ 91 #define PXA2X0_I2S_SIZE 0x0084 92 #define PXA2X0_AC97_BASE 0x40500000 /* AC '97 Controller */ 93 #define PXA2X0_AC97_SIZE 0x600 94 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client Contoller */ 95 #define PXA2X0_USBDC_SIZE 0x0e04 96 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 97 #define PXA2X0_ICP_BASE 0x40800000 98 #define PXA2X0_RTC_BASE 0x40900000 99 #define PXA2X0_RTC_SIZE 0x10 100 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 101 #define PXA2X0_OST_SIZE 0x24 102 #define PXA2X0_PWM0_BASE 0x40b00000 103 #define PXA2X0_PWM1_BASE 0x40c00000 104 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 105 #define PXA2X0_INTCTL_SIZE 0x20 106 #define PXA2X0_GPIO_BASE 0x40e00000 107 #define PXA270_GPIO_SIZE 0x150 108 #define PXA250_GPIO_SIZE 0x70 109 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 110 #define PXA2X0_POWMAN_SIZE 0x1a4 /* incl. PI2C unit */ 111 #define PXA2X0_SSP_BASE 0x41000000 /* SSP serial port */ 112 #define PXA2X0_SSP1_BASE 0x41700000 /* PXA270 */ 113 #define PXA2X0_SSP2_BASE 0x41900000 /* PXA270 */ 114 #define PXA2X0_SSP_SIZE 0x40 115 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 116 #define PXA2X0_MMC_SIZE 0x48 117 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 118 #define PXA2X0_CLKMAN_SIZE 12 119 #define PXA2X0_HWUART_BASE 0x41600000 /* Hardware UART */ 120 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 121 #define PXA2X0_LCDC_SIZE 0x220 122 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 123 #define PXA2X0_MEMCTL_SIZE 0x48 124 #define PXA2X0_USBH_BASE 0x4c000000 /* USB Host controller */ 125 #define PXA2X0_USBH_SIZE 0x70 126 127 /* Internal SRAM storage. PXA27x only */ 128 #define PXA270_SRAM0_START 0x5c000000 129 #define PXA270_SRAM1_START 0x5c010000 130 #define PXA270_SRAM2_START 0x5c020000 131 #define PXA270_SRAM3_START 0x5c030000 132 #define PXA270_SRAM_BANKS 4 133 #define PXA270_SRAM_BANK_SIZE 0x00010000 134 135 /* width of interrupt controller */ 136 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 137 #define ICU_INT_HWMASK 0xffffff00 138 #define PXA250_IRQ_MIN 7 /* 0..6 are not used by integrated 139 peripherals */ 140 #define PXA270_IRQ_MIN 0 141 142 #define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */ 143 144 #define PXA2X0_INT_HWUART 7 145 #define PXA2X0_INT_GPIO0 8 146 #define PXA2X0_INT_GPIO1 9 147 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 148 #define PXA2X0_INT_USB 11 149 #define PXA2X0_INT_PMU 12 150 #define PXA2X0_INT_I2S 13 151 #define PXA2X0_INT_AC97 14 152 #define PXA2X0_INT_NSSP 16 153 #define PXA2X0_INT_LCD 17 154 #define PXA2X0_INT_I2C 18 155 #define PXA2X0_INT_ICP 19 156 #define PXA2X0_INT_STUART 20 157 #define PXA2X0_INT_BTUART 21 158 #define PXA2X0_INT_FFUART 22 159 #define PXA2X0_INT_MMC 23 160 #define PXA2X0_INT_SSP 24 161 #define PXA2X0_INT_DMA 25 162 #define PXA2X0_INT_OST0 26 163 #define PXA2X0_INT_OST1 27 164 #define PXA2X0_INT_OST2 28 165 #define PXA2X0_INT_OST3 29 166 #define PXA2X0_INT_RTCHZ 30 167 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 168 169 /* DMAC */ 170 #define DMAC_N_CHANNELS 16 171 #define DMAC_N_PRIORITIES 3 172 173 #define DMAC_DCSR(n) ((n)*4) 174 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 175 #define DCSR_STARTINR (1<<1) /* start interrupt */ 176 #define DCSR_ENDINTR (1<<2) /* end interrupt */ 177 #define DCSR_STOPSTATE (1<<3) /* channel is not running */ 178 #define DCSR_REQPEND (1<<8) /* request pending */ 179 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 180 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 181 #define DCSR_RUN (1<<31) 182 #define DMAC_DINT 0x00f0 /* DAM interrupt */ 183 #define DMAC_DINT_MASK 0xffffu 184 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 185 #define DRCMR_CHLNUM 0x0f /* channel number */ 186 #define DRCMR_MAPVLD (1<<7) /* map valid */ 187 #define DMAC_DDADR(n) (0x0200+(n)*16) 188 #define DDADR_STOP (1<<0) 189 #define DMAC_DSADR(n) (0x0204+(n)*16) 190 #define DMAC_DTADR(n) (0x0208+(n)*16) 191 #define DMAC_DCMD(n) (0x020c+(n)*16) 192 #define DCMD_LENGTH_MASK 0x1fff 193 #define DCMD_WIDTH_SHIFT 14 194 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 195 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 196 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 197 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 198 #define DCMD_SIZE_SHIFT 16 199 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 200 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 201 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 202 #define DCMD_LITTLE_ENDIEN (0<<18) 203 #define DCMD_ENDIRQEN (1<<21) 204 #define DCMD_STARTIRQEN (1<<22) 205 #define DCMD_FLOWTRG (1<<28) /* flow control by target */ 206 #define DCMD_FLOWSRC (1<<29) /* flow control by source */ 207 #define DCMD_INCTRGADDR (1<<30) /* increment target address */ 208 #define DCMD_INCSRCADDR (1<<31) /* increment source address */ 209 210 #ifndef __ASSEMBLER__ 211 /* DMA descriptor */ 212 struct pxa2x0_dma_desc { 213 volatile uint32_t dd_ddadr; 214 #define DMAC_DESC_LAST 0x1 215 volatile uint32_t dd_dsadr; 216 volatile uint32_t dd_dtadr; 217 volatile uint32_t dd_dcmd; /* command and length */ 218 }; 219 #endif 220 221 /* UART */ 222 #define PXA2X0_COM_FREQ 14745600L 223 224 /* I2C */ 225 #define I2C_IBMR 0x1680 /* Bus monitor register */ 226 #define I2C_IDBR 0x1688 /* Data buffer */ 227 #define I2C_ICR 0x1690 /* Control register */ 228 #define ICR_START (1<<0) 229 #define ICR_STOP (1<<1) 230 #define ICR_ACKNAK (1<<2) 231 #define ICR_TB (1<<3) 232 #define ICR_MA (1<<4) 233 #define ICR_SCLE (1<<5) /* PXA270? */ 234 #define ICR_IUE (1<<6) /* PXA270? */ 235 #define ICR_UR (1<<14) /* PXA270? */ 236 #define ICR_FM (1<<15) /* PXA270? */ 237 #define I2C_ISR 0x1698 /* Status register */ 238 #define ISR_ACKNAK (1<<1) 239 #define ISR_ITE (1<<6) 240 #define ISR_IRF (1<<7) 241 #define I2C_ISAR 0x16a0 /* Slave address */ 242 243 /* Clock Manager */ 244 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 245 #define CCCR_TURBO_X1 (2<<7) 246 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 247 #define CCCR_TURBO_X2 (4<<7) 248 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 249 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 250 #define CCCR_RUN_X1 (1<<5) 251 #define CCCR_RUN_X2 (2<<5) 252 #define CCCR_RUN_X4 (3<<5) 253 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 254 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 255 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 256 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 257 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 258 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 259 260 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 261 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 262 263 #define CCCR_N_SHIFT 7 264 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 265 #define CCCR_M_SHIFT 5 266 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 267 #define CCCR_L_MASK 0x1f 268 269 #define CKEN_PWM0 (1<<0) 270 #define CKEN_PWM1 (1<<1) 271 #define CKEN_AC97 (1<<2) 272 #define CKEN_SSP (1<<3) 273 #define CKEN_HWUART (1<<4) 274 #define CKEN_STUART (1<<5) 275 #define CKEN_FFUART (1<<6) 276 #define CKEN_BTUART (1<<7) 277 #define CKEN_I2S (1<<8) 278 #define CKEN_NSSP (1<<9) 279 #define CKEN_USBH (1<<10) 280 #define CKEN_USB (1<<11) 281 #define CKEN_MMC (1<<12) 282 #define CKEN_FICP (1<<13) 283 #define CKEN_I2C (1<<14) 284 #define CKEN_LCD (1<<16) 285 286 #define OSCC_OOK (1<<0) /* 32.768 kHz oscillator status */ 287 #define OSCC_OON (1<<1) /* 32.768 kHz oscillator */ 288 289 /* 290 * RTC 291 */ 292 #define RTC_RCNR 0x0000 /* count register */ 293 #define RTC_RTAR 0x0004 /* alarm register */ 294 #define RTC_RTSR 0x0008 /* status register */ 295 #define RTC_RTTR 0x000c /* trim register */ 296 /* 297 * GPIO 298 */ 299 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 300 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 301 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 302 303 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 304 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 305 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 306 307 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 308 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 309 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 310 311 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 312 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 313 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 314 315 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 316 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 317 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 318 319 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 320 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 321 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 322 323 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 324 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 325 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 326 327 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 328 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 329 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 330 331 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 332 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 333 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 334 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 335 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 336 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 337 338 /* Only for PXA270 */ 339 #define GPIO_GAFR3_L 0x6c /* alternate function [111:96] */ 340 #define GPIO_GAFR3_U 0x70 /* alternate function [120:112] */ 341 342 #define GPIO_GPLR3 0x100 /* Level reg [120:96] */ 343 #define GPIO_GPDR3 0x10c /* dir reg [120:96] */ 344 #define GPIO_GPSR3 0x118 /* set reg [120:96] */ 345 #define GPIO_GPCR3 0x124 /* clear reg [120:96] */ 346 #define GPIO_GRER3 0x130 /* rising edge [120:96] */ 347 #define GPIO_GFER3 0x13c /* falling edge [120:96] */ 348 #define GPIO_GEDR3 0x148 /* edge detect [120:96] */ 349 350 /* a bit simpler if we don't support PXA270 */ 351 #define PXA250_GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4)) 352 #define PXA250_GPIO_NPINS 85 353 354 #define PXA270_GPIO_REG(r, pin) \ 355 (pin < 96 ? PXA250_GPIO_REG(r,pin) : ((r) + 0x100 + ((((pin)-96) / 32) * 4))) 356 #define PXA270_GPIO_NPINS 121 357 358 359 #define GPIO_BANK(pin) ((pin) / 32) 360 #define GPIO_BIT(pin) (1u << ((pin) & 0x1f)) 361 #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4)) 362 #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2) 363 364 #define GPIO_IN 0x00 /* Regular GPIO input pin */ 365 #define GPIO_OUT 0x10 /* Regular GPIO output pin */ 366 #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */ 367 #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */ 368 #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */ 369 #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */ 370 #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */ 371 #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */ 372 #define GPIO_SET 0x20 /* Initial state is Set */ 373 #define GPIO_CLR 0x00 /* Initial state is Clear */ 374 375 #define GPIO_FN_MASK 0x03 376 #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT) 377 #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET) 378 #define GPIO_FN(n) ((n) & GPIO_FN_MASK) 379 #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) 380 #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) 381 #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT) 382 383 /* 384 * memory controller 385 */ 386 387 #define MEMCTL_MDCNFG 0x0000 388 #define MDCNFG_DE0 (1<<0) 389 #define MDCNFG_DE1 (1<<1) 390 #define MDCNFD_DWID01_SHIFT 2 391 #define MDCNFD_DCAC01_SHIFT 3 392 #define MDCNFD_DRAC01_SHIFT 5 393 #define MDCNFD_DNB01_SHIFT 7 394 #define MDCNFG_DE2 (1<<16) 395 #define MDCNFG_DE3 (1<<17) 396 #define MDCNFD_DWID23_SHIFT 18 397 #define MDCNFD_DCAC23_SHIFT 19 398 #define MDCNFD_DRAC23_SHIFT 21 399 #define MDCNFD_DNB23_SHIFT 23 400 401 #define MDCNFD_DWID_MASK 0x1 402 #define MDCNFD_DCAC_MASK 0x3 403 #define MDCNFD_DRAC_MASK 0x3 404 #define MDCNFD_DNB_MASK 0x1 405 406 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 407 #define MDREFR_DRI 0xfff 408 #define MDREFR_E0PIN (1<<12) 409 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 410 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 411 #define MDREFR_E1PIN (1<<15) 412 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 413 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 414 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 415 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 416 #define MDREFR_APD (1<<20) /* Auto Power Down */ 417 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 418 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 419 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 420 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 421 422 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 423 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 424 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 425 #define MSC_RBUFF_SHIFT 15 /* return data buffer */ 426 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 427 #define MSC_RRR_SHIFT 12 /* recovery time */ 428 #define MSC_RRR (7<<MSC_RRR_SHIFT) 429 #define MSC_RDN_SHIFT 8 /* ROM delay next access */ 430 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 431 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 432 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 433 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 434 #define MSC_RBW (1<<MSC_RBW_SHIFT) 435 #define MSC_RT_SHIFT 0 /* type */ 436 #define MSC_RT (7<<MSC_RT_SHIFT) 437 #define MSC_RT_NONBURST 0 438 #define MSC_RT_SRAM 1 439 #define MSC_RT_BURST4 2 440 #define MSC_RT_BURST8 3 441 #define MSC_RT_VLIO 4 442 443 /* expansion memory timing configuration */ 444 #define MEMCTL_MCMEM(n) (0x28+4*(n)) 445 #define MEMCTL_MCATT(n) (0x30+4*(n)) 446 #define MEMCTL_MCIO(n) (0x38+4*(n)) 447 448 #define MC_HOLD_SHIFT 14 449 #define MC_ASST_SHIFT 7 450 #define MC_SET_SHIFT 0 451 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 452 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 453 454 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 455 #define MECR_NOS (1<<0) /* Number of sockets */ 456 #define MECR_CIT (1<<1) /* Card-is-there */ 457 458 #define MEMCTL_MDMRS 0x0040 459 460 /* 461 * LCD Controller 462 */ 463 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 464 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 465 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 466 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 467 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 468 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 469 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 470 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 471 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 472 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 473 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 474 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 475 #define LCCR0_BM (1U<<20) /* Branch Mask */ 476 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 477 478 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 479 480 481 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 482 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 483 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 484 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 485 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 486 #define LCDC_LCCR4 0x010 /* Controller Control Register 4 */ 487 #define LCDC_LCCR5 0x014 /* Controller Control Register 5 */ 488 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 489 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 490 #define LCDC_FBR2 0x028 /* DMA ch2 frame branch register */ 491 #define LCDC_FBR3 0x02c /* DMA ch3 frame branch register */ 492 #define LCDC_FBR4 0x030 /* DMA ch4 frame branch register */ 493 #define LCDC_LCSR1 0x034 /* controller status register 1 PXA27x only */ 494 #define LCDC_LCSR 0x038 /* controller status register */ 495 #define LCSR_LDD (1U<<0) /* LCD disable done */ 496 #define LCSR_SOF (1U<<1) /* Start of frame */ 497 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 498 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 499 #define LCDC_TCR 0x044 /* TMED Control Register */ 500 #define LCDC_OVL1C1 0x050 /* Overlay 1 control register 1 */ 501 #define LCDC_OVL1C2 0x060 /* Overlay 1 control register 2 */ 502 #define LCDC_OVL2C1 0x070 /* Overlay 1 control register 1 */ 503 #define LCDC_OVL2C2 0x080 /* Overlay 1 control register 2 */ 504 #define LCDC_CCR 0x090 /* Cursor control register */ 505 #define LCDC_CMDCR 0x100 /* Command control register */ 506 #define LCDC_PRSR 0x104 /* Panel read status register */ 507 #define LCDC_FBR5 0x110 /* DMA ch5 frame branch register */ 508 #define LCDC_FBR6 0x114 /* DMA ch6 frame branch register */ 509 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 510 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 511 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 512 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 513 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 514 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 515 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 516 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 517 #define LCDC_FDADR2 0x220 /* DMA ch2 frame descriptor address */ 518 #define LCDC_FSADR2 0x224 /* DMA ch2 frame source address */ 519 #define LCDC_FIDR2 0x228 /* DMA ch2 frame ID register */ 520 #define LCDC_LDCMD2 0x22c /* DMA ch2 command register */ 521 #define LCDC_FDADR3 0x230 /* DMA ch3 frame descriptor address */ 522 #define LCDC_FSADR3 0x234 /* DMA ch3 frame source address */ 523 #define LCDC_FIDR3 0x238 /* DMA ch3 frame ID register */ 524 #define LCDC_LDCMD3 0x23c /* DMA ch3 command register */ 525 #define LCDC_FDADR4 0x240 /* DMA ch4 frame descriptor address */ 526 #define LCDC_FSADR4 0x244 /* DMA ch4 frame source address */ 527 #define LCDC_FIDR4 0x248 /* DMA ch4 frame ID register */ 528 #define LCDC_LDCMD4 0x24c /* DMA ch4 command register */ 529 #define LCDC_FDADR5 0x250 /* DMA ch5 frame descriptor address */ 530 #define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */ 531 #define LCDC_FIDR5 0x258 /* DMA ch5 frame ID register */ 532 #define LCDC_LDCMD5 0x25c /* DMA ch5 command register */ 533 #define LCDC_FDADR6 0x260 /* DMA ch6 frame descriptor address */ 534 #define LCDC_FSADR6 0x264 /* DMA ch6 frame source address */ 535 #define LCDC_FIDR6 0x268 /* DMA ch6 frame ID register */ 536 #define LCDC_LDCMD6 0x26c /* DMA ch6 command register */ 537 #define LCDC_LCDBSCNTR 0x054 /* LCD buffer strength control register */ 538 539 /* 540 * MMC/SD controller 541 */ 542 #define MMC_STRPCL 0x00 /* start/stop MMC clock */ 543 #define STRPCL_NOOP 0 544 #define STRPCL_STOP 1 /* stop MMC clock */ 545 #define STRPCL_START 2 /* start MMC clock */ 546 #define MMC_STAT 0x04 /* status register */ 547 #define STAT_READ_TIME_OUT (1<<0) 548 #define STAT_TIMEOUT_RESPONSE (1<<1) 549 #define STAT_CRC_WRITE_ERROR (1<<2) 550 #define STAT_CRC_READ_ERROR (1<<3) 551 #define STAT_SPI_READ_ERROR_TOKEN (1<<4) 552 #define STAT_RES_CRC_ERR (1<<5) 553 #define STAT_XMIT_FIFO_EMPTY (1<<6) 554 #define STAT_RECV_FIFO_FULL (1<<7) 555 #define STAT_CLK_EN (1<<8) 556 #define STAT_DATA_TRAN_DONE (1<<11) 557 #define STAT_PRG_DONE (1<<12) 558 #define STAT_END_CMD_RES (1<<13) 559 #define MMC_CLKRT 0x08 /* MMC clock rate */ 560 #define CLKRT_20M 0 561 #define CLKRT_10M 1 562 #define CLKRT_5M 2 563 #define CLKRT_2_5M 3 564 #define CLKRT_1_25M 4 565 #define CLKRT_625K 5 566 #define CLKRT_312K 6 567 #define MMC_SPI 0x0c /* SPI mode control */ 568 #define SPI_EN (1<<0) /* enable SPI mode */ 569 #define SPI_CRC_ON (1<<1) /* enable CRC generation */ 570 #define SPI_CS_EN (1<<2) /* Enable CS[01] */ 571 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 572 #define MMC_CMDAT 0x10 /* command/response/data */ 573 #define CMDAT_RESPONSE_FORMAT 0x03 574 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 575 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 576 #define CMDAT_RESPONSE_FORMAT_R2 2 577 #define CMDAT_RESPONSE_FORMAT_R3 3 578 #define CMDAT_DATA_EN (1<<2) 579 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 580 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 581 #define CMDAT_BUSY (1<<5) /* busy signal is expected */ 582 #define CMDAT_INIT (1<<6) /* precede command with 80 clocks */ 583 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 584 #define MMC_RESTO 0x14 /* expected response time out */ 585 #define MMC_RDTO 0x18 /* expected data read time out */ 586 #define MMC_BLKLEN 0x1c /* block length of data transaction */ 587 #define MMC_NOB 0x20 /* number of blocks (block mode) */ 588 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 589 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 590 #define MMC_I_MASK 0x28 /* interrupt mask */ 591 #define MMC_I_REG 0x2c /* interrupt register */ 592 #define MMC_I_DATA_TRAN_DONE (1<<0) 593 #define MMC_I_PRG_DONE (1<<1) 594 #define MMC_I_END_CMD_RES (1<<2) 595 #define MMC_I_STOP_CMD (1<<3) 596 #define MMC_I_CLK_IS_OFF (1<<4) 597 #define MMC_I_RXFIFO_RD_REQ (1<<5) 598 #define MMC_I_TXFIFO_WR_REQ (1<<6) 599 #define MMC_CMD 0x30 /* index of current command */ 600 #define MMC_ARGH 0x34 /* MSW part of the current command arg */ 601 #define MMC_ARGL 0x38 /* LSW part of the current command arg */ 602 #define MMC_RES 0x3c /* response FIFO */ 603 #define MMC_RXFIFO 0x40 /* receive FIFO */ 604 #define MMC_TXFIFO 0x44 /* transmit FIFO */ 605 606 /* 607 * Inter-IC Sound (I2S) Controller 608 */ 609 #define I2S_SACR0 0x0000 /* Serial Audio Global Control */ 610 #define SACR0_ENB (1<<0) /* Enable I2S Function */ 611 #define SACR0_BCKD (1<<2) /* I/O Direction of I2S_BITCLK */ 612 #define SACR0_RST (1<<3) /* FIFO Reset */ 613 #define SACR0_EFWR (1<<4) /* Special-Purpose FIFO W/R Func */ 614 #define SACR0_STRF (1<<5) /* Select TX or RX FIFO */ 615 #define SACR0_TFTH_MASK (0xf<<8) /* Trans FIFO Intr/DMA Trig Thresh */ 616 #define SACR0_RFTH_MASK (0xf<<12) /* Recv FIFO Intr/DMA Trig Thresh */ 617 #define SACR0_SET_TFTH(x) (((x) & 0xf)<<8) 618 #define SACR0_SET_RFTH(x) (((x) & 0xf)<<12) 619 #define I2S_SACR1 0x0004 /* Serial Audio I2S/MSB-Justified Control */ 620 #define SACR1_AMSL (1<<0) /* Specify Alt Mode (I2S or MSB) */ 621 #define SACR1_DREC (1<<3) /* Disable Recording Func */ 622 #define SACR1_DRPL (1<<4) /* Disable Replay Func */ 623 #define SACR1_ENLBF (1<<5) /* Enable Interface Loopback Func */ 624 #define I2S_SASR0 0x000c /* Serial Audio I2S/MSB-Justified Status */ 625 #define SASR0_TNF (1<<0) /* Transmit FIFO Not Full */ 626 #define SASR0_RNE (1<<1) /* Recv FIFO Not Empty */ 627 #define SASR0_BSY (1<<2) /* I2S Busy */ 628 #define SASR0_TFS (1<<3) /* Trans FIFO Service Request */ 629 #define SASR0_RFS (1<<4) /* Recv FIFO Service Request */ 630 #define SASR0_TUR (1<<5) /* Trans FIFO Underrun */ 631 #define SASR0_ROR (1<<6) /* Recv FIFO Overrun */ 632 #define SASR0_I2SOFF (1<<7) /* I2S Controller Off */ 633 #define SASR0_TFL_MASK (0xf<<8) /* Trans FIFO Level */ 634 #define SASR0_RFL_MASK (0xf<<12) /* Recv FIFO Level */ 635 #define SASR0_GET_TFL(x) (((x) & 0xf) >> 8) 636 #define SASR0_GET_RFL(x) (((x) & 0xf) >> 12) 637 #define I2S_SAIMR 0x0014 /* Serial Audio Interrupt Mask */ 638 #define SAIMR_TFS (1<<3) /* Enable TX FIFO Service Req Intr */ 639 #define SAIMR_RFS (1<<4) /* Enable RX FIFO Service Req Intr */ 640 #define SAIMR_TUR (1<<5) /* Enable TX FIFO Underrun Intr */ 641 #define SAIMR_ROR (1<<6) /* Enable RX FIFO Overrun Intr */ 642 #define I2S_SAICR 0x0018 /* Serial Audio Interrupt Clear */ 643 #define SAICR_TUR (1<<5) /* Clear Intr and SASR0_TUR */ 644 #define SAICR_ROR (1<<6) /* Clear Intr and SASR0_ROR */ 645 #define I2S_SADIV 0x0060 /* Audio Clock Divider */ 646 #define SADIV_MASK 0x7f 647 #define SADIV_3_058MHz 0x0c /* 3.058 MHz */ 648 #define SADIV_2_836MHz 0x0d /* 2.836 MHz */ 649 #define SADIV_1_405MHz 0x1a /* 1.405 MHz */ 650 #define SADIV_1_026MHz 0x24 /* 1.026 MHz */ 651 #define SADIV_702_75kHz 0x34 /* 702.75 kHz */ 652 #define SADIV_513_25kHz 0x48 /* 513.25 kHz */ 653 #define I2S_SADR 0x0080 /* Serial Audio Data Register */ 654 #define SADR_DTL (0xffff<<0) /* Left Data Sample */ 655 #define SADR_DTH (0xffff<<16) /* Right Data Sample */ 656 657 /* 658 * AC97 659 */ 660 #define AC97_N_CODECS 2 661 #define AC97_GCR 0x000c /* Global control register */ 662 #define GCR_GIE (1<<0) /* interrupt enable */ 663 #define GCR_COLD_RST (1<<1) 664 #define GCR_WARM_RST (1<<2) 665 #define GCR_ACLINK_OFF (1<<3) 666 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 667 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 668 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 669 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 670 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 671 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 672 673 #define AC97_GSR 0x001c /* Global status register */ 674 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 675 #define GSR_MIINT (1<<1) /* modem in interrupt */ 676 #define GSR_MOINT (1<<2) /* modem out interrupt */ 677 #define GSR_PIINT (1<<5) /* PCM in interrupt */ 678 #define GSR_POINT (1<<6) /* PCM out interrupt */ 679 #define GSR_MINT (1<<7) /* Mic in interrupt */ 680 #define GSR_PCR (1<<8) /* primary code ready */ 681 #define GSR_SCR (1<<9) /* secondary code ready */ 682 #define GSR_PRIRES (1<<10) /* primary resume interrupt */ 683 #define GSR_SECRES (1<<11) /* secondary resume interrupt */ 684 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 685 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 686 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 687 #define GSR_RDCS (1<<15) /* Read completion status */ 688 #define GSR_SDONE (1<<18) /* status done */ 689 #define GSR_CDONE (1<<19) /* command done */ 690 691 #define AC97_POCR 0x0000 /* PCM-out control */ 692 #define AC97_PICR 0x0004 /* PCM-in control */ 693 #define AC97_POSR 0x0010 /* PCM-out status */ 694 #define AC97_PISR 0x0014 /* PCM-out status */ 695 #define AC97_MCCR 0x0008 /* MIC-in control register */ 696 #define AC97_MCSR 0x0018 /* MIC-in status register */ 697 #define AC97_MICR 0x0100 /* Modem-in control register */ 698 #define AC97_MISR 0x0108 /* Modem-in status register */ 699 #define AC97_MOCR 0x0110 /* Modem-out control register */ 700 #define AC97_MOSR 0x0118 /* Modem-out status register */ 701 #define AC97_FEFIE (1<<3) /* fifo error interrupt enable */ 702 #define AC97_FIFOE (1<<4) /* fifo error */ 703 704 #define AC97_CAR 0x0020 /* Codec access register */ 705 #define CAR_CAIP (1<<0) /* Codec access in progress */ 706 707 #define AC97_PCDR 0x0040 /* PCM data register */ 708 #define AC97_MCDR 0x0060 /* MIC-in data register */ 709 #define AC97_MODR 0x0140 /* Modem data register */ 710 711 /* address to access codec registers */ 712 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 713 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 714 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 715 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 716 #define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100)) 717 718 /* 719 * USB device controller 720 */ 721 #define USBDC_UDCCR 0x0000 /* UDC control register */ 722 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 723 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 724 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 725 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 726 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 727 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 728 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 729 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 730 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 731 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 732 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 733 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 734 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 735 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 736 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 737 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 738 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 739 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 740 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 741 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 742 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 743 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 744 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 745 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 746 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 747 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 748 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 749 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 750 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 751 752 #define USBHC_UHCRHDA 0x0048 /* UHC Root Hub Descriptor A */ 753 #define UHCRHDA_POTPGT_SHIFT 24 /* Power on to power good time */ 754 #define UHCRHDA_NOCP (1<<12) /* No over current protection */ 755 #define UHCRHDA_OCPM (1<<11) /* Over current protection mode */ 756 #define UHCRHDA_DT (1<<10) /* Device type */ 757 #define UHCRHDA_NPS (1<<9) /* No power switching */ 758 #define UHCRHDA_PSM (1<<8) /* Power switching mode */ 759 #define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */ 760 #define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */ 761 #define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */ 762 #define USBHC_UHCHR 0x0064 /* UHC Reset Register */ 763 #define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */ 764 #define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */ 765 #define UHCHR_SSEP1 (1<<9) /* Sleep standby enable for port1 */ 766 #define UHCHR_PCPL (1<<7) /* Power control polarity low */ 767 #define UHCHR_PSPL (1<<6) /* Power sense polarity low */ 768 #define UHCHR_SSE (1<<5) /* Sleep standby enable */ 769 #define UHCHR_UIT (1<<4) /* USB interrupt test */ 770 #define UHCHR_SSDC (1<<3) /* Simulation scale down clock */ 771 #define UHCHR_CGR (1<<2) /* Clock generation reset */ 772 #define UHCHR_FHR (1<<1) /* Force host controller reset */ 773 #define UHCHR_FSBIR (1<<0) /* Force system bus interface reset */ 774 #define UHCHR_MASK 0xeff 775 776 /* 777 * PWM controller 778 */ 779 #define PWM_PWMCR 0x0000 /* Control register */ 780 #define PWM_PWMDCR 0x0004 /* Duty cycle register */ 781 #define PWM_FD (1<<10) /* Full duty */ 782 #define PWM_PWMPCR 0x0008 /* Period register */ 783 784 /* Synchronous Serial Protocol (SSP) serial ports */ 785 #define SSP_SSCR0 0x00 786 #define SSP_SSCR1 0x04 787 #define SSP_SSSR 0x08 788 #define SSSR_TNF (1<<2) 789 #define SSSR_RNE (1<<3) 790 #define SSP_SSDR 0x10 791 792 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 793
Indexes created Tue Sep 30 20:09:53 GMT 2025