pxa2x0reg.h revision 1.16
1 /* $NetBSD: pxa2x0reg.h,v 1.16 2007/06/28 14:30:58 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCIC_SOCKET_BASE 0x20000000 66 #define PXA2X0_PCIC_SOCKET_OFFSET 0x10000000 67 #define PXA2X0_PCMCIA_SLOT0 PXA2X0_PCIC_SOCKET_BASE 68 #define PXA2X0_PCMCIA_SLOT1 \ 69 (PXA2X0_PCIC_PCMCIA_SLOT0 + PXA2X0_PCIC_SOCKET_OFFSET) 70 71 #define PXA2X0_PERIPH_START 0x40000000 72 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 73 #define PXA270_PERIPH_END 0x530fffff 74 #define PXA250_PERIPH_END 0x480fffff 75 76 #define PXA2X0_SDRAM0_START 0xa0000000 77 #define PXA2X0_SDRAM1_START 0xa4000000 78 #define PXA2X0_SDRAM2_START 0xa8000000 79 #define PXA2X0_SDRAM3_START 0xac000000 80 #define PXA2X0_SDRAM_BANKS 4 81 #define PXA2X0_SDRAM_BANK_SIZE 0x04000000 82 83 /* 84 * Physical address of integrated peripherals 85 */ 86 87 #define PXA2X0_DMAC_BASE 0x40000000 88 #define PXA2X0_DMAC_SIZE 0x300 89 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 90 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 91 #define PXA2X0_I2C_BASE 0x40300000 /* I2C Bus Interface Unit */ 92 #define PXA2X0_I2C_SIZE 0x16a4 93 #define PXA2X0_I2S_BASE 0x40400000 /* Inter-IC Sound Controller */ 94 #define PXA2X0_I2S_SIZE 0x84 95 #define PXA2X0_AC97_BASE 0x40500000 /* AC '97 Controller */ 96 #define PXA2X0_AC97_SIZE 0x600 97 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client Contoller */ 98 #define PXA250_USBDC_SIZE 0xe04 99 #define PXA270_USBDC_SIZE 0x460 100 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 101 #define PXA2X0_ICP_BASE 0x40800000 102 #define PXA2X0_RTC_BASE 0x40900000 /* Real-time Clock */ 103 #define PXA250_RTC_SIZE 0x10 104 #define PXA270_RTC_SIZE 0x3c 105 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 106 #define PXA2X0_OST_SIZE 0x24 107 #define PXA2X0_PWM0_BASE 0x40b00000 108 #define PXA2X0_PWM1_BASE 0x40c00000 109 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 110 #define PXA2X0_INTCTL_SIZE 0x20 111 #define PXA2X0_GPIO_BASE 0x40e00000 112 #define PXA270_GPIO_SIZE 0x150 113 #define PXA250_GPIO_SIZE 0x70 114 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 115 #define PXA2X0_POWMAN_SIZE 0x1a4 /* incl. PI2C unit */ 116 #define PXA2X0_SSP_BASE 0x41000000 /* SSP serial port */ 117 #define PXA2X0_SSP1_BASE 0x41700000 /* PXA270 */ 118 #define PXA2X0_SSP2_BASE 0x41900000 /* PXA270 */ 119 #define PXA2X0_SSP_SIZE 0x40 120 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 121 #define PXA2X0_MMC_SIZE 0x50 122 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 123 #define PXA2X0_CLKMAN_SIZE 12 124 #define PXA2X0_HWUART_BASE 0x41600000 /* Hardware UART */ 125 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 126 #define PXA2X0_LCDC_SIZE 0x220 127 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 128 #define PXA250_MEMCTL_SIZE 0x48 129 #define PXA270_MEMCTL_SIZE 0x84 130 #define PXA2X0_USBHC_BASE 0x4c000000 /* USB Host controller */ 131 #define PXA2X0_USBHC_SIZE 0x70 132 133 /* Internal SRAM storage. PXA27x only */ 134 #define PXA270_SRAM0_START 0x5c000000 135 #define PXA270_SRAM1_START 0x5c010000 136 #define PXA270_SRAM2_START 0x5c020000 137 #define PXA270_SRAM3_START 0x5c030000 138 #define PXA270_SRAM_BANKS 4 139 #define PXA270_SRAM_BANK_SIZE 0x00010000 140 141 /* width of interrupt controller */ 142 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 143 #define ICU_INT_HWMASK 0xffffff00 144 #define PXA250_IRQ_MIN 7 /* 0..6 are not used by integrated 145 peripherals */ 146 #define PXA270_IRQ_MIN 0 147 148 #define PXA2X0_INT_USBH2 2 /* USB host (all other events) */ 149 #define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */ 150 151 #define PXA2X0_INT_HWUART 7 152 #define PXA2X0_INT_GPIO0 8 153 #define PXA2X0_INT_GPIO1 9 154 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 155 #define PXA2X0_INT_USB 11 156 #define PXA2X0_INT_PMU 12 157 #define PXA2X0_INT_I2S 13 158 #define PXA2X0_INT_AC97 14 159 #define PXA2X0_INT_NSSP 16 160 #define PXA2X0_INT_LCD 17 161 #define PXA2X0_INT_I2C 18 162 #define PXA2X0_INT_ICP 19 163 #define PXA2X0_INT_STUART 20 164 #define PXA2X0_INT_BTUART 21 165 #define PXA2X0_INT_FFUART 22 166 #define PXA2X0_INT_MMC 23 167 #define PXA2X0_INT_SSP 24 168 #define PXA2X0_INT_DMA 25 169 #define PXA2X0_INT_OST0 26 170 #define PXA2X0_INT_OST1 27 171 #define PXA2X0_INT_OST2 28 172 #define PXA2X0_INT_OST3 29 173 #define PXA2X0_INT_RTCHZ 30 174 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 175 176 /* DMAC */ 177 #define DMAC_N_CHANNELS 16 178 #define DMAC_N_PRIORITIES 3 179 180 #define DMAC_DCSR(n) ((n)*4) 181 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 182 #define DCSR_STARTINR (1<<1) /* start interrupt */ 183 #define DCSR_ENDINTR (1<<2) /* end interrupt */ 184 #define DCSR_STOPSTATE (1<<3) /* channel is not running */ 185 #define DCSR_REQPEND (1<<8) /* request pending */ 186 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 187 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 188 #define DCSR_RUN (1<<31) 189 #define DMAC_DINT 0x00f0 /* DMA interrupt */ 190 #define DMAC_DINT_MASK 0xffffu 191 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 192 #define DRCMR_CHLNUM 0x0f /* channel number */ 193 #define DRCMR_MAPVLD (1<<7) /* map valid */ 194 #define DMAC_DDADR(n) (0x0200+(n)*16) 195 #define DDADR_STOP (1<<0) 196 #define DMAC_DSADR(n) (0x0204+(n)*16) 197 #define DMAC_DTADR(n) (0x0208+(n)*16) 198 #define DMAC_DCMD(n) (0x020c+(n)*16) 199 #define DCMD_LENGTH_MASK 0x1fff 200 #define DCMD_WIDTH_SHIFT 14 201 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 202 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 203 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 204 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 205 #define DCMD_SIZE_SHIFT 16 206 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 207 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 208 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 209 #define DCMD_LITTLE_ENDIEN (0<<18) 210 #define DCMD_ENDIRQEN (1<<21) 211 #define DCMD_STARTIRQEN (1<<22) 212 #define DCMD_FLOWTRG (1<<28) /* flow control by target */ 213 #define DCMD_FLOWSRC (1<<29) /* flow control by source */ 214 #define DCMD_INCTRGADDR (1<<30) /* increment target address */ 215 #define DCMD_INCSRCADDR (1<<31) /* increment source address */ 216 217 #ifndef __ASSEMBLER__ 218 /* DMA descriptor */ 219 struct pxa2x0_dma_desc { 220 volatile uint32_t dd_ddadr; 221 #define DMAC_DESC_LAST 0x1 222 volatile uint32_t dd_dsadr; 223 volatile uint32_t dd_dtadr; 224 volatile uint32_t dd_dcmd; /* command and length */ 225 }; 226 #endif 227 228 /* UART */ 229 #define PXA2X0_COM_FREQ 14745600L 230 231 /* I2C */ 232 #define I2C_IBMR 0x1680 /* Bus monitor register */ 233 #define I2C_IDBR 0x1688 /* Data buffer */ 234 #define I2C_ICR 0x1690 /* Control register */ 235 #define ICR_START (1<<0) 236 #define ICR_STOP (1<<1) 237 #define ICR_ACKNAK (1<<2) 238 #define ICR_TB (1<<3) 239 #define ICR_MA (1<<4) 240 #define ICR_SCLE (1<<5) /* PXA270? */ 241 #define ICR_IUE (1<<6) /* PXA270? */ 242 #define ICR_UR (1<<14) /* PXA270? */ 243 #define ICR_FM (1<<15) /* PXA270? */ 244 #define I2C_ISR 0x1698 /* Status register */ 245 #define ISR_ACKNAK (1<<1) 246 #define ISR_ITE (1<<6) 247 #define ISR_IRF (1<<7) 248 #define I2C_ISAR 0x16a0 /* Slave address */ 249 250 /* Clock Manager */ 251 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 252 #define CCCR_TURBO_X1 (2<<7) 253 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 254 #define CCCR_TURBO_X2 (4<<7) 255 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 256 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 257 #define CCCR_RUN_X1 (1<<5) 258 #define CCCR_RUN_X2 (2<<5) 259 #define CCCR_RUN_X4 (3<<5) 260 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 261 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 262 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 263 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 264 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 265 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 266 267 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 268 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 269 270 #define CCCR_N_SHIFT 7 271 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 272 #define CCCR_M_SHIFT 5 273 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 274 #define CCCR_L_MASK 0x1f 275 276 #define CKEN_PWM0 (1<<0) 277 #define CKEN_PWM1 (1<<1) 278 #define CKEN_AC97 (1<<2) 279 #define CKEN_SSP (1<<3) 280 #define CKEN_HWUART (1<<4) 281 #define CKEN_STUART (1<<5) 282 #define CKEN_FFUART (1<<6) 283 #define CKEN_BTUART (1<<7) 284 #define CKEN_I2S (1<<8) 285 #define CKEN_NSSP (1<<9) 286 #define CKEN_USBHC (1<<10) 287 #define CKEN_USBDC (1<<11) 288 #define CKEN_MMC (1<<12) 289 #define CKEN_FICP (1<<13) 290 #define CKEN_I2C (1<<14) 291 #define CKEN_LCD (1<<16) 292 293 #define OSCC_OOK (1<<0) /* 32.768 kHz oscillator status */ 294 #define OSCC_OON (1<<1) /* 32.768 kHz oscillator */ 295 296 /* 297 * RTC 298 */ 299 #define RTC_RCNR 0x0000 /* count register */ 300 #define RTC_RTAR 0x0004 /* alarm register */ 301 #define RTC_RTSR 0x0008 /* status register */ 302 #define RTC_RTTR 0x000c /* trim register */ 303 #define RTC_RDCR 0x0010 /* day counter register */ 304 #define RTC_RYCR 0x0014 /* year counter register */ 305 #define RTC_RDAR1 0x0018 /* wristwatch day alarm register 1 */ 306 #define RTC_RYAR1 0x001c /* wristwatch year alarm register 1 */ 307 #define RTC_RDAR2 0x0020 /* wristwatch day alarm register 2 */ 308 #define RTC_RYAR2 0x0024 /* wristwatch year alarm register 2 */ 309 #define RTC_SWCR 0x0028 /* stopwatch counter register */ 310 #define RTC_SWAR1 0x002c /* stopwatch alarm register 1 */ 311 #define RTC_SWAR2 0x0030 /* stopwatch alarm register 2 */ 312 #define RTC_RTCPICR 0x0034 /* periodic interrupt counter register */ 313 #define RTC_PIAR 0x0038 /* periodic interrupt alarm register */ 314 315 #define RDCR_SECOND_SHIFT 0 316 #define RDCR_SECOND_MASK 0x3f 317 #define RDCR_MINUTE_SHIFT 6 318 #define RDCR_MINUTE_MASK 0x3f 319 #define RDCR_HOUR_SHIFT 12 320 #define RDCR_HOUR_MASK 0x1f 321 #define RDCR_DOW_SHIFT 17 322 #define RDCR_DOW_MASK 0x7 323 #define RDCR_WOM_SHIFT 20 324 #define RDCR_WOM_MASK 0x7 325 #define RYCR_DOM_SHIFT 0 326 #define RYCR_DOM_MASK 0x1f 327 #define RYCR_MONTH_SHIFT 5 328 #define RYCR_MONTH_MASK 0xf 329 #define RYCR_YEAR_SHIFT 9 330 #define RYCR_YEAR_MASK 0xfff 331 332 /* 333 * GPIO 334 */ 335 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 336 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 337 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 338 339 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 340 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 341 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 342 343 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 344 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 345 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 346 347 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 348 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 349 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 350 351 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 352 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 353 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 354 355 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 356 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 357 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 358 359 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 360 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 361 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 362 363 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 364 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 365 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 366 367 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 368 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 369 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 370 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 371 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 372 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 373 374 /* Only for PXA270 */ 375 #define GPIO_GAFR3_L 0x6c /* alternate function [111:96] */ 376 #define GPIO_GAFR3_U 0x70 /* alternate function [120:112] */ 377 378 #define GPIO_GPLR3 0x100 /* Level reg [120:96] */ 379 #define GPIO_GPDR3 0x10c /* dir reg [120:96] */ 380 #define GPIO_GPSR3 0x118 /* set reg [120:96] */ 381 #define GPIO_GPCR3 0x124 /* clear reg [120:96] */ 382 #define GPIO_GRER3 0x130 /* rising edge [120:96] */ 383 #define GPIO_GFER3 0x13c /* falling edge [120:96] */ 384 #define GPIO_GEDR3 0x148 /* edge detect [120:96] */ 385 386 /* a bit simpler if we don't support PXA270 */ 387 #define PXA250_GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4)) 388 #define PXA250_GPIO_NPINS 85 389 390 #define PXA270_GPIO_REG(r, pin) \ 391 (pin < 96 ? PXA250_GPIO_REG(r,pin) : ((r) + 0x100 + ((((pin)-96) / 32) * 4))) 392 #define PXA270_GPIO_NPINS 121 393 394 395 #define GPIO_BANK(pin) ((pin) / 32) 396 #define GPIO_BIT(pin) (1u << ((pin) & 0x1f)) 397 #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4)) 398 #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2) 399 400 #define GPIO_IN 0x00 /* Regular GPIO input pin */ 401 #define GPIO_OUT 0x10 /* Regular GPIO output pin */ 402 #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */ 403 #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */ 404 #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */ 405 #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */ 406 #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */ 407 #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */ 408 #define GPIO_SET 0x20 /* Initial state is Set */ 409 #define GPIO_CLR 0x00 /* Initial state is Clear */ 410 411 #define GPIO_FN_MASK 0x03 412 #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT) 413 #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET) 414 #define GPIO_FN(n) ((n) & GPIO_FN_MASK) 415 #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) 416 #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) 417 #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT) 418 419 /* 420 * memory controller 421 */ 422 423 #define MEMCTL_MDCNFG 0x0000 424 #define MDCNFG_DE0 (1<<0) 425 #define MDCNFG_DE1 (1<<1) 426 #define MDCNFD_DWID01_SHIFT 2 427 #define MDCNFD_DCAC01_SHIFT 3 428 #define MDCNFD_DRAC01_SHIFT 5 429 #define MDCNFD_DNB01_SHIFT 7 430 #define MDCNFG_DE2 (1<<16) 431 #define MDCNFG_DE3 (1<<17) 432 #define MDCNFD_DWID23_SHIFT 18 433 #define MDCNFD_DCAC23_SHIFT 19 434 #define MDCNFD_DRAC23_SHIFT 21 435 #define MDCNFD_DNB23_SHIFT 23 436 437 #define MDCNFD_DWID_MASK 0x1 438 #define MDCNFD_DCAC_MASK 0x3 439 #define MDCNFD_DRAC_MASK 0x3 440 #define MDCNFD_DNB_MASK 0x1 441 442 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 443 #define MDREFR_DRI 0xfff 444 #define MDREFR_E0PIN (1<<12) 445 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 446 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 447 #define MDREFR_E1PIN (1<<15) 448 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 449 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 450 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 451 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 452 #define MDREFR_APD (1<<20) /* Auto Power Down */ 453 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 454 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 455 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 456 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 457 458 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 459 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 460 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 461 #define MSC_RBUFF_SHIFT 15 /* return data buffer */ 462 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 463 #define MSC_RRR_SHIFT 12 /* recovery time */ 464 #define MSC_RRR (7<<MSC_RRR_SHIFT) 465 #define MSC_RDN_SHIFT 8 /* ROM delay next access */ 466 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 467 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 468 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 469 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 470 #define MSC_RBW (1<<MSC_RBW_SHIFT) 471 #define MSC_RT_SHIFT 0 /* type */ 472 #define MSC_RT (7<<MSC_RT_SHIFT) 473 #define MSC_RT_NONBURST 0 474 #define MSC_RT_SRAM 1 475 #define MSC_RT_BURST4 2 476 #define MSC_RT_BURST8 3 477 #define MSC_RT_VLIO 4 478 479 /* expansion memory timing configuration */ 480 #define MEMCTL_MCMEM(n) (0x28+4*(n)) 481 #define MEMCTL_MCATT(n) (0x30+4*(n)) 482 #define MEMCTL_MCIO(n) (0x38+4*(n)) 483 484 #define MC_HOLD_SHIFT 14 485 #define MC_ASST_SHIFT 7 486 #define MC_SET_SHIFT 0 487 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 488 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 489 490 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 491 #define MECR_NOS (1<<0) /* Number of sockets */ 492 #define MECR_CIT (1<<1) /* Card-is-there */ 493 494 #define MEMCTL_MDMRS 0x0040 495 496 /* 497 * LCD Controller 498 */ 499 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 500 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 501 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 502 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 503 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 504 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 505 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 506 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 507 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 508 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 509 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 510 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 511 #define LCCR0_BM (1U<<20) /* Branch Mask */ 512 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 513 /* PXA270 */ 514 #define LCCR0_LCDT (1U<<22) /* LCD Panel Type */ 515 #define LCCR0_RDSTM (1U<<23) /* Read Status Interrupt Mask */ 516 #define LCCR0_CMDIM (1U<<24) /* Command Interrupt Mask */ 517 #define LCCR0_OUC (1U<<25) /* Overlay Underlay Control */ 518 #define LCCR0_LDDALT (1U<<26) /* LDD Alternate Mapping Control Bit */ 519 520 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 521 522 523 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 524 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 525 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 526 #define LCCR3_BPP3_SHIFT 29 /* Bits per pixel[3] */ 527 #define LCCR3_BPP3 (0x01<<LCCR3_BPP3_SHIFT) 528 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel[2:0] */ 529 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 530 #define LCDC_LCCR4 0x010 /* Controller Control Register 4 */ 531 #define LCDC_LCCR5 0x014 /* Controller Control Register 5 */ 532 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 533 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 534 #define LCDC_FBR2 0x028 /* DMA ch2 frame branch register */ 535 #define LCDC_FBR3 0x02c /* DMA ch3 frame branch register */ 536 #define LCDC_FBR4 0x030 /* DMA ch4 frame branch register */ 537 #define LCDC_LCSR1 0x034 /* controller status register 1 PXA27x only */ 538 #define LCDC_LCSR 0x038 /* controller status register */ 539 #define LCSR_LDD (1U<<0) /* LCD disable done */ 540 #define LCSR_SOF (1U<<1) /* Start of frame */ 541 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 542 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 543 #define LCDC_TCR 0x044 /* TMED Control Register */ 544 #define LCDC_OVL1C1 0x050 /* Overlay 1 control register 1 */ 545 #define LCDC_OVL1C2 0x060 /* Overlay 1 control register 2 */ 546 #define LCDC_OVL2C1 0x070 /* Overlay 1 control register 1 */ 547 #define LCDC_OVL2C2 0x080 /* Overlay 1 control register 2 */ 548 #define LCDC_CCR 0x090 /* Cursor control register */ 549 #define LCDC_CMDCR 0x100 /* Command control register */ 550 #define LCDC_PRSR 0x104 /* Panel read status register */ 551 #define LCDC_FBR5 0x110 /* DMA ch5 frame branch register */ 552 #define LCDC_FBR6 0x114 /* DMA ch6 frame branch register */ 553 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 554 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 555 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 556 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 557 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 558 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 559 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 560 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 561 #define LCDC_FDADR2 0x220 /* DMA ch2 frame descriptor address */ 562 #define LCDC_FSADR2 0x224 /* DMA ch2 frame source address */ 563 #define LCDC_FIDR2 0x228 /* DMA ch2 frame ID register */ 564 #define LCDC_LDCMD2 0x22c /* DMA ch2 command register */ 565 #define LCDC_FDADR3 0x230 /* DMA ch3 frame descriptor address */ 566 #define LCDC_FSADR3 0x234 /* DMA ch3 frame source address */ 567 #define LCDC_FIDR3 0x238 /* DMA ch3 frame ID register */ 568 #define LCDC_LDCMD3 0x23c /* DMA ch3 command register */ 569 #define LCDC_FDADR4 0x240 /* DMA ch4 frame descriptor address */ 570 #define LCDC_FSADR4 0x244 /* DMA ch4 frame source address */ 571 #define LCDC_FIDR4 0x248 /* DMA ch4 frame ID register */ 572 #define LCDC_LDCMD4 0x24c /* DMA ch4 command register */ 573 #define LCDC_FDADR5 0x250 /* DMA ch5 frame descriptor address */ 574 #define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */ 575 #define LCDC_FIDR5 0x258 /* DMA ch5 frame ID register */ 576 #define LCDC_LDCMD5 0x25c /* DMA ch5 command register */ 577 #define LCDC_FDADR6 0x260 /* DMA ch6 frame descriptor address */ 578 #define LCDC_FSADR6 0x264 /* DMA ch6 frame source address */ 579 #define LCDC_FIDR6 0x268 /* DMA ch6 frame ID register */ 580 #define LCDC_LDCMD6 0x26c /* DMA ch6 command register */ 581 #define LCDC_LCDBSCNTR 0x054 /* LCD buffer strength control register */ 582 583 /* 584 * MMC/SD controller 585 */ 586 #define MMC_STRPCL 0x00 /* start/stop MMC clock */ 587 #define STRPCL_NOOP 0 588 #define STRPCL_STOP 1 /* stop MMC clock */ 589 #define STRPCL_START 2 /* start MMC clock */ 590 #define MMC_STAT 0x04 /* status register */ 591 #define STAT_READ_TIME_OUT (1<<0) 592 #define STAT_TIMEOUT_RESPONSE (1<<1) 593 #define STAT_CRC_WRITE_ERROR (1<<2) 594 #define STAT_CRC_READ_ERROR (1<<3) 595 #define STAT_SPI_READ_ERROR_TOKEN (1<<4) 596 #define STAT_RES_CRC_ERR (1<<5) 597 #define STAT_XMIT_FIFO_EMPTY (1<<6) 598 #define STAT_RECV_FIFO_FULL (1<<7) 599 #define STAT_CLK_EN (1<<8) 600 #define STAT_FLASH_ERR (1<<9) 601 #define STAT_SPI_WR_ERR (1<<10) 602 #define STAT_DATA_TRAN_DONE (1<<11) 603 #define STAT_PRG_DONE (1<<12) 604 #define STAT_END_CMD_RES (1<<13) 605 #define STAT_RD_STALLED (1<<14) 606 #define STAT_SDIO_INT (1<<15) 607 #define STAT_SDIO_SUSPEND_ACK (1<<16) 608 #define STAT_ERR_MASK (STAT_READ_TIME_OUT \ 609 | STAT_TIMEOUT_RESPONSE \ 610 | STAT_CRC_WRITE_ERROR \ 611 | STAT_CRC_READ_ERROR \ 612 | STAT_SPI_READ_ERROR_TOKEN \ 613 | STAT_RES_CRC_ERR \ 614 | STAT_FLASH_ERR \ 615 | STAT_SPI_WR_ERR) 616 #define MMC_CLKRT 0x08 /* MMC clock rate */ 617 #define CLKRT_DIV1 0 618 #define CLKRT_DIV2 1 619 #define CLKRT_DIV4 2 620 #define CLKRT_DIV8 3 621 #define CLKRT_DIV16 4 622 #define CLKRT_DIV32 5 623 #define CLKRT_DIV64 6 624 #define MMC_SPI 0x0c /* SPI mode control */ 625 #define SPI_EN (1<<0) /* enable SPI mode */ 626 #define SPI_CRC_ON (1<<1) /* enable CRC generation */ 627 #define SPI_CS_EN (1<<2) /* Enable CS[01] */ 628 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 629 #define MMC_CMDAT 0x10 /* command/response/data */ 630 #define CMDAT_RESPONSE_FORMAT 0x03 631 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 632 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 633 #define CMDAT_RESPONSE_FORMAT_R2 2 634 #define CMDAT_RESPONSE_FORMAT_R3 3 635 #define CMDAT_DATA_EN (1<<2) 636 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 637 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 638 #define CMDAT_BUSY (1<<5) /* busy signal is expected */ 639 #define CMDAT_INIT (1<<6) /* precede command with 80 clocks */ 640 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 641 #define CMDAT_SD_4DAT (1<<8) /* enable 4bit data transfers */ 642 #define CMDAT_STOP_TRAN (1<<10) /* 1=Stop data transmission */ 643 #define CMDAT_SDIO_INT_EN (1<<11) 644 #define CMDAT_SDIO_SUSPEND (1<<12) 645 #define CMDAT_SDIO_RESUME (1<<13) 646 #define MMC_RESTO 0x14 /* expected response time out */ 647 #define RESTO_MASK 0x7f 648 #define MMC_RDTO 0x18 /* expected data read time out */ 649 #define RDTO_MASK 0xffff 650 #define RDTO_UNIT 13128 /* (ns) */ 651 #define MMC_BLKLEN 0x1c /* block length of data transaction */ 652 #define BLKLEN_MASK 0xfff 653 #define MMC_NOB 0x20 /* number of blocks (block mode) */ 654 #define NOB_MASK 0xffff 655 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 656 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 657 #define MMC_I_MASK 0x28 /* interrupt mask */ 658 #define MMC_I_REG 0x2c /* interrupt register */ 659 #define MMC_I_DATA_TRAN_DONE (1<<0) 660 #define MMC_I_PRG_DONE (1<<1) 661 #define MMC_I_END_CMD_RES (1<<2) 662 #define MMC_I_STOP_CMD (1<<3) 663 #define MMC_I_CLK_IS_OFF (1<<4) 664 #define MMC_I_RXFIFO_RD_REQ (1<<5) 665 #define MMC_I_TXFIFO_WR_REQ (1<<6) 666 #define MMC_I_TINT (1<<7) 667 #define MMC_I_DAT_ERR (1<<8) 668 #define MMC_I_RES_ERR (1<<9) 669 #define MMC_I_RD_STALLED (1<<10) 670 #define MMC_I_SDIO_INT (1<<11) 671 #define MMC_I_SDIO_SUSPEND_ACK (1<<12) 672 #define MMC_I_ALL (0x1fff) 673 #define MMC_CMD 0x30 /* index of current command */ 674 #define CMD_MASK 0x3f 675 #define MMC_ARGH 0x34 /* MSW part of the current command arg */ 676 #define ARGH_MASK 0xffff 677 #define MMC_ARGL 0x38 /* LSW part of the current command arg */ 678 #define ARGL_MASK 0xffff 679 #define MMC_RES 0x3c /* response FIFO */ 680 #define RES_MASK 0xffff 681 #define MMC_RXFIFO 0x40 /* receive FIFO */ 682 #define MMC_TXFIFO 0x44 /* transmit FIFO */ 683 #define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ 684 #define RDWAIT_RD_WAIT_EN (1<<0) 685 #define RDWAIT_WAIT_START (1<<1) 686 #define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ 687 #define CLKS_REM_MASK 0xffff 688 689 #define PXA250_MMC_CLKRT_MIN 312500 690 #define PXA250_MMC_CLKRT_MAX 20000000 691 #define PXA270_MMC_CLKRT_MIN 304688 692 #define PXA270_MMC_CLKRT_MAX 19500000 693 694 /* 695 * Inter-IC Sound (I2S) Controller 696 */ 697 #define I2S_SACR0 0x0000 /* Serial Audio Global Control */ 698 #define SACR0_ENB (1<<0) /* Enable I2S Function */ 699 #define SACR0_BCKD (1<<2) /* I/O Direction of I2S_BITCLK */ 700 #define SACR0_RST (1<<3) /* FIFO Reset */ 701 #define SACR0_EFWR (1<<4) /* Special-Purpose FIFO W/R Func */ 702 #define SACR0_STRF (1<<5) /* Select TX or RX FIFO */ 703 #define SACR0_TFTH_MASK (0xf<<8) /* Trans FIFO Intr/DMA Trig Thresh */ 704 #define SACR0_RFTH_MASK (0xf<<12) /* Recv FIFO Intr/DMA Trig Thresh */ 705 #define SACR0_SET_TFTH(x) (((x) & 0xf)<<8) 706 #define SACR0_SET_RFTH(x) (((x) & 0xf)<<12) 707 #define I2S_SACR1 0x0004 /* Serial Audio I2S/MSB-Justified Control */ 708 #define SACR1_AMSL (1<<0) /* Specify Alt Mode (I2S or MSB) */ 709 #define SACR1_DREC (1<<3) /* Disable Recording Func */ 710 #define SACR1_DRPL (1<<4) /* Disable Replay Func */ 711 #define SACR1_ENLBF (1<<5) /* Enable Interface Loopback Func */ 712 #define I2S_SASR0 0x000c /* Serial Audio I2S/MSB-Justified Status */ 713 #define SASR0_TNF (1<<0) /* Transmit FIFO Not Full */ 714 #define SASR0_RNE (1<<1) /* Recv FIFO Not Empty */ 715 #define SASR0_BSY (1<<2) /* I2S Busy */ 716 #define SASR0_TFS (1<<3) /* Trans FIFO Service Request */ 717 #define SASR0_RFS (1<<4) /* Recv FIFO Service Request */ 718 #define SASR0_TUR (1<<5) /* Trans FIFO Underrun */ 719 #define SASR0_ROR (1<<6) /* Recv FIFO Overrun */ 720 #define SASR0_I2SOFF (1<<7) /* I2S Controller Off */ 721 #define SASR0_TFL_MASK (0xf<<8) /* Trans FIFO Level */ 722 #define SASR0_RFL_MASK (0xf<<12) /* Recv FIFO Level */ 723 #define SASR0_GET_TFL(x) (((x) & 0xf) >> 8) 724 #define SASR0_GET_RFL(x) (((x) & 0xf) >> 12) 725 #define I2S_SAIMR 0x0014 /* Serial Audio Interrupt Mask */ 726 #define SAIMR_TFS (1<<3) /* Enable TX FIFO Service Req Intr */ 727 #define SAIMR_RFS (1<<4) /* Enable RX FIFO Service Req Intr */ 728 #define SAIMR_TUR (1<<5) /* Enable TX FIFO Underrun Intr */ 729 #define SAIMR_ROR (1<<6) /* Enable RX FIFO Overrun Intr */ 730 #define I2S_SAICR 0x0018 /* Serial Audio Interrupt Clear */ 731 #define SAICR_TUR (1<<5) /* Clear Intr and SASR0_TUR */ 732 #define SAICR_ROR (1<<6) /* Clear Intr and SASR0_ROR */ 733 #define I2S_SADIV 0x0060 /* Audio Clock Divider */ 734 #define SADIV_MASK 0x7f 735 #define SADIV_3_058MHz 0x0c /* 3.058 MHz */ 736 #define SADIV_2_836MHz 0x0d /* 2.836 MHz */ 737 #define SADIV_1_405MHz 0x1a /* 1.405 MHz */ 738 #define SADIV_1_026MHz 0x24 /* 1.026 MHz */ 739 #define SADIV_702_75kHz 0x34 /* 702.75 kHz */ 740 #define SADIV_513_25kHz 0x48 /* 513.25 kHz */ 741 #define I2S_SADR 0x0080 /* Serial Audio Data Register */ 742 #define SADR_DTL (0xffff<<0) /* Left Data Sample */ 743 #define SADR_DTH (0xffff<<16) /* Right Data Sample */ 744 745 /* 746 * AC97 747 */ 748 #define AC97_N_CODECS 2 749 #define AC97_GCR 0x000c /* Global control register */ 750 #define GCR_GIE (1<<0) /* interrupt enable */ 751 #define GCR_COLD_RST (1<<1) 752 #define GCR_WARM_RST (1<<2) 753 #define GCR_ACLINK_OFF (1<<3) 754 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 755 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 756 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 757 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 758 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 759 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 760 761 #define AC97_GSR 0x001c /* Global status register */ 762 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 763 #define GSR_MIINT (1<<1) /* modem in interrupt */ 764 #define GSR_MOINT (1<<2) /* modem out interrupt */ 765 #define GSR_PIINT (1<<5) /* PCM in interrupt */ 766 #define GSR_POINT (1<<6) /* PCM out interrupt */ 767 #define GSR_MINT (1<<7) /* Mic in interrupt */ 768 #define GSR_PCR (1<<8) /* primary code ready */ 769 #define GSR_SCR (1<<9) /* secondary code ready */ 770 #define GSR_PRIRES (1<<10) /* primary resume interrupt */ 771 #define GSR_SECRES (1<<11) /* secondary resume interrupt */ 772 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 773 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 774 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 775 #define GSR_RDCS (1<<15) /* Read completion status */ 776 #define GSR_SDONE (1<<18) /* status done */ 777 #define GSR_CDONE (1<<19) /* command done */ 778 779 #define AC97_POCR 0x0000 /* PCM-out control */ 780 #define AC97_PICR 0x0004 /* PCM-in control */ 781 #define AC97_POSR 0x0010 /* PCM-out status */ 782 #define AC97_PISR 0x0014 /* PCM-out status */ 783 #define AC97_MCCR 0x0008 /* MIC-in control register */ 784 #define AC97_MCSR 0x0018 /* MIC-in status register */ 785 #define AC97_MICR 0x0100 /* Modem-in control register */ 786 #define AC97_MISR 0x0108 /* Modem-in status register */ 787 #define AC97_MOCR 0x0110 /* Modem-out control register */ 788 #define AC97_MOSR 0x0118 /* Modem-out status register */ 789 #define AC97_FEFIE (1<<3) /* fifo error interrupt enable */ 790 #define AC97_FIFOE (1<<4) /* fifo error */ 791 792 #define AC97_CAR 0x0020 /* Codec access register */ 793 #define CAR_CAIP (1<<0) /* Codec access in progress */ 794 795 #define AC97_PCDR 0x0040 /* PCM data register */ 796 #define AC97_MCDR 0x0060 /* MIC-in data register */ 797 #define AC97_MODR 0x0140 /* Modem data register */ 798 799 /* address to access codec registers */ 800 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 801 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 802 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 803 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 804 #define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100)) 805 806 /* 807 * USB device controller (PXA250) 808 */ 809 #define USBDC_UDCCR 0x0000 /* UDC control register */ 810 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 811 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 812 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 813 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 814 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 815 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 816 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 817 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 818 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 819 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 820 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 821 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 822 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 823 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 824 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 825 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 826 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 827 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 828 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 829 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 830 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 831 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 832 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 833 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 834 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 835 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 836 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 837 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 838 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 839 840 /* 841 * USB device controller (PXA270) 842 */ 843 #define USBDC_UDCCR 0x0000 /* UDC Control Register */ 844 #define USBDC_UDCCR_UDE (1<<0) /* UDC Enable */ 845 #define USBDC_UDCCR_UDA (1<<1) /* UDC Active */ 846 #define USBDC_UDCCR_UDR (1<<2) /* UDC Resume */ 847 #define USBDC_UDCCR_EMCE (1<<3) /* Endpoint Mem Config Error */ 848 #define USBDC_UDCCR_SMAC (1<<4) /* Switch EndPt Mem to Active Config */ 849 #define USBDC_UDCCR_AAISN (7<<5) /* Active UDC Alt Iface Setting */ 850 #define USBDC_UDCCR_AIN (7<<8) /* Active UDC Iface */ 851 #define USBDC_UDCCR_ACN (7<<11) /* Active UDC Config */ 852 #define USBDC_UDCCR_DWRE (1<<16) /* Device Remote Wake-Up Feature */ 853 #define USBDC_UDCCR_BHNP (1<<28) /* B-Device Host Neg Proto Enable */ 854 #define USBDC_UDCCR_AHNP (1<<29) /* A-Device Host NEg Proto Support */ 855 #define USBDC_UDCCR_AALTHNP (1<<30) /* A-Dev Alt Host Neg Proto Port Sup */ 856 #define USBDC_UDCCR_OEN (1<<31) /* On-The-Go Enable */ 857 #define USBDC_UDCICR0 0x0004 /* UDC Interrupt Control Register 0 */ 858 #define USBDC_UDCICR0_IE(n) (3<<(n)) /* Interrupt Enables */ 859 #define USBDC_UDCICR1 0x0008 /* UDC Interrupt Control Register 1 */ 860 #define USBDC_UDCICR1_IE(n) (3<<(n)) /* Interrupt Enables */ 861 #define USBDC_UDCICR1_IERS (1<<27) /* Interrupt Enable Reset */ 862 #define USBDC_UDCICR1_IESU (1<<28) /* Interrupt Enable Suspend */ 863 #define USBDC_UDCICR1_IERU (1<<29) /* Interrupt Enable Resume */ 864 #define USBDC_UDCICR1_IESOF (1<<30) /* Interrupt Enable Start of Frame */ 865 #define USBDC_UDCICR1_IECC (1<<31) /* Interrupt Enable Config Change */ 866 #define USBDC_UDCISR0 0x000c /* UDC Interrupt Status Register 0 */ 867 #define USBDC_UDCISR0_IR(n) (3<<(n)) /* Interrupt Requests */ 868 #define USBDC_UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */ 869 #define USBDC_UDCISR1_IR(n) (3<<(n)) /* Interrupt Requests */ 870 #define USBDC_UDCISR1_IRRS (1<<27) /* Interrupt Enable Reset */ 871 #define USBDC_UDCISR1_IRSU (1<<28) /* Interrupt Enable Suspend */ 872 #define USBDC_UDCISR1_IRRU (1<<29) /* Interrupt Enable Resume */ 873 #define USBDC_UDCISR1_IRSOF (1<<30) /* Interrupt Enable Start of Frame */ 874 #define USBDC_UDCISR1_IRCC (1<<31) /* Interrupt Enable Config Change */ 875 #define USBDC_UDCFNR 0x0014 /* UDC Frame Number Register */ 876 #define USBDC_UDCFNR_FN (1023<<0) /* Frame Number */ 877 #define USBDC_UDCOTGICR 0x0018 /* UDC OTG Interrupt Control Register */ 878 #define USBDC_UDCOTGICR_IEIDF (1<<0) /* OTG ID Change Fall Intr En */ 879 #define USBDC_UDCOTGICR_IEIDR (1<<1) /* OTG ID Change Ris Intr En */ 880 #define USBDC_UDCOTGICR_IESDF (1<<2) /* OTG A-Dev SRP Detect Fall Intr En */ 881 #define USBDC_UDCOTGICR_IESDR (1<<3) /* OTG A-Dev SRP Detect Ris Intr En */ 882 #define USBDC_UDCOTGICR_IESVF (1<<4) /* OTG Session Valid Fall Intr En */ 883 #define USBDC_UDCOTGICR_IESVR (1<<5) /* OTG Session Valid Ris Intr En */ 884 #define USBDC_UDCOTGICR_IEVV44F (1<<6) /* OTG Vbus Valid 4.4V Fall Intr En */ 885 #define USBDC_UDCOTGICR_IEVV44R (1<<7) /* OTG Vbus Valid 4.4V Ris Intr En */ 886 #define USBDC_UDCOTGICR_IEVV40F (1<<8) /* OTG Vbus Valid 4.0V Fall Intr En */ 887 #define USBDC_UDCOTGICR_IEVV40R (1<<9) /* OTG Vbus Valid 4.0V Ris Intr En */ 888 #define USBDC_UDCOTGICR_IEXF (1<<16) /* Extern Transceiver Intr Fall En */ 889 #define USBDC_UDCOTGICR_IEXR (1<<17) /* Extern Transceiver Intr Ris En */ 890 #define USBDC_UDCOTGICR_IESF (1<<24) /* OTG SET_FEATURE Command Recvd */ 891 #define USBDC_UDCOTGISR 0x001c /* UDC OTG Interrupt Status Register */ 892 #define USBDC_UDCOTGISR_IRIDF (1<<0) /* OTG ID Change Fall Intr Req */ 893 #define USBDC_UDCOTGISR_IRIDR (1<<1) /* OTG ID Change Ris Intr Req */ 894 #define USBDC_UDCOTGISR_IRSDF (1<<2) /* OTG A-Dev SRP Detect Fall Intr Req */ 895 #define USBDC_UDCOTGISR_IRSDR (1<<3) /* OTG A-Dev SRP Detect Ris Intr Req */ 896 #define USBDC_UDCOTGISR_IRSVF (1<<4) /* OTG Session Valid Fall Intr Req */ 897 #define USBDC_UDCOTGISR_IRSVR (1<<5) /* OTG Session Valid Ris Intr Req */ 898 #define USBDC_UDCOTGISR_IRVV44F (1<<6) /* OTG Vbus Valid 4.4V Fall Intr Req */ 899 #define USBDC_UDCOTGISR_IRVV44R (1<<7) /* OTG Vbus Valid 4.4V Ris Intr Req */ 900 #define USBDC_UDCOTGISR_IRVV40F (1<<8) /* OTG Vbus Valid 4.0V Fall Intr Req */ 901 #define USBDC_UDCOTGISR_IRVV40R (1<<9) /* OTG Vbus Valid 4.0V Ris Intr Req */ 902 #define USBDC_UDCOTGISR_IRXF (1<<16) /* Extern Transceiver Intr Fall Req */ 903 #define USBDC_UDCOTGISR_IRXR (1<<17) /* Extern Transceiver Intr Ris Req */ 904 #define USBDC_UDCOTGISR_IRSF (1<<24) /* OTG SET_FEATURE Command Recvd */ 905 #define USBDC_UP2OCR 0x0020 /* USB Port 2 Output Control Register */ 906 #define USBDC_UP2OCR_CPVEN (1<<0) /* Charge Pump Vbus Enable */ 907 #define USBDC_UP2OCR_CPVPE (1<<1) /* Charge Pump Vbus Pulse Enable */ 908 #define USBDC_UP2OCR_DPPDE (1<<2) /* Host Transc D+ Pull Down En */ 909 #define USBDC_UP2OCR_DMPDE (1<<3) /* Host Transc D- Pull Down En */ 910 #define USBDC_UP2OCR_DPPUE (1<<4) /* Host Transc D+ Pull Up En */ 911 #define USBDC_UP2OCR_DMPUE (1<<5) /* Host Transc D- Pull Up En */ 912 #define USBDC_UP2OCR_DPPUBE (1<<6) /* Host Transc D+ Pull Up Bypass En */ 913 #define USBDC_UP2OCR_DMPUBE (1<<7) /* Host Transc D- Pull Up Bypass En */ 914 #define USBDC_UP2OCR_EXSP (1<<8) /* External Transc Speed Control */ 915 #define USBDC_UP2OCR_EXSUS (1<<9) /* External Transc Suspend Control */ 916 #define USBDC_UP2OCR_IDON (1<<10) /* OTG ID Read Enable */ 917 #define USBDC_UP2OCR_HXS (1<<16) /* Host Transc Output Select */ 918 #define USBDC_UP2OCR_HXOE (1<<17) /* Host Transc Output Enable */ 919 #define USBDC_UP2OCR_SEOS (7<<24) /* Single-Ended Output Select */ 920 #define USBDC_UP3OCR 0x0024 /* USB Port 3 Output Control Register */ 921 #define USBDC_UP3OCR_CFG (3<<0) /* Host Port Configuration */ 922 /* 0x0028 to 0x00fc is reserved */ 923 #define USBDC_UDCCSR0 0x0100 /* UDC Endpoint 0 Control/Status Registers */ 924 #define USBDC_UDCCSR0_OPC (1<<0) /* OUT Packet Complete */ 925 #define USBDC_UDCCSR0_IPR (1<<1) /* IN Packet Ready */ 926 #define USBDC_UDCCSR0_FTF (1<<2) /* Flush Transmit FIFO */ 927 #define USBDC_UDCCSR0_DME (1<<3) /* DMA Enable */ 928 #define USBDC_UDCCSR0_SST (1<<4) /* Sent Stall */ 929 #define USBDC_UDCCSR0_FST (1<<5) /* Force Stall */ 930 #define USBDC_UDCCSR0_RNE (1<<6) /* Receive FIFO Not Empty */ 931 #define USBDC_UDCCSR0_SA (1<<7) /* Setup Active */ 932 #define USBDC_UDCCSR0_AREN (1<<8) /* ACK Response Enable */ 933 #define USBDC_UDCCSR0_ACM (1<<9) /* ACK Control Mode */ 934 #define USBDC_UDCCSR(n) (0x0100+4*(n)) /* UDC Control/Status Registers */ 935 #define USBDC_UDCCSR_FS (1<<0) /* FIFO Needs Service */ 936 #define USBDC_UDCCSR_PC (1<<1) /* Packet Complete */ 937 #define USBDC_UDCCSR_TRN (1<<2) /* Tx/Rx NAK */ 938 #define USBDC_UDCCSR_DME (1<<3) /* DMA Enable */ 939 #define USBDC_UDCCSR_SST (1<<4) /* Sent STALL */ 940 #define USBDC_UDCCSR_FST (1<<5) /* Force STALL */ 941 #define USBDC_UDCCSR_BNE (1<<6) /* OUT: Buffer Not Empty */ 942 #define USBDC_UDCCSR_BNF (1<<6) /* IN: Buffer Not Full */ 943 #define USBDC_UDCCSR_SP (1<<7) /* Short Packet Control/Status */ 944 #define USBDC_UDCCSR_FEF (1<<8) /* Flush Endpoint FIFO */ 945 #define USBDC_UDCCSR_DPE (1<<9) /* Data Packet Empty (async EP only) */ 946 /* 0x0160 to 0x01fc is reserved */ 947 #define USBDC_UDCBCR(n) (0x0200+4*(n)) /* UDC Byte Count Registers */ 948 #define USBDC_UDCBCR_BC (1023<<0) /* Byte Count */ 949 /* 0x0260 to 0x02fc is reserved */ 950 #define USBDC_UDCDR(n) (0x0300+4*(n)) /* UDC Data Registers */ 951 /* 0x0360 to 0x03fc is reserved */ 952 /* 0x0400 is reserved */ 953 #define USBDC_UDCECR(n) (0x0400+4*(n)) /* UDC Configuration Registers */ 954 #define USBDC_UDCECR_EE (1<<0) /* Endpoint Enable */ 955 #define USBDC_UDCECR_DE (1<<1) /* Double-Buffering Enable */ 956 #define USBDC_UDCECR_MPE (1023<<2) /* Maximum Packet Size */ 957 #define USBDC_UDCECR_ED (1<<12) /* USB Endpoint Direction */ 958 #define USBDC_UDCECR_ET (3<<13) /* USB Enpoint Type */ 959 #define USBDC_UDCECR_EN (15<<15) /* Endpoint Number */ 960 #define USBDC_UDCECR_AISN (7<<19) /* Alternate Interface Number */ 961 #define USBDC_UDCECR_IN (7<<22) /* Interface Number */ 962 #define USBDC_UDCECR_CN (3<<25) /* Configuration Number */ 963 964 /* 965 * USB Host Controller 966 */ 967 #define USBHC_UHCRHDA 0x0048 /* UHC Root Hub Descriptor A */ 968 #define UHCRHDA_POTPGT_SHIFT 24 /* Power on to power good time */ 969 #define UHCRHDA_NOCP (1<<12) /* No over current protection */ 970 #define UHCRHDA_OCPM (1<<11) /* Over current protection mode */ 971 #define UHCRHDA_DT (1<<10) /* Device type */ 972 #define UHCRHDA_NPS (1<<9) /* No power switching */ 973 #define UHCRHDA_PSM (1<<8) /* Power switching mode */ 974 #define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */ 975 #define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */ 976 #define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */ 977 #define USBHC_UHCHR 0x0064 /* UHC Reset Register */ 978 #define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */ 979 #define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */ 980 #define UHCHR_SSEP1 (1<<9) /* Sleep standby enable for port1 */ 981 #define UHCHR_PCPL (1<<7) /* Power control polarity low */ 982 #define UHCHR_PSPL (1<<6) /* Power sense polarity low */ 983 #define UHCHR_SSE (1<<5) /* Sleep standby enable */ 984 #define UHCHR_UIT (1<<4) /* USB interrupt test */ 985 #define UHCHR_SSDC (1<<3) /* Simulation scale down clock */ 986 #define UHCHR_CGR (1<<2) /* Clock generation reset */ 987 #define UHCHR_FHR (1<<1) /* Force host controller reset */ 988 #define UHCHR_FSBIR (1<<0) /* Force system bus interface reset */ 989 #define UHCHR_MASK 0xeff 990 #define USBHC_STAT 0x0060 /* UHC Status Register */ 991 #define USBHC_STAT_RWUE (1<<7) /* HCI Remote Wake-Up Event */ 992 #define USBHC_STAT_HBA (1<<8) /* HCI Buffer Active */ 993 #define USBHC_STAT_HTA (1<<10) /* HCI Transfer Abort */ 994 #define USBHC_STAT_UPS1 (1<<11) /* USB Power Sense Port 1 */ 995 #define USBHC_STAT_UPS2 (1<<12) /* USB Power Sense Port 2 */ 996 #define USBHC_STAT_UPRI (1<<13) /* USB Port Resume Interrupt */ 997 #define USBHC_STAT_SBTAI (1<<14) /* System Bus Target Abort Interrupt */ 998 #define USBHC_STAT_SBMAI (1<<15) /* System Bus Master Abort Interrupt */ 999 #define USBHC_STAT_UPS3 (1<<16) /* USB Power Sense Port 3 */ 1000 #define USBHC_STAT_MASK (USBHC_STAT_RWUE | USBHC_STAT_HBA | \ 1001 USBHC_STAT_HTA | USBHC_STAT_UPS1 | USBHC_STAT_UPS2 | USBHC_STAT_UPRI | \ 1002 USBHC_STAT_SBTAI | USBHC_STAT_SBMAI | USBHC_STAT_UPS3) 1003 #define USBHC_HR 0x0064 /* UHC Reset Register */ 1004 #define USBHC_HR_FSBIR (1<<0) /* Force System Bus Interface Reset */ 1005 #define USBHC_HR_FHR (1<<1) /* Force Host Controller Reset */ 1006 #define USBHC_HR_CGR (1<<2) /* Clock Generation Reset */ 1007 #define USBHC_HR_SSDC (1<<3) /* Simulation Scale Down Clock */ 1008 #define USBHC_HR_UIT (1<<4) /* USB Interrupt Test */ 1009 #define USBHC_HR_SSE (1<<5) /* Sleep Standby Enable */ 1010 #define USBHC_HR_PSPL (1<<6) /* Power Sense Polarity Low */ 1011 #define USBHC_HR_PCPL (1<<7) /* Power Control Polarity Low */ 1012 #define USBHC_HR_SSEP1 (1<<9) /* Sleep Standby Enable for Port 1 */ 1013 #define USBHC_HR_SSEP2 (1<<10) /* Sleep Standby Enable for Port 2 */ 1014 #define USBHC_HR_SSEP3 (1<<11) /* Sleep Standby Enable for Port 3 */ 1015 #define USBHC_HR_MASK (USBHC_HR_FSBIR | USBHC_HR_FHR | \ 1016 USBHC_HR_CGR | USBHC_HR_SSDC | USBHC_HR_UIT | USBHC_HR_SSE | \ 1017 USBHC_HR_PSPL | USBHC_HR_PCPL | USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | \ 1018 USBHC_HR_SSEP3) 1019 #define USBHC_HIE 0x0068 /* UHC Interrupt Enable Register */ 1020 #define USBHC_HIE_RWIE (1<<7) /* HCI Remote Wake-Up */ 1021 #define USBHC_HIE_HBAIE (1<<8) /* HCI Buffer Active */ 1022 #define USBHC_HIE_TAIE (1<<10) /* HCI Interface Transfer Abort */ 1023 #define USBHC_HIE_UPS1IE (1<<11) /* USB Power Sense Port 1 */ 1024 #define USBHC_HIE_UPS2IE (1<<12) /* USB Power Sense Port 2 */ 1025 #define USBHC_HIE_UPRIE (1<<13) /* USB Port Resume */ 1026 #define USBHC_HIE_UPS3IE (1<<14) /* USB Power Sense Port 3 */ 1027 #define USBHC_HIE_MASK (USBHC_HIE_RWIE | USBHC_HIE_HBAIE | \ 1028 USBHC_HIE_TAIE | USBHC_HIE_UPS1IE | USBHC_HIE_UPS2IE | USBHC_HIE_UPRIE | \ 1029 USBHC_HIE_UPS3IE) 1030 #define USBHC_HIT 0x006C /* UHC Interrupt Test Register */ 1031 #define USBHC_HIT_RWUT (1<<7) /* HCI Remote Wake-Up */ 1032 #define USBHC_HIT_BAT (1<<8) /* HCI Buffer Active */ 1033 #define USBHC_HIT_IRQT (1<<9) /* Normal OHC */ 1034 #define USBHC_HIT_TAT (1<<10) /* HCI Interface Transfer Abort */ 1035 #define USBHC_HIT_UPS1T (1<<11) /* USB Power Sense Port 1 */ 1036 #define USBHC_HIT_UPS2T (1<<12) /* USB Power Sense Port 2 */ 1037 #define USBHC_HIT_UPRT (1<<13) /* USB Port Resume */ 1038 #define USBHC_HIT_STAT (1<<14) /* System Bus Target Abort */ 1039 #define USBHC_HIT_SMAT (1<<15) /* System Bus Master Abort */ 1040 #define USBHC_HIT_UPS3T (1<<16) /* USB Power Sense Port 3 */ 1041 #define USBHC_HIT_MASK (USBHC_HIT_RWUT | USBHC_HIT_BAT | \ 1042 USBHC_HIT_IRQT | USBHC_HIT_TAT | USBHC_HIT_UPS1T | USBHC_HIT_UPS2T | \ 1043 USBHC_HIT_UPRT | USBHC_HIT_STAT | USBHC_HIT_SMAT | USBHC_HIT_UPS3T) 1044 #define USBHC_RST_WAIT 10000 /* usecs to wait for reset */ 1045 1046 /* 1047 * PWM controller 1048 */ 1049 #define PWM_PWMCR 0x0000 /* Control register */ 1050 #define PWM_PWMDCR 0x0004 /* Duty cycle register */ 1051 #define PWM_FD (1<<10) /* Full duty */ 1052 #define PWM_PWMPCR 0x0008 /* Period register */ 1053 1054 /* Synchronous Serial Protocol (SSP) serial ports */ 1055 #define SSP_SSCR0 0x00 1056 #define SSP_SSCR1 0x04 1057 #define SSP_SSSR 0x08 1058 #define SSSR_TNF (1<<2) 1059 #define SSSR_RNE (1<<3) 1060 #define SSP_SSDR 0x10 1061 1062 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 1063
Indexes created Tue Sep 30 20:09:53 GMT 2025