pxa2x0reg.h revision 1.2
1 /* $NetBSD: pxa2x0reg.h,v 1.2 2003/03/18 11:23:03 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCMCIA_SLOT0 0x20000000 66 #define PXA2X0_PCMCIA_SLOT1 0x30000000 67 68 #define PXA2X0_PERIPH_START 0x40000000 69 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 70 #define PXA2X0_PERIPH_END 0x480fffff 71 72 #define PXA2X0_SDRAM0_START 0xa0000000 73 #define PXA2X0_SDRAM1_START 0xa4000000 74 #define PXA2X0_SDRAM2_START 0xa8000000 75 #define PXA2X0_SDRAM3_START 0xac000000 76 77 /* 78 * Physical address of integrated peripherals 79 */ 80 81 #define PXA2X0_DMAC_BASE 0x40000000 82 #define PXA2X0_DMAC_SIZE 0x300 83 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 84 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 85 #define PXA2X0_I2C_BASE 0x40300000 86 #define PXA2X0_I2C_SIZE 0x000016a4 87 #define PXA2X0_I2S_BASE 0x40400000 88 #define PXA2X0_AC97_BASE 0x40500000 89 #define PXA2X0_AC97_SIZE 0x3fc 90 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client */ 91 #define PXA2X0_USBDC_SIZE 0x0e04 92 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 93 #define PXA2X0_ICP_BASE 0x40800000 94 #define PXA2X0_RTC_BASE 0x40900000 95 #define PXA2X0_RTC_SIZE 0x10 96 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 97 #define PXA2X0_PWM0_BASE 0x40b00000 98 #define PXA2X0_PWM1_BASE 0x40c00000 99 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 100 #define PXA2X0_INTCTL_SIZE 0x20 101 #define PXA2X0_GPIO_BASE 0x40e00000 102 #define PXA2X0_GPIO_SIZE 0x70 103 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 104 #define PXA2X0_SSP_BASE 0x41000000 105 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 106 #define PXA2X0_MMC_SIZE 0x48 107 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 108 #define PXA2X0_CLKMAN_SIZE 12 109 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 110 #define PXA2X0_LCDC_SIZE 0x220 111 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 112 #define PXA2X0_MEMCTL_SIZE 0x48 113 114 /* width of interrupt controller */ 115 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 116 #define ICU_INT_HWMASK 0xffffff00 117 #define PXA2X0_IRQ_MIN 8 /* 0..7 are not used by integrated 118 peripherals */ 119 120 #define PXA2X0_INT_GPIO0 8 121 #define PXA2X0_INT_GPIO1 9 122 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 123 #define PXA2X0_INT_USB 11 124 #define PXA2X0_INT_PMU 12 125 #define PXA2X0_INT_I2S 13 126 #define PXA2X0_INT_AC97 14 127 #define PXA2X0_INT_LCD 17 128 #define PXA2X0_INT_I2C 18 129 #define PXA2X0_INT_ICP 19 130 #define PXA2X0_INT_STUART 20 131 #define PXA2X0_INT_BTUART 21 132 #define PXA2X0_INT_FFUART 22 133 #define PXA2X0_INT_MMC 23 134 #define PXA2X0_INT_SSP 24 135 #define PXA2X0_INT_DMA 25 136 #define PXA2X0_INT_OST0 26 137 #define PXA2X0_INT_OST1 27 138 #define PXA2X0_INT_OST2 28 139 #define PXA2X0_INT_OST3 29 140 #define PXA2X0_INT_RTCHZ 30 141 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 142 143 /* DMAC */ 144 #define DMAC_N_CHANNELS 16 145 146 #define DMAC_DCSR(n) ((n)*4) 147 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 148 #define DCSR_STARTINR (1<<1) /* start interrupt */ 149 #define DCSR_ENDINTR (1<<2) /* end interrupt */ 150 #define DCSR_STOPSTATE (1<<3) /* channel is not running */ 151 #define DCSR_REQPEND (1<<8) /* request pending */ 152 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 153 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 154 #define DCSR_RUN (1<<31) 155 #define DMAC_DINT 0x00f0 /* DAM interrupt */ 156 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 157 #define DRCMR_CHLNUM 0x0f /* channel number */ 158 #define DRCMR_MAPVLD (1<<7) /* map valid */ 159 #define DMAC_DDADR(n) (0x0200+(n)*16) 160 #define DDADR_STOP (1<<0) 161 #define DMAC_DSADR(n) (0x0204+(n)*16) 162 #define DMAC_DTADR(n) (0x0208+(n)*16) 163 #define DMAC_DCMD(n) (0x020c+(n)*16) 164 #define DCMD_LENGTH 0x1fff 165 #define DCMD_WIDTH_SHIFT 14 166 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 167 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 168 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 169 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 170 #define DCMD_SIZE_SHIFT 16 171 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 172 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 173 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 174 #define DCMD_LITTLE_ENDIEN (0<<18) 175 #define DCMD_ENDIRQEN (1<<21) 176 #define DCMD_STARTIRQEN (1<<22) 177 #define DCMD_FLOWTRG (1<<28) /* flow control by target */ 178 #define DCMD_FLOWSRC (1<<29) /* flow control by source */ 179 #define DCMD_INCTRGADDR (1<<30) /* increment target address */ 180 #define DCMD_INCSRCADDR (1<<31) /* increment source address */ 181 182 /* DMA request index */ 183 #define DMAC_MAP_DREQ0 0 184 #define DMAC_MAP_DREQ1 1 185 #define DMAC_MAP_I2SRX 2 186 #define DMAC_MAP_I2STX 3 187 #define DMAC_MAP_BTURARTX 4 188 /* ... */ 189 #define DMAC_MAP_AC97MODEMRX 9 190 #define DMAC_MAP_AC97MODEMTX 10 191 #define DMAC_MAP_AC97AUDIORX 11 192 #define DMAC_MAP_AC97AUDIOTX 12 193 /* ... */ 194 #define DMAC_MAP_USBEP(n) (24+(n)) /* for endpoint 1..4,6..9,11..14 */ 195 196 197 #ifndef __ASSEMBLER__ 198 /* DMA descriptor */ 199 struct pxa2x0_dma_desc { 200 uint32_t dd_ddadr; 201 uint32_t dd_dsadr; 202 uint32_t dd_dtadr; 203 uint32_t dd_dcmd; /* command and length */ 204 }; 205 #endif 206 207 /* UART */ 208 #define PXA2X0_COM_FREQ 14745600L 209 210 /* I2C */ 211 #define I2C_IBMR 0x1680 /* Bus monitor register */ 212 #define I2C_IDBR 0x1688 /* Data buffer */ 213 #define I2C_ICR 0x1690 /* Control register */ 214 #define ICR_START (1<<0) 215 #define ICR_STOP (1<<1) 216 #define ICR_ACKNAK (1<<2) 217 #define ICR_TB (1<<3) 218 #define ICR_MA (1<<4) 219 #define I2C_ISR 0x1698 /* Status register */ 220 #define I2C_ISAR 0x16a0 /* Slave address */ 221 222 /* Clock Manager */ 223 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 224 #define CCCR_TURBO_X1 (2<<7) 225 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 226 #define CCCR_TURBO_X2 (4<<7) 227 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 228 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 229 #define CCCR_RUN_X1 (1<<5) 230 #define CCCR_RUN_X2 (2<<5) 231 #define CCCR_RUN_X4 (3<<5) 232 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 233 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 234 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 235 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 236 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 237 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 238 239 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 240 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 241 242 #define CCCR_N_SHIFT 7 243 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 244 #define CCCR_M_SHIFT 5 245 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 246 #define CCCR_L_MASK 0x1f 247 248 #define CKEN_PWM0 (1<<0) 249 #define CKEN_PWM1 (1<<1) 250 #define CKEN_AC97 (1<<2) 251 #define CKEN_SSP (1<<3) 252 #define CKEN_STUART (1<<5) 253 #define CKEN_FFUART (1<<6) 254 #define CKEN_BTUART (1<<7) 255 #define CKEN_I2S (1<<8) 256 #define CKEN_USB (1<<11) 257 #define CKEN_MMC (1<<12) 258 #define CKEN_FICP (1<<13) 259 #define CKEN_I2C (1<<14) 260 #define CKEN_LCD (1<<16) 261 262 #define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */ 263 #define OSCC_OON (1<<1) /* 32.768KHz oscillator */ 264 265 /* 266 * RTC 267 */ 268 #define RTC_RCNR 0x0000 /* count register */ 269 #define RTC_RTAR 0x0004 /* alarm register */ 270 #define RTC_RTSR 0x0008 /* status register */ 271 #define RTC_RTTR 0x000c /* trim register */ 272 /* 273 * GPIO 274 */ 275 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 276 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 277 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 278 279 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 280 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 281 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 282 283 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 284 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 285 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 286 287 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 288 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 289 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 290 291 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 292 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 293 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 294 295 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 296 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 297 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 298 299 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 300 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 301 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 302 303 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 304 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 305 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 306 307 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 308 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 309 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 310 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 311 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 312 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 313 314 /* 315 * memory controller 316 */ 317 318 #define MEMCTL_MDCNFG 0x0000 319 #define MDCNFG_DE0 (1<<0) 320 #define MDCNFG_DE1 (1<<1) 321 #define MDCNFG_DE2 (1<<16) 322 #define MDCNFG_DE3 (1<<17) 323 324 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 325 #define MDREFR_DRI 0xfff 326 #define MDREFR_E0PIN (1<<12) 327 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 328 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 329 #define MDREFR_E1PIN (1<<15) 330 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 331 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 332 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 333 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 334 #define MDREFR_APD (1<<20) /* Auto Power Down */ 335 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 336 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 337 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 338 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 339 340 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 341 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 342 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 343 #define MSC_RBUFF_SHIFT 15 /* return data buffer */ 344 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 345 #define MSC_RRR_SHIFT 12 /* recovery time */ 346 #define MSC_RRR (7<<MSC_RRR_SHIFT) 347 #define MSC_RDN_SHIFT 8 /* ROM delay next access */ 348 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 349 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 350 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 351 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 352 #define MSC_RBW (1<<MSC_RBW_SHIFT) 353 #define MSC_RT_SHIFT 0 /* type */ 354 #define MSC_RT (7<<MSC_RT_SHIFT) 355 #define MSC_RT_NONBURST 0 356 #define MSC_RT_SRAM 1 357 #define MSC_RT_BURST4 2 358 #define MSC_RT_BURST8 3 359 #define MSC_RT_VLIO 4 360 361 /* expansion memory timing configuration */ 362 #define MEMCTL_MCMEM(n) (0x28+4*(n)) 363 #define MEMCTL_MCATT(n) (0x30+4*(n)) 364 #define MEMCTL_MCIO(n) (0x38+4*(n)) 365 366 #define MC_HOLD_SHIFT 14 367 #define MC_ASST_SHIFT 7 368 #define MC_SET_SHIFT 0 369 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 370 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 371 372 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 373 #define MECR_NOS (1<<0) /* Number of sockets */ 374 #define MECR_CIT (1<<1) /* Card-is-there */ 375 376 #define MEMCTL_MDMRS 0x0040 377 378 /* 379 * LCD Controller 380 */ 381 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 382 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 383 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 384 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 385 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 386 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 387 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 388 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 389 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 390 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 391 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 392 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 393 #define LCCR0_BM (1U<<20) /* Branch Mask */ 394 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 395 396 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 397 398 399 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 400 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 401 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 402 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 403 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 404 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 405 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 406 #define LCDC_LCSR 0x038 /* controller status register */ 407 #define LCSR_LDD (1U<<0) /* LCD disable done */ 408 #define LCSR_SOF (1U<<1) /* Start of frame */ 409 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 410 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 411 #define LCDC_TCR 0x044 /* TMED Control Register */ 412 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 413 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 414 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 415 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 416 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 417 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 418 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 419 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 420 421 /* 422 * MMC/SD controller 423 */ 424 #define MMC_STRPCL 0x00 /* start/stop MMC clock */ 425 #define STRPCL_NOOP 0 426 #define STRPCL_STOP 1 /* stop MMC clock */ 427 #define STRPCL_START 2 /* start MMC clock */ 428 #define MMC_STAT 0x04 /* status register */ 429 #define STAT_READ_TIME_OUT (1<<0) 430 #define STAT_TIMEOUT_RESPONSE (1<<1) 431 #define STAT_CRC_WRITE_ERROR (1<<2) 432 #define STAT_CRC_READ_ERROR (1<<3) 433 #define STAT_SPI_READ_ERROR_TOKEN (1<<4) 434 #define STAT_RES_CRC_ERR (1<<5) 435 #define STAT_XMIT_FIFO_EMPTY (1<<6) 436 #define STAT_RECV_FIFO_FULL (1<<7) 437 #define STAT_CLK_EN (1<<8) 438 #define STAT_DATA_TRAN_DONE (1<<11) 439 #define STAT_PRG_DONE (1<<12) 440 #define STAT_END_CMD_RES (1<<13) 441 #define MMC_CLKRT 0x08 /* MMC clock rate */ 442 #define CLKRT_20M 0 443 #define CLKRT_10M 1 444 #define CLKRT_5M 2 445 #define CLKRT_2_5M 3 446 #define CLKRT_1_25M 4 447 #define CLKRT_625K 5 448 #define CLKRT_312K 6 449 #define MMC_SPI 0x0c /* SPI mode control */ 450 #define SPI_EN (1<<0) /* enable SPI mode */ 451 #define SPI_CRC_ON (1<<1) /* enable CRC generation */ 452 #define SPI_CS_EN (1<<2) /* Enable CS[01] */ 453 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 454 #define MMC_CMDAT 0x10 /* command/response/data */ 455 #define CMDAT_RESPONSE_FORMAT 0x03 456 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 457 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 458 #define CMDAT_RESPONSE_FORMAT_R2 2 459 #define CMDAT_RESPONSE_FORMAT_R3 3 460 #define CMDAT_DATA_EN (1<<2) 461 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 462 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 463 #define CMDAT_BUSY (1<<5) /* busy signal is expected */ 464 #define CMDAT_INIT (1<<6) /* preceede command with 80 clocks */ 465 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 466 #define MMC_RESTO 0x14 /* expected response time out */ 467 #define MMC_RDTO 0x18 /* expected data read time out */ 468 #define MMC_BLKLEN 0x1c /* block length of data transaction */ 469 #define MMC_NOB 0x20 /* number of blocks (block mode) */ 470 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 471 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 472 #define MMC_I_MASK 0x28 /* interrupt mask */ 473 #define MMC_I_REG 0x2c /* interrupt register */ 474 #define MMC_I_DATA_TRAN_DONE (1<<0) 475 #define MMC_I_PRG_DONE (1<<1) 476 #define MMC_I_END_CMD_RES (1<<2) 477 #define MMC_I_STOP_CMD (1<<3) 478 #define MMC_I_CLK_IS_OFF (1<<4) 479 #define MMC_I_RXFIFO_RD_REQ (1<<5) 480 #define MMC_I_TXFIFO_WR_REQ (1<<6) 481 #define MMC_CMD 0x30 /* index of current command */ 482 #define MMC_ARGH 0x34 /* MSW part of the current command arg */ 483 #define MMC_ARGL 0x38 /* LSW part of the current command arg */ 484 #define MMC_RES 0x3c /* response FIFO */ 485 #define MMC_RXFIFO 0x40 /* receive FIFO */ 486 #define MMC_TXFIFO 0x44 /* transmit FIFO */ 487 488 /* 489 * AC97 490 */ 491 #define AC97_GCR 0x000c /* Global control register */ 492 #define GCR_GIE (1<<0) /* interrupt enable */ 493 #define GCR_COLD_RST (1<<1) 494 #define GCR_WARM_RST (1<<2) 495 #define GCR_ACLINK_OFF (1<<3) 496 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 497 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 498 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 499 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 500 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 501 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 502 503 #define AC97_GSR 0x001c /* Global status register */ 504 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 505 #define GSR_MIINT (1<<1) /* modem in interrupt */ 506 #define GSR_MOINT (1<<2) /* modem out interrupt */ 507 #define GSR_PIINT (1<<5) /* PCM in interrupt */ 508 #define GSR_POINT (1<<6) /* PCM in interrupt */ 509 #define GSR_MINT (1<<7) /* Mic in interrupt */ 510 #define GSR_PCR (1<<8) /* primary code ready */ 511 #define GSR_SCR (1<<9) /* secondary code ready */ 512 #define GSR_PRIRES (1<<10) /* primary resume interrupt */ 513 #define GSR_SECRES (1<<11) /* secondary resume interrupt */ 514 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 515 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 516 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 517 #define GSR_RDCS (1<<15) /* Read completion status */ 518 #define GSR_SDONE (1<<18) /* status done */ 519 #define GSR_CDONE (1<<19) /* command done */ 520 521 #define AC97_POCR 0x0000 /* PCM-out control */ 522 #define AC97_PICR 0x0004 /* PCM-in control */ 523 #define AC97_POSR 0x0010 /* PCM-out status */ 524 #define AC97_PISR 0x0014 /* PCM-out status */ 525 #define AC97_MCCR 0x0008 /* MIC-in control register */ 526 #define AC97_MCSR 0x0018 /* MIC-in status register */ 527 #define AC97_MICR 0x0100 /* Modem-in control register */ 528 #define AC97_MISR 0x0108 /* Modem-in status register */ 529 #define AC97_MOCR 0x0110 /* Modem-in control register */ 530 #define AC97_MOSR 0x0118 /* Modem-out status register */ 531 #define AC97_FIFOE (1<<4) /* fifo error */ 532 533 #define AC97_CAR 0x0020 /* Codec access register */ 534 #define CAR_CAIP (1<<0) /* Codec access in progress */ 535 536 #define AC97_PCDR 0x0040 /* PCM data register */ 537 #define AC97_MCDR 0x0060 /* MIC-in data register */ 538 #define AC97_MODR 0x0060 /* Modem data register */ 539 540 /* address to access codec registers */ 541 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 542 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 543 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 544 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 545 546 /* 547 * USB device controller 548 */ 549 #define USBDC_UDCCR 0x0000 /* UDC control register */ 550 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 551 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 552 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 553 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 554 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 555 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 556 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 557 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 558 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 559 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 560 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 561 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 562 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 563 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 564 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 565 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 566 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 567 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 568 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 569 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 570 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 571 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 572 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 573 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 574 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 575 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 576 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 577 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 578 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 579 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 580
Indexes created Tue Sep 30 11:09:46 GMT 2025