pxa2x0reg.h revision 1.3
1 /* $NetBSD: pxa2x0reg.h,v 1.3 2003/06/05 13:48:28 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCMCIA_SLOT0 0x20000000 66 #define PXA2X0_PCMCIA_SLOT1 0x30000000 67 68 #define PXA2X0_PERIPH_START 0x40000000 69 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 70 #define PXA2X0_PERIPH_END 0x480fffff 71 72 #define PXA2X0_SDRAM0_START 0xa0000000 73 #define PXA2X0_SDRAM1_START 0xa4000000 74 #define PXA2X0_SDRAM2_START 0xa8000000 75 #define PXA2X0_SDRAM3_START 0xac000000 76 #define PXA2X0_SDRAM_BANKS 4 77 #define PXA2X0_SDRAM_BANK_SIZE 0x04000000 78 79 /* 80 * Physical address of integrated peripherals 81 */ 82 83 #define PXA2X0_DMAC_BASE 0x40000000 84 #define PXA2X0_DMAC_SIZE 0x300 85 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 86 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 87 #define PXA2X0_I2C_BASE 0x40300000 88 #define PXA2X0_I2C_SIZE 0x000016a4 89 #define PXA2X0_I2S_BASE 0x40400000 90 #define PXA2X0_AC97_BASE 0x40500000 91 #define PXA2X0_AC97_SIZE 0x600 92 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client */ 93 #define PXA2X0_USBDC_SIZE 0x0e04 94 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 95 #define PXA2X0_ICP_BASE 0x40800000 96 #define PXA2X0_RTC_BASE 0x40900000 97 #define PXA2X0_RTC_SIZE 0x10 98 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 99 #define PXA2X0_PWM0_BASE 0x40b00000 100 #define PXA2X0_PWM1_BASE 0x40c00000 101 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 102 #define PXA2X0_INTCTL_SIZE 0x20 103 #define PXA2X0_GPIO_BASE 0x40e00000 104 #define PXA2X0_GPIO_SIZE 0x70 105 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 106 #define PXA2X0_SSP_BASE 0x41000000 107 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 108 #define PXA2X0_MMC_SIZE 0x48 109 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 110 #define PXA2X0_CLKMAN_SIZE 12 111 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 112 #define PXA2X0_LCDC_SIZE 0x220 113 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 114 #define PXA2X0_MEMCTL_SIZE 0x48 115 116 /* width of interrupt controller */ 117 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 118 #define ICU_INT_HWMASK 0xffffff00 119 #define PXA2X0_IRQ_MIN 8 /* 0..7 are not used by integrated 120 peripherals */ 121 122 #define PXA2X0_INT_GPIO0 8 123 #define PXA2X0_INT_GPIO1 9 124 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 125 #define PXA2X0_INT_USB 11 126 #define PXA2X0_INT_PMU 12 127 #define PXA2X0_INT_I2S 13 128 #define PXA2X0_INT_AC97 14 129 #define PXA2X0_INT_LCD 17 130 #define PXA2X0_INT_I2C 18 131 #define PXA2X0_INT_ICP 19 132 #define PXA2X0_INT_STUART 20 133 #define PXA2X0_INT_BTUART 21 134 #define PXA2X0_INT_FFUART 22 135 #define PXA2X0_INT_MMC 23 136 #define PXA2X0_INT_SSP 24 137 #define PXA2X0_INT_DMA 25 138 #define PXA2X0_INT_OST0 26 139 #define PXA2X0_INT_OST1 27 140 #define PXA2X0_INT_OST2 28 141 #define PXA2X0_INT_OST3 29 142 #define PXA2X0_INT_RTCHZ 30 143 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 144 145 /* DMAC */ 146 #define DMAC_N_CHANNELS 16 147 #define DMAC_N_PRIORITIES 3 148 149 #define DMAC_DCSR(n) ((n)*4) 150 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 151 #define DCSR_STARTINR (1<<1) /* start interrupt */ 152 #define DCSR_ENDINTR (1<<2) /* end interrupt */ 153 #define DCSR_STOPSTATE (1<<3) /* channel is not running */ 154 #define DCSR_REQPEND (1<<8) /* request pending */ 155 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 156 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 157 #define DCSR_RUN (1<<31) 158 #define DMAC_DINT 0x00f0 /* DAM interrupt */ 159 #define DMAC_DINT_MASK 0xffffu 160 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 161 #define DRCMR_CHLNUM 0x0f /* channel number */ 162 #define DRCMR_MAPVLD (1<<7) /* map valid */ 163 #define DMAC_DDADR(n) (0x0200+(n)*16) 164 #define DDADR_STOP (1<<0) 165 #define DMAC_DSADR(n) (0x0204+(n)*16) 166 #define DMAC_DTADR(n) (0x0208+(n)*16) 167 #define DMAC_DCMD(n) (0x020c+(n)*16) 168 #define DCMD_LENGTH_MASK 0x1fff 169 #define DCMD_WIDTH_SHIFT 14 170 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 171 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 172 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 173 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 174 #define DCMD_SIZE_SHIFT 16 175 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 176 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 177 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 178 #define DCMD_LITTLE_ENDIEN (0<<18) 179 #define DCMD_ENDIRQEN (1<<21) 180 #define DCMD_STARTIRQEN (1<<22) 181 #define DCMD_FLOWTRG (1<<28) /* flow control by target */ 182 #define DCMD_FLOWSRC (1<<29) /* flow control by source */ 183 #define DCMD_INCTRGADDR (1<<30) /* increment target address */ 184 #define DCMD_INCSRCADDR (1<<31) /* increment source address */ 185 186 #ifndef __ASSEMBLER__ 187 /* DMA descriptor */ 188 struct pxa2x0_dma_desc { 189 volatile uint32_t dd_ddadr; 190 #define DMAC_DESC_LAST 0x1 191 volatile uint32_t dd_dsadr; 192 volatile uint32_t dd_dtadr; 193 volatile uint32_t dd_dcmd; /* command and length */ 194 }; 195 #endif 196 197 /* UART */ 198 #define PXA2X0_COM_FREQ 14745600L 199 200 /* I2C */ 201 #define I2C_IBMR 0x1680 /* Bus monitor register */ 202 #define I2C_IDBR 0x1688 /* Data buffer */ 203 #define I2C_ICR 0x1690 /* Control register */ 204 #define ICR_START (1<<0) 205 #define ICR_STOP (1<<1) 206 #define ICR_ACKNAK (1<<2) 207 #define ICR_TB (1<<3) 208 #define ICR_MA (1<<4) 209 #define I2C_ISR 0x1698 /* Status register */ 210 #define I2C_ISAR 0x16a0 /* Slave address */ 211 212 /* Clock Manager */ 213 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 214 #define CCCR_TURBO_X1 (2<<7) 215 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 216 #define CCCR_TURBO_X2 (4<<7) 217 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 218 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 219 #define CCCR_RUN_X1 (1<<5) 220 #define CCCR_RUN_X2 (2<<5) 221 #define CCCR_RUN_X4 (3<<5) 222 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 223 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 224 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 225 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 226 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 227 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 228 229 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 230 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 231 232 #define CCCR_N_SHIFT 7 233 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 234 #define CCCR_M_SHIFT 5 235 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 236 #define CCCR_L_MASK 0x1f 237 238 #define CKEN_PWM0 (1<<0) 239 #define CKEN_PWM1 (1<<1) 240 #define CKEN_AC97 (1<<2) 241 #define CKEN_SSP (1<<3) 242 #define CKEN_STUART (1<<5) 243 #define CKEN_FFUART (1<<6) 244 #define CKEN_BTUART (1<<7) 245 #define CKEN_I2S (1<<8) 246 #define CKEN_USB (1<<11) 247 #define CKEN_MMC (1<<12) 248 #define CKEN_FICP (1<<13) 249 #define CKEN_I2C (1<<14) 250 #define CKEN_LCD (1<<16) 251 252 #define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */ 253 #define OSCC_OON (1<<1) /* 32.768KHz oscillator */ 254 255 /* 256 * RTC 257 */ 258 #define RTC_RCNR 0x0000 /* count register */ 259 #define RTC_RTAR 0x0004 /* alarm register */ 260 #define RTC_RTSR 0x0008 /* status register */ 261 #define RTC_RTTR 0x000c /* trim register */ 262 /* 263 * GPIO 264 */ 265 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 266 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 267 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 268 269 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 270 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 271 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 272 273 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 274 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 275 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 276 277 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 278 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 279 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 280 281 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 282 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 283 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 284 285 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 286 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 287 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 288 289 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 290 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 291 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 292 293 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 294 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 295 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 296 297 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 298 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 299 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 300 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 301 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 302 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 303 304 #define GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4)) 305 #define GPIO_BANK(pin) ((pin) / 32) 306 #define GPIO_BIT(pin) (1u << ((pin) & 0x1f)) 307 #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4)) 308 #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2) 309 310 #define GPIO_IN 0x00 /* Regular GPIO input pin */ 311 #define GPIO_OUT 0x10 /* Regular GPIO output pin */ 312 #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */ 313 #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */ 314 #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */ 315 #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */ 316 #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */ 317 #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */ 318 #define GPIO_SET 0x20 /* Initial state is Set */ 319 #define GPIO_CLR 0x00 /* Initial state is Clear */ 320 321 #define GPIO_FN_MASK 0x03 322 #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT) 323 #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET) 324 #define GPIO_FN(n) ((n) & GPIO_FN_MASK) 325 #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) 326 #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) 327 #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT) 328 329 #define GPIO_NPINS 81 330 331 /* 332 * memory controller 333 */ 334 335 #define MEMCTL_MDCNFG 0x0000 336 #define MDCNFG_DE0 (1<<0) 337 #define MDCNFG_DE1 (1<<1) 338 #define MDCNFD_DWID01_SHIFT 2 339 #define MDCNFD_DCAC01_SHIFT 3 340 #define MDCNFD_DRAC01_SHIFT 5 341 #define MDCNFD_DNB01_SHIFT 7 342 #define MDCNFG_DE2 (1<<16) 343 #define MDCNFG_DE3 (1<<17) 344 #define MDCNFD_DWID23_SHIFT 18 345 #define MDCNFD_DCAC23_SHIFT 19 346 #define MDCNFD_DRAC23_SHIFT 21 347 #define MDCNFD_DNB23_SHIFT 23 348 349 #define MDCNFD_DWID_MASK 0x1 350 #define MDCNFD_DCAC_MASK 0x3 351 #define MDCNFD_DRAC_MASK 0x3 352 #define MDCNFD_DNB_MASK 0x1 353 354 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 355 #define MDREFR_DRI 0xfff 356 #define MDREFR_E0PIN (1<<12) 357 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 358 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 359 #define MDREFR_E1PIN (1<<15) 360 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 361 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 362 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 363 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 364 #define MDREFR_APD (1<<20) /* Auto Power Down */ 365 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 366 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 367 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 368 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 369 370 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 371 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 372 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 373 #define MSC_RBUFF_SHIFT 15 /* return data buffer */ 374 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 375 #define MSC_RRR_SHIFT 12 /* recovery time */ 376 #define MSC_RRR (7<<MSC_RRR_SHIFT) 377 #define MSC_RDN_SHIFT 8 /* ROM delay next access */ 378 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 379 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 380 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 381 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 382 #define MSC_RBW (1<<MSC_RBW_SHIFT) 383 #define MSC_RT_SHIFT 0 /* type */ 384 #define MSC_RT (7<<MSC_RT_SHIFT) 385 #define MSC_RT_NONBURST 0 386 #define MSC_RT_SRAM 1 387 #define MSC_RT_BURST4 2 388 #define MSC_RT_BURST8 3 389 #define MSC_RT_VLIO 4 390 391 /* expansion memory timing configuration */ 392 #define MEMCTL_MCMEM(n) (0x28+4*(n)) 393 #define MEMCTL_MCATT(n) (0x30+4*(n)) 394 #define MEMCTL_MCIO(n) (0x38+4*(n)) 395 396 #define MC_HOLD_SHIFT 14 397 #define MC_ASST_SHIFT 7 398 #define MC_SET_SHIFT 0 399 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 400 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 401 402 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 403 #define MECR_NOS (1<<0) /* Number of sockets */ 404 #define MECR_CIT (1<<1) /* Card-is-there */ 405 406 #define MEMCTL_MDMRS 0x0040 407 408 /* 409 * LCD Controller 410 */ 411 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 412 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 413 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 414 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 415 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 416 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 417 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 418 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 419 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 420 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 421 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 422 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 423 #define LCCR0_BM (1U<<20) /* Branch Mask */ 424 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 425 426 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 427 428 429 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 430 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 431 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 432 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 433 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 434 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 435 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 436 #define LCDC_LCSR 0x038 /* controller status register */ 437 #define LCSR_LDD (1U<<0) /* LCD disable done */ 438 #define LCSR_SOF (1U<<1) /* Start of frame */ 439 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 440 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 441 #define LCDC_TCR 0x044 /* TMED Control Register */ 442 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 443 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 444 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 445 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 446 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 447 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 448 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 449 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 450 451 /* 452 * MMC/SD controller 453 */ 454 #define MMC_STRPCL 0x00 /* start/stop MMC clock */ 455 #define STRPCL_NOOP 0 456 #define STRPCL_STOP 1 /* stop MMC clock */ 457 #define STRPCL_START 2 /* start MMC clock */ 458 #define MMC_STAT 0x04 /* status register */ 459 #define STAT_READ_TIME_OUT (1<<0) 460 #define STAT_TIMEOUT_RESPONSE (1<<1) 461 #define STAT_CRC_WRITE_ERROR (1<<2) 462 #define STAT_CRC_READ_ERROR (1<<3) 463 #define STAT_SPI_READ_ERROR_TOKEN (1<<4) 464 #define STAT_RES_CRC_ERR (1<<5) 465 #define STAT_XMIT_FIFO_EMPTY (1<<6) 466 #define STAT_RECV_FIFO_FULL (1<<7) 467 #define STAT_CLK_EN (1<<8) 468 #define STAT_DATA_TRAN_DONE (1<<11) 469 #define STAT_PRG_DONE (1<<12) 470 #define STAT_END_CMD_RES (1<<13) 471 #define MMC_CLKRT 0x08 /* MMC clock rate */ 472 #define CLKRT_20M 0 473 #define CLKRT_10M 1 474 #define CLKRT_5M 2 475 #define CLKRT_2_5M 3 476 #define CLKRT_1_25M 4 477 #define CLKRT_625K 5 478 #define CLKRT_312K 6 479 #define MMC_SPI 0x0c /* SPI mode control */ 480 #define SPI_EN (1<<0) /* enable SPI mode */ 481 #define SPI_CRC_ON (1<<1) /* enable CRC generation */ 482 #define SPI_CS_EN (1<<2) /* Enable CS[01] */ 483 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 484 #define MMC_CMDAT 0x10 /* command/response/data */ 485 #define CMDAT_RESPONSE_FORMAT 0x03 486 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 487 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 488 #define CMDAT_RESPONSE_FORMAT_R2 2 489 #define CMDAT_RESPONSE_FORMAT_R3 3 490 #define CMDAT_DATA_EN (1<<2) 491 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 492 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 493 #define CMDAT_BUSY (1<<5) /* busy signal is expected */ 494 #define CMDAT_INIT (1<<6) /* preceede command with 80 clocks */ 495 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 496 #define MMC_RESTO 0x14 /* expected response time out */ 497 #define MMC_RDTO 0x18 /* expected data read time out */ 498 #define MMC_BLKLEN 0x1c /* block length of data transaction */ 499 #define MMC_NOB 0x20 /* number of blocks (block mode) */ 500 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 501 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 502 #define MMC_I_MASK 0x28 /* interrupt mask */ 503 #define MMC_I_REG 0x2c /* interrupt register */ 504 #define MMC_I_DATA_TRAN_DONE (1<<0) 505 #define MMC_I_PRG_DONE (1<<1) 506 #define MMC_I_END_CMD_RES (1<<2) 507 #define MMC_I_STOP_CMD (1<<3) 508 #define MMC_I_CLK_IS_OFF (1<<4) 509 #define MMC_I_RXFIFO_RD_REQ (1<<5) 510 #define MMC_I_TXFIFO_WR_REQ (1<<6) 511 #define MMC_CMD 0x30 /* index of current command */ 512 #define MMC_ARGH 0x34 /* MSW part of the current command arg */ 513 #define MMC_ARGL 0x38 /* LSW part of the current command arg */ 514 #define MMC_RES 0x3c /* response FIFO */ 515 #define MMC_RXFIFO 0x40 /* receive FIFO */ 516 #define MMC_TXFIFO 0x44 /* transmit FIFO */ 517 518 /* 519 * AC97 520 */ 521 #define AC97_N_CODECS 2 522 #define AC97_GCR 0x000c /* Global control register */ 523 #define GCR_GIE (1<<0) /* interrupt enable */ 524 #define GCR_COLD_RST (1<<1) 525 #define GCR_WARM_RST (1<<2) 526 #define GCR_ACLINK_OFF (1<<3) 527 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 528 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 529 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 530 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 531 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 532 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 533 534 #define AC97_GSR 0x001c /* Global status register */ 535 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 536 #define GSR_MIINT (1<<1) /* modem in interrupt */ 537 #define GSR_MOINT (1<<2) /* modem out interrupt */ 538 #define GSR_PIINT (1<<5) /* PCM in interrupt */ 539 #define GSR_POINT (1<<6) /* PCM in interrupt */ 540 #define GSR_MINT (1<<7) /* Mic in interrupt */ 541 #define GSR_PCR (1<<8) /* primary code ready */ 542 #define GSR_SCR (1<<9) /* secondary code ready */ 543 #define GSR_PRIRES (1<<10) /* primary resume interrupt */ 544 #define GSR_SECRES (1<<11) /* secondary resume interrupt */ 545 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 546 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 547 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 548 #define GSR_RDCS (1<<15) /* Read completion status */ 549 #define GSR_SDONE (1<<18) /* status done */ 550 #define GSR_CDONE (1<<19) /* command done */ 551 552 #define AC97_POCR 0x0000 /* PCM-out control */ 553 #define AC97_PICR 0x0004 /* PCM-in control */ 554 #define AC97_POSR 0x0010 /* PCM-out status */ 555 #define AC97_PISR 0x0014 /* PCM-out status */ 556 #define AC97_MCCR 0x0008 /* MIC-in control register */ 557 #define AC97_MCSR 0x0018 /* MIC-in status register */ 558 #define AC97_MICR 0x0100 /* Modem-in control register */ 559 #define AC97_MISR 0x0108 /* Modem-in status register */ 560 #define AC97_MOCR 0x0110 /* Modem-in control register */ 561 #define AC97_MOSR 0x0118 /* Modem-out status register */ 562 #define AC97_FIFOE (1<<4) /* fifo error */ 563 564 #define AC97_CAR 0x0020 /* Codec access register */ 565 #define CAR_CAIP (1<<0) /* Codec access in progress */ 566 567 #define AC97_PCDR 0x0040 /* PCM data register */ 568 #define AC97_MCDR 0x0060 /* MIC-in data register */ 569 #define AC97_MODR 0x0060 /* Modem data register */ 570 571 /* address to access codec registers */ 572 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 573 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 574 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 575 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 576 #define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100)) 577 578 /* 579 * USB device controller 580 */ 581 #define USBDC_UDCCR 0x0000 /* UDC control register */ 582 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 583 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 584 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 585 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 586 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 587 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 588 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 589 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 590 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 591 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 592 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 593 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 594 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 595 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 596 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 597 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 598 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 599 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 600 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 601 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 602 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 603 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 604 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 605 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 606 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 607 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 608 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 609 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 610 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 611 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 612
Indexes created Tue Sep 30 11:09:46 GMT 2025