pxa2x0reg.h revision 1.6
1 /* $NetBSD: pxa2x0reg.h,v 1.6 2005/07/04 00:27:24 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCMCIA_SLOT0 0x20000000 66 #define PXA2X0_PCMCIA_SLOT1 0x30000000 67 68 #define PXA2X0_PERIPH_START 0x40000000 69 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 70 #define PXA270_PERIPH_END 0x530fffff 71 #define PXA250_PERIPH_END 0x480fffff 72 73 #define PXA2X0_SDRAM0_START 0xa0000000 74 #define PXA2X0_SDRAM1_START 0xa4000000 75 #define PXA2X0_SDRAM2_START 0xa8000000 76 #define PXA2X0_SDRAM3_START 0xac000000 77 #define PXA2X0_SDRAM_BANKS 4 78 #define PXA2X0_SDRAM_BANK_SIZE 0x04000000 79 80 /* 81 * Physical address of integrated peripherals 82 */ 83 84 #define PXA2X0_DMAC_BASE 0x40000000 85 #define PXA2X0_DMAC_SIZE 0x300 86 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 87 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 88 #define PXA2X0_I2C_BASE 0x40300000 89 #define PXA2X0_I2C_SIZE 0x000016a4 90 #define PXA2X0_I2S_BASE 0x40400000 91 #define PXA2X0_AC97_BASE 0x40500000 92 #define PXA2X0_AC97_SIZE 0x600 93 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client */ 94 #define PXA2X0_USBDC_SIZE 0x0e04 95 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 96 #define PXA2X0_ICP_BASE 0x40800000 97 #define PXA2X0_RTC_BASE 0x40900000 98 #define PXA2X0_RTC_SIZE 0x10 99 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 100 #define PXA2X0_PWM0_BASE 0x40b00000 101 #define PXA2X0_PWM1_BASE 0x40c00000 102 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 103 #define PXA2X0_INTCTL_SIZE 0x20 104 #define PXA2X0_GPIO_BASE 0x40e00000 105 106 #define PXA270_GPIO_SIZE 0x150 107 #define PXA250_GPIO_SIZE 0x70 108 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 109 #define PXA2X0_SSP_BASE 0x41000000 110 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 111 #define PXA2X0_MMC_SIZE 0x48 112 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 113 #define PXA2X0_CLKMAN_SIZE 12 114 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 115 #define PXA2X0_LCDC_SIZE 0x220 116 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 117 #define PXA2X0_MEMCTL_SIZE 0x48 118 #define PXA2X0_USBH_BASE 0x4c000000 /* USB Host controller */ 119 #define PXA2X0_USBH_SIZE 0x70 120 121 /* Internal SRAM storage. PXA27x only */ 122 #define PXA270_SRAM0_START 0x5c000000 123 #define PXA270_SRAM1_START 0x5c010000 124 #define PXA270_SRAM2_START 0x5c020000 125 #define PXA270_SRAM3_START 0x5c030000 126 #define PXA270_SRAM_BANKS 4 127 #define PXA270_SRAM_BANK_SIZE 0x00010000 128 129 /* width of interrupt controller */ 130 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 131 #define ICU_INT_HWMASK 0xffffff00 132 #define PXA250_IRQ_MIN 8 /* 0..7 are not used by integrated 133 peripherals */ 134 #define PXA270_IRQ_MIN 0 135 136 #define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */ 137 138 #define PXA2X0_INT_GPIO0 8 139 #define PXA2X0_INT_GPIO1 9 140 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 141 #define PXA2X0_INT_USB 11 142 #define PXA2X0_INT_PMU 12 143 #define PXA2X0_INT_I2S 13 144 #define PXA2X0_INT_AC97 14 145 #define PXA2X0_INT_LCD 17 146 #define PXA2X0_INT_I2C 18 147 #define PXA2X0_INT_ICP 19 148 #define PXA2X0_INT_STUART 20 149 #define PXA2X0_INT_BTUART 21 150 #define PXA2X0_INT_FFUART 22 151 #define PXA2X0_INT_MMC 23 152 #define PXA2X0_INT_SSP 24 153 #define PXA2X0_INT_DMA 25 154 #define PXA2X0_INT_OST0 26 155 #define PXA2X0_INT_OST1 27 156 #define PXA2X0_INT_OST2 28 157 #define PXA2X0_INT_OST3 29 158 #define PXA2X0_INT_RTCHZ 30 159 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 160 161 /* DMAC */ 162 #define DMAC_N_CHANNELS 16 163 #define DMAC_N_PRIORITIES 3 164 165 #define DMAC_DCSR(n) ((n)*4) 166 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 167 #define DCSR_STARTINR (1<<1) /* start interrupt */ 168 #define DCSR_ENDINTR (1<<2) /* end interrupt */ 169 #define DCSR_STOPSTATE (1<<3) /* channel is not running */ 170 #define DCSR_REQPEND (1<<8) /* request pending */ 171 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 172 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 173 #define DCSR_RUN (1<<31) 174 #define DMAC_DINT 0x00f0 /* DAM interrupt */ 175 #define DMAC_DINT_MASK 0xffffu 176 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 177 #define DRCMR_CHLNUM 0x0f /* channel number */ 178 #define DRCMR_MAPVLD (1<<7) /* map valid */ 179 #define DMAC_DDADR(n) (0x0200+(n)*16) 180 #define DDADR_STOP (1<<0) 181 #define DMAC_DSADR(n) (0x0204+(n)*16) 182 #define DMAC_DTADR(n) (0x0208+(n)*16) 183 #define DMAC_DCMD(n) (0x020c+(n)*16) 184 #define DCMD_LENGTH_MASK 0x1fff 185 #define DCMD_WIDTH_SHIFT 14 186 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 187 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 188 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 189 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 190 #define DCMD_SIZE_SHIFT 16 191 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 192 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 193 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 194 #define DCMD_LITTLE_ENDIEN (0<<18) 195 #define DCMD_ENDIRQEN (1<<21) 196 #define DCMD_STARTIRQEN (1<<22) 197 #define DCMD_FLOWTRG (1<<28) /* flow control by target */ 198 #define DCMD_FLOWSRC (1<<29) /* flow control by source */ 199 #define DCMD_INCTRGADDR (1<<30) /* increment target address */ 200 #define DCMD_INCSRCADDR (1<<31) /* increment source address */ 201 202 #ifndef __ASSEMBLER__ 203 /* DMA descriptor */ 204 struct pxa2x0_dma_desc { 205 volatile uint32_t dd_ddadr; 206 #define DMAC_DESC_LAST 0x1 207 volatile uint32_t dd_dsadr; 208 volatile uint32_t dd_dtadr; 209 volatile uint32_t dd_dcmd; /* command and length */ 210 }; 211 #endif 212 213 /* UART */ 214 #define PXA2X0_COM_FREQ 14745600L 215 216 /* I2C */ 217 #define I2C_IBMR 0x1680 /* Bus monitor register */ 218 #define I2C_IDBR 0x1688 /* Data buffer */ 219 #define I2C_ICR 0x1690 /* Control register */ 220 #define ICR_START (1<<0) 221 #define ICR_STOP (1<<1) 222 #define ICR_ACKNAK (1<<2) 223 #define ICR_TB (1<<3) 224 #define ICR_MA (1<<4) 225 #define I2C_ISR 0x1698 /* Status register */ 226 #define I2C_ISAR 0x16a0 /* Slave address */ 227 228 /* Clock Manager */ 229 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 230 #define CCCR_TURBO_X1 (2<<7) 231 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 232 #define CCCR_TURBO_X2 (4<<7) 233 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 234 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 235 #define CCCR_RUN_X1 (1<<5) 236 #define CCCR_RUN_X2 (2<<5) 237 #define CCCR_RUN_X4 (3<<5) 238 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 239 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 240 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 241 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 242 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 243 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 244 245 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 246 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 247 248 #define CCCR_N_SHIFT 7 249 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 250 #define CCCR_M_SHIFT 5 251 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 252 #define CCCR_L_MASK 0x1f 253 254 #define CKEN_PWM0 (1<<0) 255 #define CKEN_PWM1 (1<<1) 256 #define CKEN_AC97 (1<<2) 257 #define CKEN_SSP (1<<3) 258 #define CKEN_STUART (1<<5) 259 #define CKEN_FFUART (1<<6) 260 #define CKEN_BTUART (1<<7) 261 #define CKEN_I2S (1<<8) 262 #define CKEN_USBH (1<<10) 263 #define CKEN_USB (1<<11) 264 #define CKEN_MMC (1<<12) 265 #define CKEN_FICP (1<<13) 266 #define CKEN_I2C (1<<14) 267 #define CKEN_LCD (1<<16) 268 269 #define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */ 270 #define OSCC_OON (1<<1) /* 32.768KHz oscillator */ 271 272 /* 273 * RTC 274 */ 275 #define RTC_RCNR 0x0000 /* count register */ 276 #define RTC_RTAR 0x0004 /* alarm register */ 277 #define RTC_RTSR 0x0008 /* status register */ 278 #define RTC_RTTR 0x000c /* trim register */ 279 /* 280 * GPIO 281 */ 282 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 283 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 284 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 285 286 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 287 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 288 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 289 290 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 291 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 292 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 293 294 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 295 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 296 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 297 298 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 299 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 300 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 301 302 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 303 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 304 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 305 306 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 307 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 308 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 309 310 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 311 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 312 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 313 314 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 315 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 316 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 317 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 318 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 319 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 320 321 /* Only for PXA270 */ 322 #define GPIO_GAFR3_L 0x6c /* alternate function [111:96] */ 323 #define GPIO_GAFR3_U 0x70 /* alternate function [120:112] */ 324 325 #define GPIO_GPLR3 0x100 /* Level reg [120:96] */ 326 #define GPIO_GPDR3 0x10c /* dir reg [120:96] */ 327 #define GPIO_GPSR3 0x118 /* set reg [120:96] */ 328 #define GPIO_GPCR3 0x124 /* clear reg [120:96] */ 329 #define GPIO_GRER3 0x130 /* rising edge [120:96] */ 330 #define GPIO_GFER3 0x13c /* falling edge [120:96] */ 331 #define GPIO_GEDR3 0x148 /* edge detect [120:96] */ 332 333 /* a bit simpler if we don't support PXA270 */ 334 #define PXA250_GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4)) 335 #define PXA250_GPIO_NPINS 85 336 337 #define PXA270_GPIO_REG(r, pin) \ 338 (pin < 96 ? PXA250_GPIO_REG(r,pin) : ((r) + 0x100 + ((((pin)-96) / 32) * 4))) 339 #define PXA270_GPIO_NPINS 121 340 341 342 #define GPIO_BANK(pin) ((pin) / 32) 343 #define GPIO_BIT(pin) (1u << ((pin) & 0x1f)) 344 #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4)) 345 #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2) 346 347 #define GPIO_IN 0x00 /* Regular GPIO input pin */ 348 #define GPIO_OUT 0x10 /* Regular GPIO output pin */ 349 #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */ 350 #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */ 351 #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */ 352 #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */ 353 #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */ 354 #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */ 355 #define GPIO_SET 0x20 /* Initial state is Set */ 356 #define GPIO_CLR 0x00 /* Initial state is Clear */ 357 358 #define GPIO_FN_MASK 0x03 359 #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT) 360 #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET) 361 #define GPIO_FN(n) ((n) & GPIO_FN_MASK) 362 #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) 363 #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) 364 #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT) 365 366 /* 367 * memory controller 368 */ 369 370 #define MEMCTL_MDCNFG 0x0000 371 #define MDCNFG_DE0 (1<<0) 372 #define MDCNFG_DE1 (1<<1) 373 #define MDCNFD_DWID01_SHIFT 2 374 #define MDCNFD_DCAC01_SHIFT 3 375 #define MDCNFD_DRAC01_SHIFT 5 376 #define MDCNFD_DNB01_SHIFT 7 377 #define MDCNFG_DE2 (1<<16) 378 #define MDCNFG_DE3 (1<<17) 379 #define MDCNFD_DWID23_SHIFT 18 380 #define MDCNFD_DCAC23_SHIFT 19 381 #define MDCNFD_DRAC23_SHIFT 21 382 #define MDCNFD_DNB23_SHIFT 23 383 384 #define MDCNFD_DWID_MASK 0x1 385 #define MDCNFD_DCAC_MASK 0x3 386 #define MDCNFD_DRAC_MASK 0x3 387 #define MDCNFD_DNB_MASK 0x1 388 389 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 390 #define MDREFR_DRI 0xfff 391 #define MDREFR_E0PIN (1<<12) 392 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 393 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 394 #define MDREFR_E1PIN (1<<15) 395 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 396 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 397 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 398 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 399 #define MDREFR_APD (1<<20) /* Auto Power Down */ 400 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 401 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 402 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 403 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 404 405 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 406 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 407 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 408 #define MSC_RBUFF_SHIFT 15 /* return data buffer */ 409 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 410 #define MSC_RRR_SHIFT 12 /* recovery time */ 411 #define MSC_RRR (7<<MSC_RRR_SHIFT) 412 #define MSC_RDN_SHIFT 8 /* ROM delay next access */ 413 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 414 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 415 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 416 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 417 #define MSC_RBW (1<<MSC_RBW_SHIFT) 418 #define MSC_RT_SHIFT 0 /* type */ 419 #define MSC_RT (7<<MSC_RT_SHIFT) 420 #define MSC_RT_NONBURST 0 421 #define MSC_RT_SRAM 1 422 #define MSC_RT_BURST4 2 423 #define MSC_RT_BURST8 3 424 #define MSC_RT_VLIO 4 425 426 /* expansion memory timing configuration */ 427 #define MEMCTL_MCMEM(n) (0x28+4*(n)) 428 #define MEMCTL_MCATT(n) (0x30+4*(n)) 429 #define MEMCTL_MCIO(n) (0x38+4*(n)) 430 431 #define MC_HOLD_SHIFT 14 432 #define MC_ASST_SHIFT 7 433 #define MC_SET_SHIFT 0 434 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 435 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 436 437 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 438 #define MECR_NOS (1<<0) /* Number of sockets */ 439 #define MECR_CIT (1<<1) /* Card-is-there */ 440 441 #define MEMCTL_MDMRS 0x0040 442 443 /* 444 * LCD Controller 445 */ 446 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 447 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 448 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 449 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 450 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 451 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 452 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 453 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 454 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 455 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 456 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 457 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 458 #define LCCR0_BM (1U<<20) /* Branch Mask */ 459 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 460 461 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 462 463 464 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 465 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 466 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 467 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 468 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 469 #define LCDC_LCCR4 0x010 /* Controller Control Register 3 */ 470 #define LCDC_LCCR5 0x014 /* Controller Control Register 3 */ 471 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 472 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 473 #define LCDC_FBR2 0x028 /* DMA ch2 frame branch register */ 474 #define LCDC_FBR3 0x02c /* DMA ch3 frame branch register */ 475 #define LCDC_FBR4 0x030 /* DMA ch4 frame branch register */ 476 #define LCDC_LCSR1 0x034 /* controller status register 1 PXA27x only */ 477 #define LCDC_LCSR 0x038 /* controller status register */ 478 #define LCSR_LDD (1U<<0) /* LCD disable done */ 479 #define LCSR_SOF (1U<<1) /* Start of frame */ 480 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 481 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 482 #define LCDC_TCR 0x044 /* TMED Control Register */ 483 #define LCDC_OVL1C1 0x050 /* Overlay 1 control register 1 */ 484 #define LCDC_OVL1C2 0x060 /* Overlay 1 control register 2 */ 485 #define LCDC_OVL2C1 0x070 /* Overlay 1 control register 1 */ 486 #define LCDC_OVL2C2 0x080 /* Overlay 1 control register 2 */ 487 #define LCDC_CCR 0x090 /* Cursor control register */ 488 #define LCDC_CMDCR 0x100 /* Command control register */ 489 #define LCDC_PRSR 0x104 /* Panel read status register */ 490 #define LCDC_FBR5 0x110 /* DMA ch5 frame branch register */ 491 #define LCDC_FBR6 0x114 /* DMA ch6 frame branch register */ 492 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 493 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 494 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 495 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 496 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 497 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 498 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 499 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 500 #define LCDC_FDADR2 0x220 /* DMA ch2 frame descriptor address */ 501 #define LCDC_FSADR2 0x224 /* DMA ch2 frame source address */ 502 #define LCDC_FIDR2 0x228 /* DMA ch2 frame ID register */ 503 #define LCDC_LDCMD2 0x22c /* DMA ch2 command register */ 504 #define LCDC_FDADR3 0x230 /* DMA ch3 frame descriptor address */ 505 #define LCDC_FSADR3 0x234 /* DMA ch3 frame source address */ 506 #define LCDC_FIDR3 0x238 /* DMA ch3 frame ID register */ 507 #define LCDC_LDCMD3 0x23c /* DMA ch3 command register */ 508 #define LCDC_FDADR4 0x240 /* DMA ch4 frame descriptor address */ 509 #define LCDC_FSADR4 0x244 /* DMA ch4 frame source address */ 510 #define LCDC_FIDR4 0x248 /* DMA ch4 frame ID register */ 511 #define LCDC_LDCMD4 0x24c /* DMA ch4 command register */ 512 #define LCDC_FDADR5 0x250 /* DMA ch5 frame descriptor address */ 513 #define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */ 514 #define LCDC_FIDR5 0x258 /* DMA ch5 frame ID register */ 515 #define LCDC_LDCMD5 0x25c /* DMA ch5 command register */ 516 #define LCDC_FDADR6 0x260 /* DMA ch6 frame descriptor address */ 517 #define LCDC_FSADR6 0x264 /* DMA ch6 frame source address */ 518 #define LCDC_FIDR6 0x268 /* DMA ch6 frame ID register */ 519 #define LCDC_LDCMD6 0x26c /* DMA ch6 command register */ 520 #define LCDC_LCDBSCNTR 0x054 /* LCD buffer strength control register */ 521 522 /* 523 * MMC/SD controller 524 */ 525 #define MMC_STRPCL 0x00 /* start/stop MMC clock */ 526 #define STRPCL_NOOP 0 527 #define STRPCL_STOP 1 /* stop MMC clock */ 528 #define STRPCL_START 2 /* start MMC clock */ 529 #define MMC_STAT 0x04 /* status register */ 530 #define STAT_READ_TIME_OUT (1<<0) 531 #define STAT_TIMEOUT_RESPONSE (1<<1) 532 #define STAT_CRC_WRITE_ERROR (1<<2) 533 #define STAT_CRC_READ_ERROR (1<<3) 534 #define STAT_SPI_READ_ERROR_TOKEN (1<<4) 535 #define STAT_RES_CRC_ERR (1<<5) 536 #define STAT_XMIT_FIFO_EMPTY (1<<6) 537 #define STAT_RECV_FIFO_FULL (1<<7) 538 #define STAT_CLK_EN (1<<8) 539 #define STAT_DATA_TRAN_DONE (1<<11) 540 #define STAT_PRG_DONE (1<<12) 541 #define STAT_END_CMD_RES (1<<13) 542 #define MMC_CLKRT 0x08 /* MMC clock rate */ 543 #define CLKRT_20M 0 544 #define CLKRT_10M 1 545 #define CLKRT_5M 2 546 #define CLKRT_2_5M 3 547 #define CLKRT_1_25M 4 548 #define CLKRT_625K 5 549 #define CLKRT_312K 6 550 #define MMC_SPI 0x0c /* SPI mode control */ 551 #define SPI_EN (1<<0) /* enable SPI mode */ 552 #define SPI_CRC_ON (1<<1) /* enable CRC generation */ 553 #define SPI_CS_EN (1<<2) /* Enable CS[01] */ 554 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 555 #define MMC_CMDAT 0x10 /* command/response/data */ 556 #define CMDAT_RESPONSE_FORMAT 0x03 557 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 558 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 559 #define CMDAT_RESPONSE_FORMAT_R2 2 560 #define CMDAT_RESPONSE_FORMAT_R3 3 561 #define CMDAT_DATA_EN (1<<2) 562 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 563 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 564 #define CMDAT_BUSY (1<<5) /* busy signal is expected */ 565 #define CMDAT_INIT (1<<6) /* preceede command with 80 clocks */ 566 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 567 #define MMC_RESTO 0x14 /* expected response time out */ 568 #define MMC_RDTO 0x18 /* expected data read time out */ 569 #define MMC_BLKLEN 0x1c /* block length of data transaction */ 570 #define MMC_NOB 0x20 /* number of blocks (block mode) */ 571 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 572 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 573 #define MMC_I_MASK 0x28 /* interrupt mask */ 574 #define MMC_I_REG 0x2c /* interrupt register */ 575 #define MMC_I_DATA_TRAN_DONE (1<<0) 576 #define MMC_I_PRG_DONE (1<<1) 577 #define MMC_I_END_CMD_RES (1<<2) 578 #define MMC_I_STOP_CMD (1<<3) 579 #define MMC_I_CLK_IS_OFF (1<<4) 580 #define MMC_I_RXFIFO_RD_REQ (1<<5) 581 #define MMC_I_TXFIFO_WR_REQ (1<<6) 582 #define MMC_CMD 0x30 /* index of current command */ 583 #define MMC_ARGH 0x34 /* MSW part of the current command arg */ 584 #define MMC_ARGL 0x38 /* LSW part of the current command arg */ 585 #define MMC_RES 0x3c /* response FIFO */ 586 #define MMC_RXFIFO 0x40 /* receive FIFO */ 587 #define MMC_TXFIFO 0x44 /* transmit FIFO */ 588 589 /* 590 * AC97 591 */ 592 #define AC97_N_CODECS 2 593 #define AC97_GCR 0x000c /* Global control register */ 594 #define GCR_GIE (1<<0) /* interrupt enable */ 595 #define GCR_COLD_RST (1<<1) 596 #define GCR_WARM_RST (1<<2) 597 #define GCR_ACLINK_OFF (1<<3) 598 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 599 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 600 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 601 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 602 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 603 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 604 605 #define AC97_GSR 0x001c /* Global status register */ 606 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 607 #define GSR_MIINT (1<<1) /* modem in interrupt */ 608 #define GSR_MOINT (1<<2) /* modem out interrupt */ 609 #define GSR_PIINT (1<<5) /* PCM in interrupt */ 610 #define GSR_POINT (1<<6) /* PCM out interrupt */ 611 #define GSR_MINT (1<<7) /* Mic in interrupt */ 612 #define GSR_PCR (1<<8) /* primary code ready */ 613 #define GSR_SCR (1<<9) /* secondary code ready */ 614 #define GSR_PRIRES (1<<10) /* primary resume interrupt */ 615 #define GSR_SECRES (1<<11) /* secondary resume interrupt */ 616 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 617 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 618 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 619 #define GSR_RDCS (1<<15) /* Read completion status */ 620 #define GSR_SDONE (1<<18) /* status done */ 621 #define GSR_CDONE (1<<19) /* command done */ 622 623 #define AC97_POCR 0x0000 /* PCM-out control */ 624 #define AC97_PICR 0x0004 /* PCM-in control */ 625 #define AC97_POSR 0x0010 /* PCM-out status */ 626 #define AC97_PISR 0x0014 /* PCM-out status */ 627 #define AC97_MCCR 0x0008 /* MIC-in control register */ 628 #define AC97_MCSR 0x0018 /* MIC-in status register */ 629 #define AC97_MICR 0x0100 /* Modem-in control register */ 630 #define AC97_MISR 0x0108 /* Modem-in status register */ 631 #define AC97_MOCR 0x0110 /* Modem-out control register */ 632 #define AC97_MOSR 0x0118 /* Modem-out status register */ 633 #define AC97_FEFIE (1<<3) /* fifo error interrupt enable */ 634 #define AC97_FIFOE (1<<4) /* fifo error */ 635 636 #define AC97_CAR 0x0020 /* Codec access register */ 637 #define CAR_CAIP (1<<0) /* Codec access in progress */ 638 639 #define AC97_PCDR 0x0040 /* PCM data register */ 640 #define AC97_MCDR 0x0060 /* MIC-in data register */ 641 #define AC97_MODR 0x0140 /* Modem data register */ 642 643 /* address to access codec registers */ 644 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 645 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 646 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 647 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 648 #define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100)) 649 650 /* 651 * USB device controller 652 */ 653 #define USBDC_UDCCR 0x0000 /* UDC control register */ 654 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 655 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 656 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 657 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 658 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 659 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 660 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 661 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 662 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 663 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 664 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 665 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 666 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 667 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 668 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 669 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 670 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 671 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 672 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 673 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 674 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 675 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 676 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 677 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 678 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 679 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 680 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 681 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 682 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 683 684 #define USBHC_UHCRHDA 0x0048 /* UHC Root Hub Descriptor A */ 685 #define UHCRHDA_POTPGT_SHIFT 24 /* Power on to power good time */ 686 #define UHCRHDA_NOCP (1<<12) /* No over current protection */ 687 #define UHCRHDA_OCPM (1<<11) /* Over current protection mode */ 688 #define UHCRHDA_DT (1<<10) /* Device type */ 689 #define UHCRHDA_NPS (1<<9) /* No power switching */ 690 #define UHCRHDA_PSM (1<<8) /* Power switching mode */ 691 #define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */ 692 #define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */ 693 #define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */ 694 #define USBHC_UHCHR 0x0064 /* UHC Reset Register */ 695 #define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */ 696 #define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */ 697 #define UHCHR_SSEP1 (1<<9) /* Sleep standby enable for port1 */ 698 #define UHCHR_PCPL (1<<7) /* Power control polarity low */ 699 #define UHCHR_PSPL (1<<6) /* Power sense polarity low */ 700 #define UHCHR_SSE (1<<5) /* Sleep standby enable */ 701 #define UHCHR_UIT (1<<4) /* USB interrupt test */ 702 #define UHCHR_SSDC (1<<3) /* Simulation scale down clock */ 703 #define UHCHR_CGR (1<<2) /* Clock generation reset */ 704 #define UHCHR_FHR (1<<1) /* Force host controller reset */ 705 #define UHCHR_FSBIR (1<<0) /* Force system bus interface reset */ 706 #define UHCHR_MASK 0xeff 707 708 /* 709 * PWM controller 710 */ 711 #define PWM_PWMCR 0x0000 /* Control register */ 712 #define PWM_PWMDCR 0x0004 /* Duty cycle register */ 713 #define PWM_FD (1<<10) /* Full duty */ 714 #define PWM_PWMPCR 0x0008 /* Period register */ 715 716 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 717
Indexes created Tue Sep 30 07:10:03 GMT 2025