clock.c revision 1.27.6.3
1 /* $NetBSD: clock.c,v 1.27.6.3 2002/06/24 22:04:10 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: clock.c 1.18 91/01/21$ 41 * 42 * @(#)clock.c 7.6 (Berkeley) 5/7/91 43 */ 44 45 #include <sys/param.h> 46 #include <sys/kernel.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/uio.h> 50 #include <sys/conf.h> 51 #include <sys/lwp.h> 52 #include <sys/proc.h> 53 54 #include <dev/clock_subr.h> 55 56 #include <machine/psl.h> 57 #include <machine/cpu.h> 58 #include <machine/iomap.h> 59 #include <machine/mfp.h> 60 #include <atari/dev/clockreg.h> 61 #include <atari/atari/device.h> 62 63 #if defined(GPROF) && defined(PROFTIMER) 64 #include <machine/profile.h> 65 #endif 66 67 /* 68 * The MFP clock runs at 2457600Hz. We use a {system,stat,prof}clock divider 69 * of 200. Therefore the timer runs at an effective rate of: 70 * 2457600/200 = 12288Hz. 71 */ 72 #define CLOCK_HZ 12288 73 74 /* 75 * Machine-dependent clock routines. 76 * 77 * Inittodr initializes the time of day hardware which provides 78 * date functions. 79 * 80 * Resettodr restores the time of day hardware after a time change. 81 */ 82 83 struct clock_softc { 84 struct device sc_dev; 85 int sc_flags; 86 }; 87 88 /* 89 * 'sc_flags' state info. Only used by the rtc-device functions. 90 */ 91 #define RTC_OPEN 1 92 93 /* {b,c}devsw[] function prototypes for rtc functions */ 94 dev_type_open(rtcopen); 95 dev_type_close(rtcclose); 96 dev_type_read(rtcread); 97 dev_type_write(rtcwrite); 98 99 static void clockattach __P((struct device *, struct device *, void *)); 100 static int clockmatch __P((struct device *, struct cfdata *, void *)); 101 102 struct cfattach clock_ca = { 103 sizeof(struct clock_softc), clockmatch, clockattach 104 }; 105 106 extern struct cfdriver clock_cd; 107 108 void statintr __P((struct clockframe)); 109 110 static u_long gettod __P((void)); 111 static int twodigits __P((char *, int)); 112 113 static int divisor; /* Systemclock divisor */ 114 115 /* 116 * Statistics and profile clock intervals and variances. Variance must 117 * be a power of 2. Since this gives us an even number, not an odd number, 118 * we discard one case and compensate. That is, a variance of 64 would 119 * give us offsets in [0..63]. Instead, we take offsets in [1..63]. 120 * This is symmetric around the point 32, or statvar/2, and thus averages 121 * to that value (assuming uniform random numbers). 122 */ 123 #ifdef STATCLOCK 124 static int statvar = 32; /* {stat,prof}clock variance */ 125 static int statmin; /* statclock divisor - variance/2 */ 126 static int profmin; /* profclock divisor - variance/2 */ 127 static int clk2min; /* current, from above choices */ 128 #endif 129 130 int 131 clockmatch(pdp, cfp, auxp) 132 struct device *pdp; 133 struct cfdata *cfp; 134 void *auxp; 135 { 136 if (!atari_realconfig) { 137 /* 138 * Initialize Timer-B in the ST-MFP. This timer is used by 139 * the 'delay' function below. This timer is setup to be 140 * continueously counting from 255 back to zero at a 141 * frequency of 614400Hz. We do this *early* in the 142 * initialisation process. 143 */ 144 MFP->mf_tbcr = 0; /* Stop timer */ 145 MFP->mf_iera &= ~IA_TIMB; /* Disable timer interrupts */ 146 MFP->mf_tbdr = 0; 147 MFP->mf_tbcr = T_Q004; /* Start timer */ 148 149 /* 150 * Initialize the time structure 151 */ 152 time.tv_sec = 0; 153 time.tv_usec = 0; 154 155 return 0; 156 } 157 if(!strcmp("clock", auxp)) 158 return(1); 159 return(0); 160 } 161 162 /* 163 * Start the real-time clock. 164 */ 165 void clockattach(pdp, dp, auxp) 166 struct device *pdp, *dp; 167 void *auxp; 168 { 169 struct clock_softc *sc = (void *)dp; 170 171 sc->sc_flags = 0; 172 173 /* 174 * Initialize Timer-A in the ST-MFP. We use a divisor of 200. 175 * The MFP clock runs at 2457600Hz. Therefore the timer runs 176 * at an effective rate of: 2457600/200 = 12288Hz. The 177 * following expression works for 48, 64 or 96 hz. 178 */ 179 divisor = CLOCK_HZ/hz; 180 MFP->mf_tacr = 0; /* Stop timer */ 181 MFP->mf_iera &= ~IA_TIMA; /* Disable timer interrupts */ 182 MFP->mf_tadr = divisor; /* Set divisor */ 183 184 if (hz != 48 && hz != 64 && hz != 96) { /* XXX */ 185 printf (": illegal value %d for systemclock, reset to %d\n\t", 186 hz, 64); 187 hz = 64; 188 } 189 printf(": system hz %d timer-A divisor 200/%d\n", hz, divisor); 190 191 #ifdef STATCLOCK 192 if ((stathz == 0) || (stathz > hz) || (CLOCK_HZ % stathz)) 193 stathz = hz; 194 if ((profhz == 0) || (profhz > (hz << 1)) || (CLOCK_HZ % profhz)) 195 profhz = hz << 1; 196 197 MFP->mf_tcdcr &= 0x7; /* Stop timer */ 198 MFP->mf_ierb &= ~IB_TIMC; /* Disable timer inter. */ 199 MFP->mf_tcdr = CLOCK_HZ/stathz; /* Set divisor */ 200 201 statmin = (CLOCK_HZ/stathz) - (statvar >> 1); 202 profmin = (CLOCK_HZ/profhz) - (statvar >> 1); 203 clk2min = statmin; 204 #endif /* STATCLOCK */ 205 206 } 207 208 void cpu_initclocks() 209 { 210 MFP->mf_tacr = T_Q200; /* Start timer */ 211 MFP->mf_ipra = (u_int8_t)~IA_TIMA;/* Clear pending interrupts */ 212 MFP->mf_iera |= IA_TIMA; /* Enable timer interrupts */ 213 MFP->mf_imra |= IA_TIMA; /* ..... */ 214 215 #ifdef STATCLOCK 216 MFP->mf_tcdcr = (MFP->mf_tcdcr & 0x7) | (T_Q200<<4); /* Start */ 217 MFP->mf_iprb = (u_int8_t)~IB_TIMC;/* Clear pending interrupts */ 218 MFP->mf_ierb |= IB_TIMC; /* Enable timer interrupts */ 219 MFP->mf_imrb |= IB_TIMC; /* ..... */ 220 #endif /* STATCLOCK */ 221 } 222 223 void 224 setstatclockrate(newhz) 225 int newhz; 226 { 227 #ifdef STATCLOCK 228 if (newhz == stathz) 229 clk2min = statmin; 230 else clk2min = profmin; 231 #endif /* STATCLOCK */ 232 } 233 234 #ifdef STATCLOCK 235 void 236 statintr(frame) 237 struct clockframe frame; 238 { 239 register int var, r; 240 241 var = statvar - 1; 242 do { 243 r = random() & var; 244 } while(r == 0); 245 246 /* 247 * Note that we are always lagging behind as the new divisor 248 * value will not be loaded until the next interrupt. This 249 * shouldn't disturb the median frequency (I think ;-) ) as 250 * only the value used when switching frequencies is used 251 * twice. This shouldn't happen very often. 252 */ 253 MFP->mf_tcdr = clk2min + r; 254 255 statclock(&frame); 256 } 257 #endif /* STATCLOCK */ 258 259 /* 260 * Returns number of usec since last recorded clock "tick" 261 * (i.e. clock interrupt). 262 */ 263 long 264 clkread() 265 { 266 u_int delta; 267 u_char ipra, tadr; 268 269 /* 270 * Note: Order is important! 271 * By reading 'ipra' before 'tadr' and caching the data, I try to avoid 272 * the situation that very low value in 'tadr' is read (== a big delta) 273 * while also acccounting for a full 'tick' because the counter went 274 * through zero during the calculations. 275 */ 276 ipra = MFP->mf_ipra; tadr = MFP->mf_tadr; 277 278 delta = ((divisor - tadr) * tick) / divisor; 279 /* 280 * Account for pending clock interrupts 281 */ 282 if(ipra & IA_TIMA) 283 return(delta + tick); 284 return(delta); 285 } 286 287 #define TIMB_FREQ 614400 288 #define TIMB_LIMIT 256 289 290 /* 291 * Wait "n" microseconds. 292 * Relies on MFP-Timer B counting down from TIMB_LIMIT at TIMB_FREQ Hz. 293 * Note: timer had better have been programmed before this is first used! 294 */ 295 void 296 delay(n) 297 int n; 298 { 299 int tick, otick; 300 301 /* 302 * Read the counter first, so that the rest of the setup overhead is 303 * counted. 304 */ 305 otick = MFP->mf_tbdr; 306 307 /* 308 * Calculate ((n * TIMER_FREQ) / 1e6) using explicit assembler code so 309 * we can take advantage of the intermediate 64-bit quantity to prevent 310 * loss of significance. 311 */ 312 n -= 5; 313 if(n < 0) 314 return; 315 { 316 u_int temp; 317 318 __asm __volatile ("mulul %2,%1:%0" : "=d" (n), "=d" (temp) 319 : "d" (TIMB_FREQ), "d" (n)); 320 __asm __volatile ("divul %1,%2:%0" : "=d" (n) 321 : "d"(1000000),"d"(temp),"0"(n)); 322 } 323 324 while(n > 0) { 325 tick = MFP->mf_tbdr; 326 if(tick > otick) 327 n -= TIMB_LIMIT - (tick - otick); 328 else n -= otick - tick; 329 otick = tick; 330 } 331 } 332 333 #ifdef GPROF 334 /* 335 * profclock() is expanded in line in lev6intr() unless profiling kernel. 336 * Assumes it is called with clock interrupts blocked. 337 */ 338 profclock(pc, ps) 339 caddr_t pc; 340 int ps; 341 { 342 /* 343 * Came from user mode. 344 * If this process is being profiled record the tick. 345 */ 346 if (USERMODE(ps)) { 347 if (p->p_stats.p_prof.pr_scale) 348 addupc(pc, &curproc->p_stats.p_prof, 1); 349 } 350 /* 351 * Came from kernel (supervisor) mode. 352 * If we are profiling the kernel, record the tick. 353 */ 354 else if (profiling < 2) { 355 register int s = pc - s_lowpc; 356 357 if (s < s_textsize) 358 kcount[s / (HISTFRACTION * sizeof (*kcount))]++; 359 } 360 /* 361 * Kernel profiling was on but has been disabled. 362 * Mark as no longer profiling kernel and if all profiling done, 363 * disable the clock. 364 */ 365 if (profiling && (profon & PRF_KERNEL)) { 366 profon &= ~PRF_KERNEL; 367 if (profon == PRF_NONE) 368 stopprofclock(); 369 } 370 } 371 #endif 372 373 /*********************************************************************** 374 * Real Time Clock support * 375 ***********************************************************************/ 376 377 u_int mc146818_read(rtc, regno) 378 void *rtc; 379 u_int regno; 380 { 381 ((struct rtc *)rtc)->rtc_regno = regno; 382 return(((struct rtc *)rtc)->rtc_data & 0377); 383 } 384 385 void mc146818_write(rtc, regno, value) 386 void *rtc; 387 u_int regno, value; 388 { 389 ((struct rtc *)rtc)->rtc_regno = regno; 390 ((struct rtc *)rtc)->rtc_data = value; 391 } 392 393 /* 394 * Initialize the time of day register, assuming the RTC runs in UTC. 395 * Since we've got the 'rtc' device, this functionality should be removed 396 * from the kernel. The only problem to be solved before that can happen 397 * is the possibility of init(1) providing a way (rc.boot?) to set 398 * the RTC before single-user mode is entered. 399 */ 400 void 401 inittodr(base) 402 time_t base; 403 { 404 /* Battery clock does not store usec's, so forget about it. */ 405 time.tv_sec = gettod(); 406 time.tv_usec = 0; 407 } 408 409 /* 410 * Function turned into a No-op. Use /dev/rtc to update the RTC. 411 */ 412 void 413 resettodr() 414 { 415 return; 416 } 417 418 static u_long 419 gettod() 420 { 421 int sps; 422 mc_todregs clkregs; 423 u_int regb; 424 struct clock_ymdhms dt; 425 426 sps = splhigh(); 427 regb = mc146818_read(RTC, MC_REGB); 428 MC146818_GETTOD(RTC, &clkregs); 429 splx(sps); 430 431 regb &= MC_REGB_24HR|MC_REGB_BINARY; 432 if (regb != (MC_REGB_24HR|MC_REGB_BINARY)) { 433 printf("Error: Nonstandard RealTimeClock Configuration -" 434 " value ignored\n" 435 " A write to /dev/rtc will correct this.\n"); 436 return(0); 437 } 438 if(clkregs[MC_SEC] > 59) 439 return(0); 440 if(clkregs[MC_MIN] > 59) 441 return(0); 442 if(clkregs[MC_HOUR] > 23) 443 return(0); 444 if(range_test(clkregs[MC_DOM], 1, 31)) 445 return(0); 446 if (range_test(clkregs[MC_MONTH], 1, 12)) 447 return(0); 448 if(clkregs[MC_YEAR] > 99) 449 return(0); 450 451 dt.dt_year = clkregs[MC_YEAR] + GEMSTARTOFTIME; 452 dt.dt_mon = clkregs[MC_MONTH]; 453 dt.dt_day = clkregs[MC_DOM]; 454 dt.dt_hour = clkregs[MC_HOUR]; 455 dt.dt_min = clkregs[MC_MIN]; 456 dt.dt_sec = clkregs[MC_SEC]; 457 458 return(clock_ymdhms_to_secs(&dt)); 459 } 460 /*********************************************************************** 461 * RTC-device support * 462 ***********************************************************************/ 463 int 464 rtcopen(dev, flag, mode, p) 465 dev_t dev; 466 int flag, mode; 467 struct proc *p; 468 { 469 int unit = minor(dev); 470 struct clock_softc *sc; 471 472 if (unit >= clock_cd.cd_ndevs) 473 return ENXIO; 474 sc = clock_cd.cd_devs[unit]; 475 if (!sc) 476 return ENXIO; 477 if (sc->sc_flags & RTC_OPEN) 478 return EBUSY; 479 480 sc->sc_flags = RTC_OPEN; 481 return 0; 482 } 483 484 int 485 rtcclose(dev, flag, mode, p) 486 dev_t dev; 487 int flag; 488 int mode; 489 struct proc *p; 490 { 491 int unit = minor(dev); 492 struct clock_softc *sc = clock_cd.cd_devs[unit]; 493 494 sc->sc_flags = 0; 495 return 0; 496 } 497 498 int 499 rtcread(dev, uio, flags) 500 dev_t dev; 501 struct uio *uio; 502 int flags; 503 { 504 struct clock_softc *sc; 505 mc_todregs clkregs; 506 int s, length; 507 char buffer[16]; 508 509 sc = clock_cd.cd_devs[minor(dev)]; 510 511 s = splhigh(); 512 MC146818_GETTOD(RTC, &clkregs); 513 splx(s); 514 515 sprintf(buffer, "%4d%02d%02d%02d%02d.%02d\n", 516 clkregs[MC_YEAR] + GEMSTARTOFTIME, 517 clkregs[MC_MONTH], clkregs[MC_DOM], 518 clkregs[MC_HOUR], clkregs[MC_MIN], clkregs[MC_SEC]); 519 520 if (uio->uio_offset > strlen(buffer)) 521 return 0; 522 523 length = strlen(buffer) - uio->uio_offset; 524 if (length > uio->uio_resid) 525 length = uio->uio_resid; 526 527 return(uiomove((caddr_t)buffer, length, uio)); 528 } 529 530 static int 531 twodigits(buffer, pos) 532 char *buffer; 533 int pos; 534 { 535 int result = 0; 536 537 if (buffer[pos] >= '0' && buffer[pos] <= '9') 538 result = (buffer[pos] - '0') * 10; 539 if (buffer[pos+1] >= '0' && buffer[pos+1] <= '9') 540 result += (buffer[pos+1] - '0'); 541 return(result); 542 } 543 544 int 545 rtcwrite(dev, uio, flags) 546 dev_t dev; 547 struct uio *uio; 548 int flags; 549 { 550 mc_todregs clkregs; 551 int s, length, error; 552 char buffer[16]; 553 554 /* 555 * We require atomic updates! 556 */ 557 length = uio->uio_resid; 558 if (uio->uio_offset || (length != sizeof(buffer) 559 && length != sizeof(buffer - 1))) 560 return(EINVAL); 561 562 if ((error = uiomove((caddr_t)buffer, sizeof(buffer), uio))) 563 return(error); 564 565 if (length == sizeof(buffer) && buffer[sizeof(buffer) - 1] != '\n') 566 return(EINVAL); 567 568 s = splclock(); 569 mc146818_write(RTC, MC_REGB, 570 mc146818_read(RTC, MC_REGB) | MC_REGB_24HR | MC_REGB_BINARY); 571 MC146818_GETTOD(RTC, &clkregs); 572 splx(s); 573 574 clkregs[MC_SEC] = twodigits(buffer, 13); 575 clkregs[MC_MIN] = twodigits(buffer, 10); 576 clkregs[MC_HOUR] = twodigits(buffer, 8); 577 clkregs[MC_DOM] = twodigits(buffer, 6); 578 clkregs[MC_MONTH] = twodigits(buffer, 4); 579 s = twodigits(buffer, 0) * 100 + twodigits(buffer, 2); 580 clkregs[MC_YEAR] = s - GEMSTARTOFTIME; 581 582 s = splclock(); 583 MC146818_PUTTOD(RTC, &clkregs); 584 splx(s); 585 586 return(0); 587 } 588
Indexes created Tue Sep 30 17:09:57 GMT 2025