clock.c revision 1.30
1 /* $NetBSD: clock.c,v 1.30 2002/10/02 05:04:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: clock.c 1.18 91/01/21$ 41 * 42 * @(#)clock.c 7.6 (Berkeley) 5/7/91 43 */ 44 45 #include <sys/param.h> 46 #include <sys/kernel.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/uio.h> 50 #include <sys/conf.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <machine/psl.h> 55 #include <machine/cpu.h> 56 #include <machine/iomap.h> 57 #include <machine/mfp.h> 58 #include <atari/dev/clockreg.h> 59 #include <atari/atari/device.h> 60 61 #if defined(GPROF) && defined(PROFTIMER) 62 #include <machine/profile.h> 63 #endif 64 65 /* 66 * The MFP clock runs at 2457600Hz. We use a {system,stat,prof}clock divider 67 * of 200. Therefore the timer runs at an effective rate of: 68 * 2457600/200 = 12288Hz. 69 */ 70 #define CLOCK_HZ 12288 71 72 /* 73 * Machine-dependent clock routines. 74 * 75 * Inittodr initializes the time of day hardware which provides 76 * date functions. 77 * 78 * Resettodr restores the time of day hardware after a time change. 79 */ 80 81 struct clock_softc { 82 struct device sc_dev; 83 int sc_flags; 84 }; 85 86 /* 87 * 'sc_flags' state info. Only used by the rtc-device functions. 88 */ 89 #define RTC_OPEN 1 90 91 dev_type_open(rtcopen); 92 dev_type_close(rtcclose); 93 dev_type_read(rtcread); 94 dev_type_write(rtcwrite); 95 96 static void clockattach __P((struct device *, struct device *, void *)); 97 static int clockmatch __P((struct device *, struct cfdata *, void *)); 98 99 CFATTACH_DECL(clock, sizeof(struct clock_softc), 100 clockmatch, clockattach, NULL, NULL); 101 102 extern struct cfdriver clock_cd; 103 104 const struct cdevsw rtc_cdevsw = { 105 rtcopen, rtcclose, rtcread, rtcwrite, noioctl, 106 nostop, notty, nopoll, nommap, 107 }; 108 109 void statintr __P((struct clockframe)); 110 111 static u_long gettod __P((void)); 112 static int twodigits __P((char *, int)); 113 114 static int divisor; /* Systemclock divisor */ 115 116 /* 117 * Statistics and profile clock intervals and variances. Variance must 118 * be a power of 2. Since this gives us an even number, not an odd number, 119 * we discard one case and compensate. That is, a variance of 64 would 120 * give us offsets in [0..63]. Instead, we take offsets in [1..63]. 121 * This is symmetric around the point 32, or statvar/2, and thus averages 122 * to that value (assuming uniform random numbers). 123 */ 124 #ifdef STATCLOCK 125 static int statvar = 32; /* {stat,prof}clock variance */ 126 static int statmin; /* statclock divisor - variance/2 */ 127 static int profmin; /* profclock divisor - variance/2 */ 128 static int clk2min; /* current, from above choices */ 129 #endif 130 131 int 132 clockmatch(pdp, cfp, auxp) 133 struct device *pdp; 134 struct cfdata *cfp; 135 void *auxp; 136 { 137 if (!atari_realconfig) { 138 /* 139 * Initialize Timer-B in the ST-MFP. This timer is used by 140 * the 'delay' function below. This timer is setup to be 141 * continueously counting from 255 back to zero at a 142 * frequency of 614400Hz. We do this *early* in the 143 * initialisation process. 144 */ 145 MFP->mf_tbcr = 0; /* Stop timer */ 146 MFP->mf_iera &= ~IA_TIMB; /* Disable timer interrupts */ 147 MFP->mf_tbdr = 0; 148 MFP->mf_tbcr = T_Q004; /* Start timer */ 149 150 /* 151 * Initialize the time structure 152 */ 153 time.tv_sec = 0; 154 time.tv_usec = 0; 155 156 return 0; 157 } 158 if(!strcmp("clock", auxp)) 159 return(1); 160 return(0); 161 } 162 163 /* 164 * Start the real-time clock. 165 */ 166 void clockattach(pdp, dp, auxp) 167 struct device *pdp, *dp; 168 void *auxp; 169 { 170 struct clock_softc *sc = (void *)dp; 171 172 sc->sc_flags = 0; 173 174 /* 175 * Initialize Timer-A in the ST-MFP. We use a divisor of 200. 176 * The MFP clock runs at 2457600Hz. Therefore the timer runs 177 * at an effective rate of: 2457600/200 = 12288Hz. The 178 * following expression works for 48, 64 or 96 hz. 179 */ 180 divisor = CLOCK_HZ/hz; 181 MFP->mf_tacr = 0; /* Stop timer */ 182 MFP->mf_iera &= ~IA_TIMA; /* Disable timer interrupts */ 183 MFP->mf_tadr = divisor; /* Set divisor */ 184 185 if (hz != 48 && hz != 64 && hz != 96) { /* XXX */ 186 printf (": illegal value %d for systemclock, reset to %d\n\t", 187 hz, 64); 188 hz = 64; 189 } 190 printf(": system hz %d timer-A divisor 200/%d\n", hz, divisor); 191 192 #ifdef STATCLOCK 193 if ((stathz == 0) || (stathz > hz) || (CLOCK_HZ % stathz)) 194 stathz = hz; 195 if ((profhz == 0) || (profhz > (hz << 1)) || (CLOCK_HZ % profhz)) 196 profhz = hz << 1; 197 198 MFP->mf_tcdcr &= 0x7; /* Stop timer */ 199 MFP->mf_ierb &= ~IB_TIMC; /* Disable timer inter. */ 200 MFP->mf_tcdr = CLOCK_HZ/stathz; /* Set divisor */ 201 202 statmin = (CLOCK_HZ/stathz) - (statvar >> 1); 203 profmin = (CLOCK_HZ/profhz) - (statvar >> 1); 204 clk2min = statmin; 205 #endif /* STATCLOCK */ 206 207 } 208 209 void cpu_initclocks() 210 { 211 MFP->mf_tacr = T_Q200; /* Start timer */ 212 MFP->mf_ipra = (u_int8_t)~IA_TIMA;/* Clear pending interrupts */ 213 MFP->mf_iera |= IA_TIMA; /* Enable timer interrupts */ 214 MFP->mf_imra |= IA_TIMA; /* ..... */ 215 216 #ifdef STATCLOCK 217 MFP->mf_tcdcr = (MFP->mf_tcdcr & 0x7) | (T_Q200<<4); /* Start */ 218 MFP->mf_iprb = (u_int8_t)~IB_TIMC;/* Clear pending interrupts */ 219 MFP->mf_ierb |= IB_TIMC; /* Enable timer interrupts */ 220 MFP->mf_imrb |= IB_TIMC; /* ..... */ 221 #endif /* STATCLOCK */ 222 } 223 224 void 225 setstatclockrate(newhz) 226 int newhz; 227 { 228 #ifdef STATCLOCK 229 if (newhz == stathz) 230 clk2min = statmin; 231 else clk2min = profmin; 232 #endif /* STATCLOCK */ 233 } 234 235 #ifdef STATCLOCK 236 void 237 statintr(frame) 238 struct clockframe frame; 239 { 240 register int var, r; 241 242 var = statvar - 1; 243 do { 244 r = random() & var; 245 } while(r == 0); 246 247 /* 248 * Note that we are always lagging behind as the new divisor 249 * value will not be loaded until the next interrupt. This 250 * shouldn't disturb the median frequency (I think ;-) ) as 251 * only the value used when switching frequencies is used 252 * twice. This shouldn't happen very often. 253 */ 254 MFP->mf_tcdr = clk2min + r; 255 256 statclock(&frame); 257 } 258 #endif /* STATCLOCK */ 259 260 /* 261 * Returns number of usec since last recorded clock "tick" 262 * (i.e. clock interrupt). 263 */ 264 long 265 clkread() 266 { 267 u_int delta; 268 u_char ipra, tadr; 269 270 /* 271 * Note: Order is important! 272 * By reading 'ipra' before 'tadr' and caching the data, I try to avoid 273 * the situation that very low value in 'tadr' is read (== a big delta) 274 * while also acccounting for a full 'tick' because the counter went 275 * through zero during the calculations. 276 */ 277 ipra = MFP->mf_ipra; tadr = MFP->mf_tadr; 278 279 delta = ((divisor - tadr) * tick) / divisor; 280 /* 281 * Account for pending clock interrupts 282 */ 283 if(ipra & IA_TIMA) 284 return(delta + tick); 285 return(delta); 286 } 287 288 #define TIMB_FREQ 614400 289 #define TIMB_LIMIT 256 290 291 /* 292 * Wait "n" microseconds. 293 * Relies on MFP-Timer B counting down from TIMB_LIMIT at TIMB_FREQ Hz. 294 * Note: timer had better have been programmed before this is first used! 295 */ 296 void 297 delay(n) 298 int n; 299 { 300 int tick, otick; 301 302 /* 303 * Read the counter first, so that the rest of the setup overhead is 304 * counted. 305 */ 306 otick = MFP->mf_tbdr; 307 308 /* 309 * Calculate ((n * TIMER_FREQ) / 1e6) using explicit assembler code so 310 * we can take advantage of the intermediate 64-bit quantity to prevent 311 * loss of significance. 312 */ 313 n -= 5; 314 if(n < 0) 315 return; 316 { 317 u_int temp; 318 319 __asm __volatile ("mulul %2,%1:%0" : "=d" (n), "=d" (temp) 320 : "d" (TIMB_FREQ), "d" (n)); 321 __asm __volatile ("divul %1,%2:%0" : "=d" (n) 322 : "d"(1000000),"d"(temp),"0"(n)); 323 } 324 325 while(n > 0) { 326 tick = MFP->mf_tbdr; 327 if(tick > otick) 328 n -= TIMB_LIMIT - (tick - otick); 329 else n -= otick - tick; 330 otick = tick; 331 } 332 } 333 334 #ifdef GPROF 335 /* 336 * profclock() is expanded in line in lev6intr() unless profiling kernel. 337 * Assumes it is called with clock interrupts blocked. 338 */ 339 profclock(pc, ps) 340 caddr_t pc; 341 int ps; 342 { 343 /* 344 * Came from user mode. 345 * If this process is being profiled record the tick. 346 */ 347 if (USERMODE(ps)) { 348 if (p->p_stats.p_prof.pr_scale) 349 addupc(pc, &curproc->p_stats.p_prof, 1); 350 } 351 /* 352 * Came from kernel (supervisor) mode. 353 * If we are profiling the kernel, record the tick. 354 */ 355 else if (profiling < 2) { 356 register int s = pc - s_lowpc; 357 358 if (s < s_textsize) 359 kcount[s / (HISTFRACTION * sizeof (*kcount))]++; 360 } 361 /* 362 * Kernel profiling was on but has been disabled. 363 * Mark as no longer profiling kernel and if all profiling done, 364 * disable the clock. 365 */ 366 if (profiling && (profon & PRF_KERNEL)) { 367 profon &= ~PRF_KERNEL; 368 if (profon == PRF_NONE) 369 stopprofclock(); 370 } 371 } 372 #endif 373 374 /*********************************************************************** 375 * Real Time Clock support * 376 ***********************************************************************/ 377 378 u_int mc146818_read(rtc, regno) 379 void *rtc; 380 u_int regno; 381 { 382 ((struct rtc *)rtc)->rtc_regno = regno; 383 return(((struct rtc *)rtc)->rtc_data & 0377); 384 } 385 386 void mc146818_write(rtc, regno, value) 387 void *rtc; 388 u_int regno, value; 389 { 390 ((struct rtc *)rtc)->rtc_regno = regno; 391 ((struct rtc *)rtc)->rtc_data = value; 392 } 393 394 /* 395 * Initialize the time of day register, assuming the RTC runs in UTC. 396 * Since we've got the 'rtc' device, this functionality should be removed 397 * from the kernel. The only problem to be solved before that can happen 398 * is the possibility of init(1) providing a way (rc.boot?) to set 399 * the RTC before single-user mode is entered. 400 */ 401 void 402 inittodr(base) 403 time_t base; 404 { 405 /* Battery clock does not store usec's, so forget about it. */ 406 time.tv_sec = gettod(); 407 time.tv_usec = 0; 408 } 409 410 /* 411 * Function turned into a No-op. Use /dev/rtc to update the RTC. 412 */ 413 void 414 resettodr() 415 { 416 return; 417 } 418 419 static u_long 420 gettod() 421 { 422 int sps; 423 mc_todregs clkregs; 424 u_int regb; 425 struct clock_ymdhms dt; 426 427 sps = splhigh(); 428 regb = mc146818_read(RTC, MC_REGB); 429 MC146818_GETTOD(RTC, &clkregs); 430 splx(sps); 431 432 regb &= MC_REGB_24HR|MC_REGB_BINARY; 433 if (regb != (MC_REGB_24HR|MC_REGB_BINARY)) { 434 printf("Error: Nonstandard RealTimeClock Configuration -" 435 " value ignored\n" 436 " A write to /dev/rtc will correct this.\n"); 437 return(0); 438 } 439 if(clkregs[MC_SEC] > 59) 440 return(0); 441 if(clkregs[MC_MIN] > 59) 442 return(0); 443 if(clkregs[MC_HOUR] > 23) 444 return(0); 445 if(range_test(clkregs[MC_DOM], 1, 31)) 446 return(0); 447 if (range_test(clkregs[MC_MONTH], 1, 12)) 448 return(0); 449 if(clkregs[MC_YEAR] > 99) 450 return(0); 451 452 dt.dt_year = clkregs[MC_YEAR] + GEMSTARTOFTIME; 453 dt.dt_mon = clkregs[MC_MONTH]; 454 dt.dt_day = clkregs[MC_DOM]; 455 dt.dt_hour = clkregs[MC_HOUR]; 456 dt.dt_min = clkregs[MC_MIN]; 457 dt.dt_sec = clkregs[MC_SEC]; 458 459 return(clock_ymdhms_to_secs(&dt)); 460 } 461 /*********************************************************************** 462 * RTC-device support * 463 ***********************************************************************/ 464 int 465 rtcopen(dev, flag, mode, p) 466 dev_t dev; 467 int flag, mode; 468 struct proc *p; 469 { 470 int unit = minor(dev); 471 struct clock_softc *sc; 472 473 if (unit >= clock_cd.cd_ndevs) 474 return ENXIO; 475 sc = clock_cd.cd_devs[unit]; 476 if (!sc) 477 return ENXIO; 478 if (sc->sc_flags & RTC_OPEN) 479 return EBUSY; 480 481 sc->sc_flags = RTC_OPEN; 482 return 0; 483 } 484 485 int 486 rtcclose(dev, flag, mode, p) 487 dev_t dev; 488 int flag; 489 int mode; 490 struct proc *p; 491 { 492 int unit = minor(dev); 493 struct clock_softc *sc = clock_cd.cd_devs[unit]; 494 495 sc->sc_flags = 0; 496 return 0; 497 } 498 499 int 500 rtcread(dev, uio, flags) 501 dev_t dev; 502 struct uio *uio; 503 int flags; 504 { 505 struct clock_softc *sc; 506 mc_todregs clkregs; 507 int s, length; 508 char buffer[16]; 509 510 sc = clock_cd.cd_devs[minor(dev)]; 511 512 s = splhigh(); 513 MC146818_GETTOD(RTC, &clkregs); 514 splx(s); 515 516 sprintf(buffer, "%4d%02d%02d%02d%02d.%02d\n", 517 clkregs[MC_YEAR] + GEMSTARTOFTIME, 518 clkregs[MC_MONTH], clkregs[MC_DOM], 519 clkregs[MC_HOUR], clkregs[MC_MIN], clkregs[MC_SEC]); 520 521 if (uio->uio_offset > strlen(buffer)) 522 return 0; 523 524 length = strlen(buffer) - uio->uio_offset; 525 if (length > uio->uio_resid) 526 length = uio->uio_resid; 527 528 return(uiomove((caddr_t)buffer, length, uio)); 529 } 530 531 static int 532 twodigits(buffer, pos) 533 char *buffer; 534 int pos; 535 { 536 int result = 0; 537 538 if (buffer[pos] >= '0' && buffer[pos] <= '9') 539 result = (buffer[pos] - '0') * 10; 540 if (buffer[pos+1] >= '0' && buffer[pos+1] <= '9') 541 result += (buffer[pos+1] - '0'); 542 return(result); 543 } 544 545 int 546 rtcwrite(dev, uio, flags) 547 dev_t dev; 548 struct uio *uio; 549 int flags; 550 { 551 mc_todregs clkregs; 552 int s, length, error; 553 char buffer[16]; 554 555 /* 556 * We require atomic updates! 557 */ 558 length = uio->uio_resid; 559 if (uio->uio_offset || (length != sizeof(buffer) 560 && length != sizeof(buffer - 1))) 561 return(EINVAL); 562 563 if ((error = uiomove((caddr_t)buffer, sizeof(buffer), uio))) 564 return(error); 565 566 if (length == sizeof(buffer) && buffer[sizeof(buffer) - 1] != '\n') 567 return(EINVAL); 568 569 s = splclock(); 570 mc146818_write(RTC, MC_REGB, 571 mc146818_read(RTC, MC_REGB) | MC_REGB_24HR | MC_REGB_BINARY); 572 MC146818_GETTOD(RTC, &clkregs); 573 splx(s); 574 575 clkregs[MC_SEC] = twodigits(buffer, 13); 576 clkregs[MC_MIN] = twodigits(buffer, 10); 577 clkregs[MC_HOUR] = twodigits(buffer, 8); 578 clkregs[MC_DOM] = twodigits(buffer, 6); 579 clkregs[MC_MONTH] = twodigits(buffer, 4); 580 s = twodigits(buffer, 0) * 100 + twodigits(buffer, 2); 581 clkregs[MC_YEAR] = s - GEMSTARTOFTIME; 582 583 s = splclock(); 584 MC146818_PUTTOD(RTC, &clkregs); 585 splx(s); 586 587 return(0); 588 } 589
Indexes created Sun Sep 21 15:09:59 GMT 2025