ncr5380reg.h revision 1.1
1 /* $NetBSD: ncr5380reg.h,v 1.1 1995/03/26 07:12:15 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Leo Weppelman. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Leo Weppelman. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _NCR5380REG_H 34 #define _NCR5380REG_H 35 /* 36 * Atari TT hardware: 37 * SCSI interface + DMA. 38 * The SCSI chip is an NCR5380 39 */ 40 41 42 #define SCSI_DMA ((struct scsi_dma *)AD_SCSI_DMA) 43 #define SCSI_5380 ((struct scsi_5380 *)AD_NCR5380) 44 45 struct scsi_dma { 46 volatile u_char s_dma_ptr[8]; /* use only the odd bytes */ 47 volatile u_char s_dma_cnt[8]; /* use only the odd bytes */ 48 volatile u_char s_dma_res[4]; /* data residue register */ 49 volatile u_char s_dma_gap; /* not used */ 50 volatile u_char s_dma_ctrl; /* control register */ 51 }; 52 53 #define set_scsi_dma(addr, val) (void)( \ 54 { \ 55 u_char *address = (u_char*)addr+1; \ 56 u_long nval = (u_long)val; \ 57 __asm("movepl %0, %1@(0)": :"d" (nval), "a" (address)); \ 58 }) 59 60 #define get_scsi_dma(addr, res) ( \ 61 { \ 62 u_char *address = (u_char*)addr+1; \ 63 u_long nval; \ 64 __asm("movepl %1@(0), %0": "=d" (nval) : "a" (address)); \ 65 res = (u_long)nval; \ 66 }) 67 68 /* 69 * Defines for DMA control register 70 */ 71 #define SD_BUSERR 0x80 /* 1 = transfer caused bus error*/ 72 #define SD_ZERO 0x40 /* 1 = byte counter is zero */ 73 #define SD_ENABLE 0x02 /* 1 = Enable DMA */ 74 #define SD_OUT 0x01 /* Direction: memory to SCSI */ 75 #define SD_IN 0x00 /* Direction: SCSI to memory */ 76 77 struct scsi_5380 { 78 volatile u_char scsi_5380[16]; /* use only the odd bytes */ 79 }; 80 81 #define scsi_data scsi_5380[ 1] /* Data register */ 82 #define scsi_icom scsi_5380[ 3] /* Initiator command register */ 83 #define scsi_mode scsi_5380[ 5] /* Mode register */ 84 #define scsi_tcom scsi_5380[ 7] /* Target command register */ 85 #define scsi_idstat scsi_5380[ 9] /* Bus status register */ 86 #define scsi_dmstat scsi_5380[11] /* DMA status register */ 87 #define scsi_trcv scsi_5380[13] /* Target receive register */ 88 #define scsi_ircv scsi_5380[15] /* Initiator receive register */ 89 90 /* 91 * Definitions for Initiator command register. 92 */ 93 #define SC_A_RST 0x80 /* RW - Assert RST */ 94 #define SC_TEST 0x40 /* W - Test mode */ 95 #define SC_AIP 0x40 /* R - Arbitration in progress */ 96 #define SC_LA 0x20 /* R - Lost arbitration */ 97 #define SC_A_ACK 0x10 /* RW - Assert ACK */ 98 #define SC_A_BSY 0x08 /* RW - Assert BSY */ 99 #define SC_A_SEL 0x04 /* RW - Assert SEL */ 100 #define SC_A_ATN 0x02 /* RW - Assert ATN */ 101 #define SC_ADTB 0x01 /* RW - Assert Data To Bus */ 102 103 /* 104 * Definitions for mode register 105 */ 106 #define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */ 107 #define SC_T_MODE 0x40 /* RW - Target mode */ 108 #define SC_E_PAR 0x20 /* RW - Enable parity check */ 109 #define SC_E_PARI 0x10 /* RW - Enable parity interrupt */ 110 #define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */ 111 #define SC_MON_BSY 0x04 /* RW - Monitor BSY */ 112 #define SC_M_DMA 0x02 /* RW - Set DMA mode */ 113 #define SC_ARBIT 0x01 /* RW - Arbitrate */ 114 115 /* 116 * Definitions for tcom register 117 */ 118 #define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */ 119 #define SC_A_REQ 0x08 /* RW - Assert REQ */ 120 #define SC_A_MSG 0x04 /* RW - Assert MSG */ 121 #define SC_A_CD 0x02 /* RW - Assert C/D */ 122 #define SC_A_IO 0x01 /* RW - Assert I/O */ 123 124 /* 125 * Definitions for idstat register 126 */ 127 #define SC_S_RST 0x80 /* R - RST is set */ 128 #define SC_S_BSY 0x40 /* R - BSY is set */ 129 #define SC_S_REQ 0x20 /* R - REQ is set */ 130 #define SC_S_MSG 0x10 /* R - MSG is set */ 131 #define SC_S_CD 0x08 /* R - C/D is set */ 132 #define SC_S_IO 0x04 /* R - I/O is set */ 133 #define SC_S_SEL 0x02 /* R - SEL is set */ 134 #define SC_S_PAR 0x01 /* R - Parity bit */ 135 136 /* 137 * Definitions for dmastat register 138 */ 139 #define SC_END_DMA 0x80 /* R - End of DMA */ 140 #define SC_DMA_REQ 0x40 /* R - DMA request */ 141 #define SC_PAR_ERR 0x20 /* R - Parity error */ 142 #define SC_IRQ_SET 0x10 /* R - IRQ is active */ 143 #define SC_PHS_MTCH 0x08 /* R - Phase Match */ 144 #define SC_BSY_ERR 0x04 /* R - Busy error */ 145 #define SC_ATN_STAT 0x02 /* R - State of ATN line */ 146 #define SC_ACK_STAT 0x01 /* R - State of ACK line */ 147 #define SC_S_SEND 0x00 /* W - Start DMA output */ 148 149 #define SC_CLINT { /* Clear interrupts */ \ 150 int i = SCSI_5380->scsi_ircv; \ 151 } 152 153 154 /* 155 * Definition of SCSI-bus phases. The values are determined by signals 156 * on the SCSI-bus. DO NOT CHANGE! 157 * The values must be used to index the pointers in SCSI-PARMS. 158 */ 159 #define NR_PHASE 8 160 #define PH_DATAOUT 0 161 #define PH_DATAIN 1 162 #define PH_CMD 2 163 #define PH_STATUS 3 164 #define PH_RES1 4 165 #define PH_RES2 5 166 #define PH_MSGOUT 6 167 #define PH_MSGIN 7 168 169 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */ 170 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */ 171 172 /* 173 * Id of Host-adapter 174 */ 175 #define SC_HOST_ID 0x80 176 177 /* 178 * Base setting for 5380 mode register 179 */ 180 #define IMODE_BASE SC_E_PAR 181 182 #endif /* _NCR5380REG_H */ 183
Indexes created Sun Sep 28 12:09:53 GMT 2025